KR20000032450A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to acquire a margin of short channel characteristic of PMOS(P-type Metal Oxide Semiconductor) without a mask. CONSTITUTION: In processes for manufacturing a PMOS transistor, a gate electrode(23a) is formed at a predetermined area on a semiconductor substrate(1). Next, dopant areas of low density are formed at two sides of the gate electrode(23a). Next, side wall spacers(27) are formed at two side-faces of the gate electrode(23a). Next, by a heat-oxidation process, an insulation layer is formed on the gate electrode(23a), side wall spacers(27) and the semiconductor substrate(1), and diffusion is enhanced to a channel in the dopant areas of low density. Next, by injection of high density dopants, dopant areas of source and drain are formed at two sides of the gate electrode(23a).

Description

Semiconductor device manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a method for manufacturing a semiconductor device suitable for improving short channel characteristics.

BACKGROUND ART In general, in semiconductor integrated circuits, research for reducing the size of a transistor constituting a semiconductor integrated circuit has been continued to obtain a highly integrated semiconductor integrated circuit having excellent performance.

As a result of these efforts, the manufacturing technology of semiconductor integrated circuits has been scaled down to sub-micron level.

The reduction size of the semiconductor device must be balanced with the characteristics of the various devices only when the horizontal dimension is reduced and the vertical dimension is proportionally reduced.

In other words, when the size of the device is reduced, for example, when the gap between the source and the drain in the transistor is close, unwanted characteristics change of the device may occur. The representative example is the short channel effect.

In order to solve the short channel effect, it is necessary to reduce the horizontal dimension (gate length) and to reduce the vertical dimension (thickness of the gate insulating film, the junction depth, etc.). The profile should be adjusted.

However, since the operating power of the device must satisfy the value required by the electronic product using the device, the dimensions of the semiconductor device are being reduced, but the operating power required by the electronic product using the semiconductor has not been reduced yet. In the case of NMOS transistors, due to the short channel effect that occurs as the gap between the source and the drain decreases, the structure of the NMOS transistor is susceptible to hot carriers, which are accelerated by the high electric field near the drain. Have.

This hot carrier is caused by a very high electric field near the drain junction due to the short channel effect and high applied voltage.

Hereinafter, a semiconductor device manufacturing method according to the prior art will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.

First, a process cross-sectional view shown in FIGS. 1A to 1E is a process cross-sectional view for explaining a process of forming a PMOS device among CMOS devices including NMOS and PMOS devices.

As shown in FIG. 1A, the gate insulating film 2 is formed on the semiconductor substrate 1, and the polysilicon layer 3 is formed on the gate insulating film 2.

A tungsten silicide layer 4 is formed on the polysilicon layer 3 and a silicon nitride film 5 is formed on the tungsten silicide layer 4.

The silicon nitride film 5 is used as a gate cap insulating film.

As shown in FIG. 1B, a photoresist (not shown) is applied onto the silicon nitride film 5, and then patterned by exposure and development processes.

A gate electrode 3a is formed by selectively removing the silicon nitride film 5, the tungsten silicide layer 4, the polysilicon layer 3, and the gate insulating film 2 by an etching process using a patterned photoresist as a mask. do.

Here, the gate electrode 3a is composed of the polysilicon layer 3 and the tungsten silicide layer 4 for minimizing the resistance of the gate electrode 3a.

Subsequently, as shown in FIG. 1C, although not shown in the drawing, a mask is formed so as not to inject P-type ions (BF ₂ ) into the NMOS region to expose only the PMOS region, and then P-type implantation is performed to perform LDD region. (6) is formed.

Here, tilt ion implantation is also possible for the halo structure, but the tilt angle is maintained at 30 °, and As (acenic) or P (phosphorus) is implanted as an impurity.

Thereafter, as shown in FIG. 1D, after removing a mask (not shown) for masking the NMOS region, a silicon nitride film is formed on the substrate 1 including the gate electrode 3a.

The silicon nitride film is etched back to form sidewall spacers 7 on both sides of the gate electrode 3a.

Subsequently, a mask (not shown) for masking the NMOS region is formed so as not to inject P-type ions into the NMOS region to expose only the PMOS region.

The source / drain impurity regions 8 / 8a are formed in the substrate 1 on both sides of the gate electrode 3a through high concentration impurity ion implantation and heat treatment using the gate electrode 3a and the sidewall spacers 7 as masks. Form.

In this PMOS device, as the gate voltage increases and a negative voltage is applied to the drain, a buried channel is formed by holes below the surface, so that holes on the source side are directed toward the drain. PMOS has a smaller driving current than NMOS because it is swept to cause transistor operation, and holes generally have less mobility than electrons.

The conventional semiconductor device manufacturing method as described above has the following problems.

As devices shrink to less than 0.5 [mu] m, there are many limitations in products requiring high integration due to the shortage of PMOS transistors on the short channel side.

In addition, in the fabrication of devices, the concept of halo ion implantation was introduced in order to secure short channel characteristics, but there was also a problem in that a mask should be additionally formed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the semiconductor device can further simplify the process by securing a short channel characteristic margin on the PMOS side and using a separate mask for improving the short channel characteristic. The purpose is to provide a manufacturing method.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

3A to 3D are cross-sectional views illustrating another embodiment of a method of fabricating a semiconductor device in accordance with the present invention.

Explanation of symbols for main parts of the drawings

21 semiconductor substrate 22 gate insulating film

23 polysilicon layer 24 metal silicide layer

25 gate cap insulating film 26 LDD region

27: side wall spacer 28: thermal oxide film

29, 29a: source / drain impurity region 39: halo impurity region

A semiconductor device fabrication method of the present invention for achieving the above object comprises the steps of forming a gate electrode in a predetermined region on a semiconductor substrate in the manufacture of a PMOS transistor of a CMOS device having an NMOS and a PMOS transistor, and on both sides of the gate electrode Forming a low-concentration impurity region in the substrate, forming sidewall spacers on both sides of the gate electrode, and thermal oxidation to form an insulating film on the gate electrode and the sidewall spacer and on the substrate. And promoting the diffusion of the low concentration impurity region into the channel and forming the source and drain impurity regions in the substrate on both sides of the gate electrode through the implantation of the high concentration impurity ions.

Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.

First, the process cross-sectional view shown in Figs. 2A to 2D shows only the PMOS device side in the CMOS device composed of the NMOS and PMOS devices as in the prior art.

Thus, as shown in FIG. 2A, a gate insulating film 22 is formed on the semiconductor substrate 21.

The polysilicon layer 23 is formed on the gate insulating layer 22, and the metal silicide layer 24 is formed on the polysilicon layer 23.

The gate cap insulating layer 25 is formed on the metal silicide layer 24.

In this case, the metal silicide layer 24 is either tungsten silicide (WSi _X ), titanium silicide (TiSi _X ), or cobalt silicide (CoSi _X ).

The gate cap insulating film 25 uses a silicon nitride film (Si ₃ N ₄ ).

Thereafter, as shown in FIG. 2B, a photoresist (not shown) is applied on the gate cap insulating film 25, and then patterned by exposure and development processes.

The gate cap insulating layer 25, the metal silicide layer 24, the polysilicon layer 23, and the gate insulating layer 22 are removed by an etching process using a patterned photoresist as a mask to form a gate electrode 23a.

In this case, the gate electrode 23a includes the polysilicon layer 23 and the metal silicide layer 24.

Thereafter, a mask is formed so as not to inject P-type impurities into the NMOS region, and only the PMOS region is exposed, and then, the LDD region 26 is formed by performing a low concentration of impurity ion implantation using the gate electrode 23a as a mask.

Next, as shown in FIG. 2C, an insulating layer is formed on the entire surface of the substrate 21 including the gate electrode 23a.

The insulating layer is etched back to form sidewall spacers 27 on both sides of the gate electrode 23a.

In this case, the material of the insulating layer is a silicon nitride film.

Thereafter, when the thermal oxidation process is performed, the thermal oxide layer 28 is grown on the entire surface of the substrate 21 including the sidewall spacers 27.

The LDD ions are later diffused toward the channel, and the short channel margin is increased by the same effect as the halo ions are implanted.

After that, as shown in FIG. 2D, a photomask (not shown) is formed to prevent P ⁺ ions from being implanted into the NMOS region and only the PMOS region is exposed, and then the gate electrode 23a is formed through high concentration of P ⁺ ion implantation. Source and drain impurity regions 29 and 29a are formed in the substrate 21 on both sides.

At this time, the heat treatment step is not performed.

3A through 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

As shown in FIG. 3A, a gate insulating film 32 is formed on the semiconductor substrate 31.

A polysilicon layer 33 is formed on the gate insulating layer 32, and a metal silicide layer 34 is formed on the polysilicon layer 33.

The gate cap insulating layer 35 is sequentially formed on the metal silicide layer 34.

Thereafter, a photoresist (not shown) is applied on the gate cap insulating layer 35, and then patterned by exposure and development processes.

The gate cap insulating layer 35, the metal silicide layer 34, the polysilicon layer 33, and the gate insulating layer 32 are sequentially removed by an etching process using the patterned photoresist as a mask, as shown in FIG. 3B. The gate electrode 33a is formed.

Subsequently, the LDD region 36 is formed in the substrate 31 of the gate electrode 33a through impurity ion implantation using the gate electrode 33a as a mask.

As shown in FIG. 3C, an insulating layer is formed on the entire surface of the substrate 31 including the gate electrode 33a.

The insulating layer is etched back to form sidewall spacers 37 on both sides of the gate electrode 33a.

In this case, the material of the insulating layer is a silicon nitride film.

Thereafter, when the thermal oxidation process is performed, a thermal oxide film 38 is grown on the entire surface of the substrate 31 including the sidewall spacers 37.

The LDD ions are later diffused toward the channel to increase the short channel margin.

Subsequently, a halo impurity region 39 is formed under the LDD region 36 through gradient ion implantation.

Thereafter, as shown in FIG. 3D, a photomask (not shown) is formed to prevent P ⁺ ions from being implanted into the NMOS region, and only the PMOS region is exposed, and then the gate electrode 33a is formed through a high concentration of P ⁺ ion implantation. Source and drain impurity regions 40 and 40a are formed in the substrate 31 on both sides.

As described above, according to another embodiment of the present invention, after the thermal oxide film 38 is grown, the halo impurity region 39 is formed to further improve the current driving capability.

As described above, in the method of manufacturing a semiconductor device of the present invention, in order to improve the short channel characteristic generated as the size of the device is reduced, in particular, to improve the short channel effect of the PMOS device, It does not perform a separate process such as halo ion implantation to improve, it is possible to improve the short channel effect without using a separate mask.

In addition, after the source and drain P ⁺ ions are implanted, the heat treatment step is omitted, thereby improving the characteristics of the PMOS transistor and increasing the driving current.

Claims (6)

In manufacturing a PMOS transistor of a CMOS device having an NMOS and a PMOS transistor, Forming a gate electrode in a predetermined region on the semiconductor substrate, Forming a low concentration impurity region in the substrate on both sides of the gate electrode; Forming sidewall spacers on both sides of the gate electrode; Forming an insulating film on the gate electrode and the sidewall spacer and on the substrate by a thermal oxidation process, and simultaneously promoting diffusion of the low concentration impurity region into the channel; And forming a source and a drain impurity region in the substrate on both sides of the gate electrode through the implantation of high concentration of impurity ions. The method of claim 1, wherein heat treatment is not performed after the implantation of the high concentration impurity ions. The method of claim 1, wherein the gate electrode is insulated from the substrate by a gate insulating film. The method of claim 1, wherein the gate electrode comprises a polysilicon layer and a metal silicide layer, and includes a gate cap insulating film. The semiconductor device manufacturing method of claim 1, further comprising forming a halo impurity region under the low concentration impurity region after forming the insulating film by the thermal oxidation process. The method of claim 4, wherein the metal silicide layer comprises tungsten silicide, cobalt silicide, or titanium silicide.