KR20000027911A - Method of forming contact of semiconductor device - Google Patents
Method of forming contact of semiconductor device Download PDFInfo
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- KR20000027911A KR20000027911A KR1019980045956A KR19980045956A KR20000027911A KR 20000027911 A KR20000027911 A KR 20000027911A KR 1019980045956 A KR1019980045956 A KR 1019980045956A KR 19980045956 A KR19980045956 A KR 19980045956A KR 20000027911 A KR20000027911 A KR 20000027911A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
본 발명은 콘택 저항의 증가를 방지할 수 있고, 도전막간의 오버랩 마진을 향상시킬 수 있는 반도체 장치의 콘택 형성 방법에 관한 것으로, 활성 영역과 비활성 영역이 정의된 반도체 기판에 게이트 전극과 소스/드레인 영역이 형성된다. 상기 반도체 기판의 전면에 형성된 층간 절연막을 콘택홀 형성용 마스크를 사용하여 상기 층간 절연막의 일부 두께를 등방성 식각하고, 나머지 두께를 이방성 식각함으로써 콘택홀이 형성된다. 이어, 상기 콘택홀을 채우도록 반도체 기판의 전면에 제 1 도전막이 형성된다. 상기 제 1 도전막을 평탄하게 식각하여 상기 반도체 기판과 전기적으로 연결되는 콘택 플러그가 형성된다. 상기 반도체 기판의 전면에 형성된 상기 제 1 도전막과 선택비를 갖는 제 2 도전막을 패터닝함으로써 상기 반도체 기판과 전기적으로 연결되는 콘택이 형성된다. 이와 같은 반도체 장치의 콘택 형성 방법에 의해서, 콘택홀 형성을 위한 층간 절연막의 식각시 일부 두께를 등방성 식각한 후, 나머지 두께를 이방성 식각하여 콘택홀의 개구부를 넓혀줌으로써 도전막의 증착시 보이드의 노출을 방지하여 콘택 저항이 증가되는 것을 방지할 수 있다. 그리고, 콘택 플러그용 도전막을 배선용 도전막과 선택비를 갖는 막질을 사용함으로써 배선용 도전막의 패터닝시 오버랩 마진을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device which can prevent an increase in contact resistance and improve an overlap margin between conductive films. An area is formed. A contact hole is formed by isotropically etching a part of the thickness of the interlayer insulating film using the contact hole forming mask and anisotropically etching the remaining thickness of the interlayer insulating film formed on the entire surface of the semiconductor substrate. Subsequently, a first conductive layer is formed on the entire surface of the semiconductor substrate to fill the contact hole. The first plug is etched flat to form a contact plug electrically connected to the semiconductor substrate. A contact electrically connected to the semiconductor substrate is formed by patterning a second conductive film having a selectivity with the first conductive film formed on the front surface of the semiconductor substrate. By the method of forming a contact of the semiconductor device, after the isotropic etching of a part of the thickness during the etching of the interlayer insulating film for forming the contact hole, the anisotropic etching of the remaining thickness is performed to widen the opening of the contact hole, thereby preventing the exposure of the void during the deposition of the conductive film. This can prevent the contact resistance from increasing. And the overlap margin at the time of patterning of the wiring conductive film can be improved by using the film quality which has a selectivity with the wiring conductive film for the contact plug conductive film.
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀 더 구체적으로는 반도체 장치의 콘택 플러그 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact plug of a semiconductor device.
DRAM 제조 방법에 있어서, 고집적화와 함께 수반되어지는 디자인 룰(design rule)의 감소는 콘택홀 및 도전층간의 간격이 좁아짐에 따라 그 콘택홀에 대한 도전 물질의 오버랩 마진(overlap margin) 또한 급격이 감소되고 있다. 특히, 콘택홀의 감소는 콘택홀의 크기 대비 높이의 비를 나타내는 종횡비(aspect ratio)의 증가를 초래함으로써 형성된 콘택홀 상부에 증착되는 도전층 예를 들어, 알루미늄과 같은 도전 물질로는 그 콘택홀을 효과적으로 채워주지 못한다. 이러한 문제는 콘택 저항을 증가시키거나 신뢰성 문제 등을 유발시킨다.In the DRAM fabrication method, the reduction of design rules accompanying high integration reduces the overlap margin of the conductive material for the contact hole as the gap between the contact hole and the conductive layer is narrowed. It is becoming. In particular, the reduction of the contact hole effectively results in the contact layer being deposited on top of the contact hole formed by causing an increase in aspect ratio representing the ratio of the height to the size of the contact hole. I can't fill it. These problems increase contact resistance or cause reliability problems.
이를 방지하기 위해 스텝 커버리지(step coverage)가 우수한 도전 물질로 채워 콘택 플러그를 형성한 후, 상기 콘택 플러그에 채워진 도전 물질보다 저항이 더 낮은 다른 도전 물질을 증착하여 패터닝하는 공정이 이루어지고 있다.In order to prevent this, a process of forming a contact plug by filling with a conductive material having excellent step coverage and then depositing and patterning another conductive material having a lower resistance than the conductive material filled in the contact plug is performed.
도 1a 내지 도 1e는 종래의 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.1A through 1E are flowcharts sequentially illustrating processes of a method for forming a contact of a conventional semiconductor device.
도 1a를 참조하면, 종래의 반도체 장치의 콘택 형성 방법은, 먼저 반도체 기판(10)에 활성 영역과 비활성 영역을 정의하기 위한 트렌치 격리(trench isolation)와 같은 소자 격리 영역(12)가 형성된다. 다음에, 상기 반도체 기판(10) 상에 게이트 산화막(도면에 미도시)을 사이에 두고 게이트 전극 형성용 도전막(14)이 형성된다. 상기 도전막(14)은 예를 들어, 폴리실리콘막과 실리사이드막이 적층된 구조를 갖는다. 상기 도전막(14) 상에 게이트 마스크(15)이 형성된다. 이어, 게이트 전극 형성용 마스크를 사용하여 상기 게이트 마스크(15)와 도전막(14)을 차례로 식각함으로써 게이트 전극(16)이 형성된다. 상기 게이트 마스크(15)는 질화막으로 형성된다.Referring to FIG. 1A, in the conventional method for forming a contact of a semiconductor device, a device isolation region 12 such as trench isolation for defining active and inactive regions is first formed in a semiconductor substrate 10. Next, a gate electrode forming conductive film 14 is formed on the semiconductor substrate 10 with a gate oxide film (not shown) interposed therebetween. The conductive film 14 has, for example, a structure in which a polysilicon film and a silicide film are laminated. The gate mask 15 is formed on the conductive layer 14. Subsequently, the gate mask 15 and the conductive film 14 are sequentially etched using the gate electrode forming mask to form the gate electrode 16. The gate mask 15 is formed of a nitride film.
그런 후, 상기 게이트 전극(16)을 포함하여 상기 반도체 기판(10) 상에 질화막이 형성된다. 상기 질화막을 에치 백(etch back) 공정으로 전면 식각함으로써 상기 게이트 전극(16)의 양측벽에 절연막 스페이서(17)가 형성된다. 상기 절연막 스페이서(17)는 후속 공정에서 형성되는 콘택 플러그와 상기 도전막(14)의 절연을 위한 막이다. 다음에, 상기 절연막 스페이서(17) 양측의 상기 반도체 기판(10)에 불순물 이온을 주입함으로써 소스/드레인 영역(18)이 형성된다. 따라서, 소스/드레인(18) 및 게이트 전극(16)을 갖는 트랜지스터가 형성된다. 이어, 상기 반도체 기판(10)의 전면에 층간 절연막(20)이 형성된다.Then, a nitride film is formed on the semiconductor substrate 10 including the gate electrode 16. The insulating layer spacers 17 are formed on both sidewalls of the gate electrode 16 by etching the entire surface of the nitride layer by an etch back process. The insulating film spacer 17 is a film for insulating the contact plug and the conductive film 14 formed in a subsequent process. Next, source / drain regions 18 are formed by implanting impurity ions into the semiconductor substrate 10 on both sides of the insulating film spacer 17. Thus, a transistor having a source / drain 18 and a gate electrode 16 is formed. Subsequently, an interlayer insulating film 20 is formed on the entire surface of the semiconductor substrate 10.
도 1b에 있어서, 상기 층간 절연막(20) 상에 콘택 플러그용 콘택홀 형성 영역을 정의하는 포토레지스트막 패턴(22)이 형성된다. 상기 포토레지스트막 패턴(22)을 마스크로 사용하여 상기 반도체 기판(10)의 소스/드레인 영역(18) 및 게이트 전극(16)의 도전막(14)이 노출될 때까지 상기 층간 절연막(20)을 식각함으로써 콘택 플러그 형성용 콘택홀(24)이 형성된다.In FIG. 1B, a photoresist film pattern 22 defining a contact hole forming region for a contact plug is formed on the interlayer insulating film 20. Using the photoresist layer pattern 22 as a mask, the interlayer insulating layer 20 until the source / drain region 18 of the semiconductor substrate 10 and the conductive layer 14 of the gate electrode 16 are exposed. By etching the contact plug forming contact hole 24 is formed.
도 1c를 참조하면, 상기 포토레지스트막 패턴(22)이 애싱 공정으로 제거된 후, 상기 반도체 기판(10) 상에 형성된 구조물들의 표면을 따라 배리어막(26)이 형성된다. 상기 배리어막(26)은 후속 상기 콘택홀(24)을 채우는 텅스텐막이 반도체 기판(10)의 실리콘(Si)과 반응하는 것을 방지하기 위한 막이다. 그리고, 상기 배리어막(26)은 Ti/TiN막이고, 약 100Å 내지 1000Å의 두께 범위 내로 형성된다.Referring to FIG. 1C, after the photoresist layer pattern 22 is removed through an ashing process, a barrier layer 26 is formed along surfaces of structures formed on the semiconductor substrate 10. The barrier film 26 is a film for preventing the tungsten film filling the contact hole 24 from reacting with silicon (Si) of the semiconductor substrate 10. The barrier film 26 is a Ti / TiN film and is formed in a thickness range of about 100 kPa to 1000 kPa.
이어, 상기 반도체 기판(10)의 전면에 제 1 도전막(28)이 증착되어 상기 콘택홀(24)이 채워진다. 상기 제 1 도전막(28)은 텅스텐(tungsten)막이고 약 2000Å 내지 6000Å의 두께 범위 내로 증착된다. 그러나, 소자가 고집적화되어 감에 따른 콘택홀 크기의 감소로 인해 상기 제 1 도전막(28)의 증착시 상기 콘택홀(24)이 잘 채워지지 않아 보이드(30)가 발생될 수 있다. 다음에, 상기 제 1 도전막(28)을 전면 에치 백 공정으로 식각함으로써 도 1d에 도시되어 있는 바와 같이, 상기 콘택홀(24) 내에만 제 1 도전막(28)이 플러그 형태(28a)로 남게되고 다른 부분은 모두 제거된다.Subsequently, a first conductive layer 28 is deposited on the entire surface of the semiconductor substrate 10 to fill the contact hole 24. The first conductive film 28 is a tungsten film and is deposited in a thickness range of about 2000 kPa to 6000 kPa. However, due to the decrease in the size of the contact hole due to the high integration of the device, the contact hole 24 may not be filled well when the first conductive layer 28 is deposited, so that the voids 30 may be generated. Next, the first conductive film 28 is etched by a front etch back process so that the first conductive film 28 is in the form of a plug 28a only in the contact hole 24, as shown in FIG. 1D. All other parts are removed.
도 1e에 있어서, 상기 반도체 기판(10)의 전면에 제 2 도전막(32)을 증착한 후, 포토레지스트막 패턴을 마스크로 사용하여 패터닝함으로써 반도체 기판(10)과 전기적으로 연결되는 배선이 형성된다.In FIG. 1E, the second conductive film 32 is deposited on the entire surface of the semiconductor substrate 10 and then patterned using a photoresist film pattern as a mask to form a wire electrically connected to the semiconductor substrate 10. do.
상술한 방법으로 콘택 플러그를 형성한 경우, 상기 제 1 도전막(28)의 에치 백 공정시 상기 보이드(30)가 노출된 경우 상기 보이드(30)에 의해 콘택홀(24) 바닥 부분에 있는 제 1 도전막(28)까지 식각되어 저항이 증가되는 콘택 불량이 발생될 수 있다. 또한, 배선 형성을 위한 상기 제 2 도전막(32)의 증착 후 패터닝시 좁게 형성된 콘택 플러그(28a)에 의해 상기 콘택 플러그(28a)에 대한 제 2 도전막(32)의 오버랩 마진(overlap margin)이 저하되는 문제가 생길 수 있다.In the case where the contact plug is formed by the above-described method, when the void 30 is exposed during the etch back process of the first conductive layer 28, the first and second contact plugs are formed on the bottom portion of the contact hole 24 by the voids 30. The contact failure may be caused by etching up to one conductive layer 28 to increase resistance. In addition, an overlap margin of the second conductive layer 32 with respect to the contact plug 28a is formed by a narrowly formed contact plug 28a during patterning after deposition of the second conductive layer 32 for wiring formation. This deterioration problem may occur.
본 발명은 상술한 제반 문제점을 해결하기 위해 제안된 것으로서, 콘택홀에 도전막의 증착시 및 에치 백 공정시 보이드의 노출을 방지할 수 있고, 콘택 플러그에 대한 도전막의 오버랩 마진을 향상시킬 수 있는 반도체 장치의 콘택 형성 방법을 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and is capable of preventing the exposure of voids during the deposition of a conductive film in a contact hole and during an etch back process, and can improve the overlap margin of the conductive film on a contact plug. It is an object to provide a method for forming a contact of a device.
도 1a 내지 도 1e는 종래의 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도; 그리고1A to 1E are flowcharts sequentially showing processes of a method for forming a contact of a conventional semiconductor device; And
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.2A through 2E are flowcharts sequentially illustrating processes of a method for forming a contact of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10, 100 : 반도체 기판 12, 102 ; 소자 격리 영역10, 100: semiconductor substrate 12, 102; Device isolation
16, 106 : 게이트 전극 20, 110 : 층간 절연막16, 106: gate electrode 20, 110: interlayer insulating film
24, 114 : 콘택홀24, 114: contact hole
(구성)(Configuration)
상술한 목적을 달성하기 위한 본 발명에 의하면, 반도체 장치의 콘택 형성 방법은, 활성 영역과 비활성 영역이 정의된 반도체 기판에 게이트 전극과 소스/드레인 영역을 형성하는 단계와; 상기 반도체 기판의 전면에 층간 절연막을 형성하는 단계와; 콘택홀 형성용 마스크를 사용하여 상기 층간 절연막의 일부 두께를 등방성 식각하고, 나머지 두께를 이방성 식각하여 콘택홀을 형성하는 단계와; 상기 콘택홀을 채우도록 반도체 기판의 전면에 제 1 도전막을 형성하는 단계와; 상기 제 1 도전막을 평탄하게 식각하여 상기 반도체 기판과 전기적으로 연결되는 콘택 플러그를 형성하는 단계와; 상기 반도체 기판의 전면에 상기 제 1 도전막과 선택비를 갖는 제 2 도전막을 형성하는 단계 및; 상기 제 2 도전막을 패터닝하여 상기 반도체 기판과 전기적으로 연결되는 콘택을 형성하는 단계를 포함한다.According to the present invention for achieving the above object, a contact forming method of a semiconductor device comprises the steps of: forming a gate electrode and a source / drain region on a semiconductor substrate in which an active region and an inactive region are defined; Forming an interlayer insulating film on the entire surface of the semiconductor substrate; Isotropically etching a part of the thickness of the interlayer insulating layer using a contact hole forming mask and anisotropically etching the remaining thickness to form a contact hole; Forming a first conductive film on an entire surface of the semiconductor substrate to fill the contact hole; Etching the first conductive layer evenly to form a contact plug electrically connected to the semiconductor substrate; Forming a second conductive film having a selectivity with respect to the first conductive film on an entire surface of the semiconductor substrate; Patterning the second conductive layer to form a contact electrically connected to the semiconductor substrate.
이 방법의 바람직한 실시예에 있어서, 상기 콘택홀 형성 후, 반도체 기판 상에 형성된 구조물을 따라 배리어막을 형성하는 단계를 더 포함한다.In a preferred embodiment of the method, after forming the contact hole, further comprising forming a barrier film along the structure formed on the semiconductor substrate.
(작용)(Action)
도 2d를 참조하면, 본 발명의 실시예에 따른 신규한 반도체 장치의 콘택 형성 방법은, 활성 영역과 비활성 영역이 정의된 반도체 기판에 게이트 전극과 소스/드레인 영역이 형성된다. 상기 반도체 기판의 전면에 형성된 층간 절연막을 콘택홀 형성용 마스크를 사용하여 상기 층간 절연막의 일부 두께를 등방성 식각하고, 나머지 두께를 이방성 식각함으로써 콘택홀이 형성된다. 이어, 상기 콘택홀을 채우도록 반도체 기판의 전면에 제 1 도전막이 형성된다. 상기 제 1 도전막을 평탄하게 식각하여 상기 반도체 기판과 전기적으로 연결되는 콘택 플러그가 형성된다. 상기 반도체 기판의 전면에 형성된 상기 제 1 도전막과 선택비를 갖는 제 2 도전막을 패터닝함으로써 상기 반도체 기판과 전기적으로 연결되는 콘택이 형성된다. 이와 같은 반도체 장치의 콘택 형성 방법에 의해서, 콘택홀 형성을 위한 층간 절연막의 식각시 일부 두께를 등방성 식각한 후, 나머지 두께를 이방성 식각하여 콘택홀의 개구부를 넓혀줌으로써 도전막의 증착시 보이드의 노출을 억제하여 콘택 저항이 증가되는 것을 방지할 수 있다. 그리고, 콘택 플러그용 도전막을 배선용 도전막과 선택비를 갖는 막질을 사용함으로써 배선용 도전막의 패터닝시 오버랩 마진을 향상시킬 수 있다.Referring to FIG. 2D, in the method of forming a contact of a novel semiconductor device according to an embodiment of the present invention, a gate electrode and a source / drain region are formed in a semiconductor substrate in which active and inactive regions are defined. A contact hole is formed by isotropically etching a part of the thickness of the interlayer insulating film using the contact hole forming mask and anisotropically etching the remaining thickness of the interlayer insulating film formed on the entire surface of the semiconductor substrate. Subsequently, a first conductive layer is formed on the entire surface of the semiconductor substrate to fill the contact hole. The first plug is etched flat to form a contact plug electrically connected to the semiconductor substrate. A contact electrically connected to the semiconductor substrate is formed by patterning a second conductive film having a selectivity with the first conductive film formed on the front surface of the semiconductor substrate. According to the method of forming a contact of a semiconductor device, after the isotropic etching of a part of the thickness during the etching of the interlayer insulating film for forming the contact hole, the anisotropic etching of the remaining thickness is made to widen the opening of the contact hole, thereby suppressing the exposure of the void during the deposition of the conductive film. This can prevent the contact resistance from increasing. And the overlap margin at the time of patterning of the wiring conductive film can be improved by using the film quality which has a selectivity with the wiring conductive film for the contact plug conductive film.
(실시예)(Example)
이하, 도 2a 내지 도 2e를 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2E.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.2A through 2E are flowcharts sequentially illustrating processes of a method for forming a contact of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 본 발명에 따른 반도체 장치의 콘택 형성 방법은, 먼저 반도체 기판(100)에 활성 영역과 비활성 영역을 정의하기 위한 트렌치 격리(trench isolation)와 같은 소자 격리 영역(102)이 형성된다. 다음에, 상기 반도체 기판(100) 상에 게이트 산화막(도면에 미도시)을 사이에 두고 게이트 전극 형성용 도전막(104)이 형성된다. 상기 도전막(104)은 예를 들어, 폴리실리콘막과 실리사이드막이 적층된 구조를 갖는다. 상기 도전막(104) 상에 게이트 마스크(105)가 형성된다. 이어, 게이트 전극 형성용 마스크를 사용하여 반도체 기판(100)의 표면이 노출될 때까지 상기 게이트 마스크(105)와 도전막(104)을 차례로 식각함으로써 게이트 전극(106)이 형성된다. 상기 게이트 마스크(105)는 질화막으로 형성된다.Referring to FIG. 2A, in the method of forming a contact of a semiconductor device according to the present invention, a device isolation region 102 such as trench isolation for defining an active region and an inactive region is first formed in a semiconductor substrate 100. do. Next, a gate electrode conductive film 104 is formed on the semiconductor substrate 100 with a gate oxide film (not shown) interposed therebetween. The conductive film 104 has a structure in which a polysilicon film and a silicide film are stacked, for example. A gate mask 105 is formed on the conductive film 104. Subsequently, the gate mask 106 is formed by sequentially etching the gate mask 105 and the conductive film 104 until the surface of the semiconductor substrate 100 is exposed using the mask for forming a gate electrode. The gate mask 105 is formed of a nitride film.
그런 후, 상기 게이트 전극(106)을 포함하여 상기 반도체 기판(100) 상에 질화막이 형성된다. 상기 질화막을 에치 백(etch back) 공정으로 전면 식각함으로써 상기 게이트 전극(106)의 양측벽에 절연막 스페이서(107)가 형성된다. 상기 절연막 스페이서(107)는 후속 공정에서 형성되는 콘택 플러그와 상기 도전막(104)의 절연을 위한 막이다.Thereafter, a nitride film is formed on the semiconductor substrate 100 including the gate electrode 106. An insulating layer spacer 107 is formed on both sidewalls of the gate electrode 106 by etching the entire surface of the nitride layer by an etch back process. The insulating film spacer 107 is a film for insulating the contact plug and the conductive film 104 formed in a subsequent process.
다음에, 상기 절연막 스페이서(107) 양측의 상기 반도체 기판(100)에 불순물 이온을 주입함으로써 소스/드레인 영역(108)이 형성된다. 따라서, 소스/드레인(108) 및 게이트 전극(106)을 갖는 트랜지스터가 형성된다. 이어, 상기 반도체 기판(100)의 전면에 절연막(110)이 형성된다. 상기 절연막(110)은 O3-TEOS(ozon-tetraethylorthosilicate)막이고, 약 5000Å 내지 10000Å의 두께 범위 내로 형성된다.Next, a source / drain region 108 is formed by implanting impurity ions into the semiconductor substrate 100 on both sides of the insulating film spacer 107. Thus, a transistor having a source / drain 108 and a gate electrode 106 is formed. Subsequently, an insulating film 110 is formed on the entire surface of the semiconductor substrate 100. The insulating film 110 is an O 3 -TEOS (ozon-tetraethylorthosilicate) film and is formed within a thickness range of about 5000 kPa to 10000 kPa.
도 2b에 있어서, 상기 절연막(110) 상에 콘택 플러그 형성용 콘택홀 형성 영역을 정의하는 포토레지스트막 패턴(112)이 형성된다. 상기 포토레지스트막 패턴(112)을 마스크로 사용하여 상기 절연막(110)의 일부 두께를 등방성 식각한 후, 상기 반도체 기판(10)의 소스/드레인 영역(108) 및 게이트 전극(106)의 도전막(104)이 노출될 때까지 상기 절연막(110)을 식각함으로써 콘택 플러그 형성용 콘택홀(114)이 형성된다.In FIG. 2B, a photoresist layer pattern 112 defining a contact hole forming region for forming a contact plug is formed on the insulating layer 110. After the isotropic etching of the thickness of the insulating layer 110 using the photoresist layer pattern 112 as a mask, the conductive layer of the source / drain region 108 and the gate electrode 106 of the semiconductor substrate 10 is formed. The contact plug forming contact hole 114 is formed by etching the insulating layer 110 until the 104 is exposed.
도 2c를 참조하면, 상기 포토레지스트막 패턴(112)을 애싱 공정으로 제거한 후, 상기 반도체 기판(100) 상에 형성된 구조물의 표면을 따라 배리어막(116)이 형성된다. 상기 배리어막(116)은 Ti/TiN막이고, 약 100Å 내지 1000Å의 두께 범위 내로 형성된다. 이어, 상기 반도체 기판(100)의 전면에 제 1 도전막(118)이 증착되어 상기 콘택홀(114)이 채워진다. 상기 제 1 도전막(118)은 텅스텐(tungsten)막이고 약 2000Å 내지 6000Å의 두께 범위 내로 증착된다. 그리고, 상기 텅스텐막은 상기 배리어막(116)인 Ti/TiN막에 대해 선택비를 갖는 막이다.Referring to FIG. 2C, after the photoresist layer pattern 112 is removed by an ashing process, a barrier layer 116 is formed along the surface of the structure formed on the semiconductor substrate 100. The barrier film 116 is a Ti / TiN film and is formed in a thickness range of about 100 kPa to 1000 kPa. Subsequently, a first conductive layer 118 is deposited on the entire surface of the semiconductor substrate 100 to fill the contact hole 114. The first conductive film 118 is a tungsten film and is deposited in a thickness range of about 2000 kPa to 6000 kPa. The tungsten film is a film having a selectivity with respect to the Ti / TiN film, which is the barrier film 116.
본 발명에서는, 상기 콘택홀(114) 형성시 일부 두께를 등방성 식각하고, 나머지 두께를 이방성 식각하여 형성하여 콘택홀(114)의 개구부를 넓게 형성함으로써 상기 콘택홀(114)을 제 1 도전막(118)으로 채울 때 등방성 식각한 부분에 발생될 수 있는 보이드(120)의 노출을 방지한다.In the present invention, when the contact hole 114 is formed, a portion of the thickness isotropically etched, and the remaining thickness is formed by anisotropically etching to form the opening of the contact hole 114 wide, thereby forming the contact hole 114 as the first conductive film ( 118 to prevent exposure of voids 120 that may occur in isotropic etched portions.
다음에, 상기 배리어막(116)의 표면이 노출될 때까지 상기 제 1 도전막(118)을 전면 에치 백 공정으로 식각함으로써 도 2d에 도시되어 있는 바와 같이, 상기 콘택홀(114) 내에만 상기 제 1 도전막(118)이 플러그 형태(118a)로 남고 나머지 부분은 모두 제거된다. 또한, 상기 에치 백 공정시에도 상기 보이드(120)의 노출은 방지된다.Next, the first conductive layer 118 is etched by a front etch back process until the surface of the barrier layer 116 is exposed, and as shown in FIG. The first conductive film 118 remains in the plug form 118a and all remaining portions are removed. In addition, exposure of the voids 120 is prevented even during the etch back process.
도 2e에 있어서, 상기 반도체 기판(100)의 전면에 제 2 도전막(122)을 형성한 후, 포토레지스트막 패턴(도면에 미도시)을 마스크로 사용하여 상기 제 2 도전막(122) 및 배리어막(116)을 차례로 식각하여 패터닝함으로써 상기 콘택 플러그(118a)와 전기적으로 연결되는 금속 배선이 형성된다. 상기 제 2 도전막(122)은 알루미늄막으로서 상기 텅스텐막과 선택비를 갖는 막이며, 약 2000Å 내지 6000Å의 두께 범위 내로 형성된다.In FIG. 2E, after the second conductive film 122 is formed on the entire surface of the semiconductor substrate 100, the second conductive film 122 and the photoresist film pattern (not shown) are used as a mask. The barrier layer 116 is sequentially etched and patterned to form metal wires electrically connected to the contact plugs 118a. The second conductive film 122 is an aluminum film having a selectivity with respect to the tungsten film, and is formed in a thickness range of about 2000 kPa to 6000 kPa.
따라서, 상기 배선 형성을 위한 제 2 도전막을 상기 콘택 플러그(118a)용 제 1 도전막과 선택비를 갖는 막을 사용함으로써 상기 콘택 플러그(118a)에 대한 배선용 도전막의 오버랩을 향상시킬 수 있다.Therefore, the overlap of the wiring conductive film with respect to the contact plug 118a can be improved by using a film having a selectivity with respect to the first conductive film for the contact plug 118a as the second conductive film for forming the wiring.
본 발명은 콘택홀 형성을 위한 층간 절연막의 식각시 일부 두께를 등방성 식각한 후, 나머지 두께를 이방성 식각하여 콘택홀의 개구부를 넓혀줌으로써 도전막의 증착시 보이드의 노출을 방지하여 콘택 저항이 증가되는 것을 방지할 수 있다. 그리고, 콘택 플러그용 도전막을 배선용 도전막과 선택비를 갖는 막질을 사용함으로써 배선용 도전막의 패터닝시 오버랩 마진을 향상시킬 수 있는 효과가 있다.According to the present invention, after the isotropic etching of the thickness of the interlayer insulating layer for forming the contact hole, the anisotropic etching of the remaining thickness is performed to widen the opening of the contact hole, thereby preventing the exposure of voids during the deposition of the conductive film, thereby preventing the contact resistance from increasing. can do. The use of the contact plug conductive film and a film quality having a selectivity with respect to the wiring conductive film has the effect of improving the overlap margin during the patterning of the wiring conductive film.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045956A KR20000027911A (en) | 1998-10-29 | 1998-10-29 | Method of forming contact of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045956A KR20000027911A (en) | 1998-10-29 | 1998-10-29 | Method of forming contact of semiconductor device |
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| KR20000027911A true KR20000027911A (en) | 2000-05-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019980045956A Withdrawn KR20000027911A (en) | 1998-10-29 | 1998-10-29 | Method of forming contact of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400071B1 (en) * | 2000-08-28 | 2003-09-29 | 인피니언 테크놀로지스 아게 | Method for manufacturing an electrically conductive connection |
| KR100652369B1 (en) * | 2001-02-19 | 2006-11-30 | 삼성전자주식회사 | Method of manufacturing a semiconductor device having a self-aligned contact pad |
| KR101149053B1 (en) * | 2006-02-23 | 2012-05-25 | 에스케이하이닉스 주식회사 | Method of forming a storage node contact of a semiconductor device |
-
1998
- 1998-10-29 KR KR1019980045956A patent/KR20000027911A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400071B1 (en) * | 2000-08-28 | 2003-09-29 | 인피니언 테크놀로지스 아게 | Method for manufacturing an electrically conductive connection |
| KR100652369B1 (en) * | 2001-02-19 | 2006-11-30 | 삼성전자주식회사 | Method of manufacturing a semiconductor device having a self-aligned contact pad |
| KR101149053B1 (en) * | 2006-02-23 | 2012-05-25 | 에스케이하이닉스 주식회사 | Method of forming a storage node contact of a semiconductor device |
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