KR100745058B1 - Self-aligned contact hole formation method of semiconductor device - Google Patents

Abstract

The method of forming a self-aligned contact hole according to the present invention comprises the steps of forming a conductor pattern having a hard mask stacked thereon on a semiconductor substrate, forming an insulating film spacer on the sidewall of the conductor pattern, and Forming an etch barrier film on the semiconductor substrate between the patterns, forming an interlayer insulating film on the entire surface of the structure on which the etch barrier film is formed, and etching the interlayer insulating film until the etch barrier film is exposed to form contact holes between the conductor patterns. And depositing a USG film on the contact hole formed structure, etching the USG film to form an etch preventing spacer on the sidewall of the contact hole, and removing the etch barrier film.

SAC, USG, Spacer, Step Coverage

Description

Method for forming self align contact hole of semiconductor device

1A to 1C are flowcharts illustrating a SAC etching process of a semiconductor device according to the prior art;

2 is a view showing a SAC etching profile according to the prior art;

3A to 3D are flowcharts illustrating a process of forming a self-aligned contact hole in a semiconductor device according to the present invention;

4 is a cross-sectional view showing the step coverage of a general USG film;

5 is a view showing a SAC etching profile according to the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 gate electrode

104: hard mask (nitride film) 106: capping film

108: spacer 109: etching barrier film

110: interlayer insulating film 112: photoresist pattern

114: SAC contact hole 116: USG film

118: etching prevention spacer 120: SAC etching profile according to the present invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method, and more particularly, to self-aligning semiconductor devices to reduce etch damage and attack of lower layers that may occur during etching for self-aligned contacts (hereinafter, referred to as SACs). It relates to a method of forming a contact hole.

As semiconductor devices have been highly integrated, reductions in device size and line width have become inevitable. Accordingly, the technology for implementing fine line widths has become a key technology in the fabrication of semiconductor devices. Contact hole margins, which directly affect the high integration of devices, are also becoming very small.

As a result, the contact hole fabrication process applied in the highly integrated semiconductor device absolutely lacks the space between the wirings (eg, word lines and bit lines) so that the SAC can be used to overcome the mis-alignment caused by the mask process. Use the method.

In the conventional SAC type landing plug contact (hereinafter referred to as LPC), an etching barrier layer (for example, SiN) and an interlayer insulating layer (Inter Poly Oxide) are sequentially formed, and the portion where the LPC is to be formed is formed on the spacer of the line sidewall. It is manufactured by etching a self-aligned form to form a contact hole, gap-filling polysilicon in the contact hole, or growing an epitaxial film by an SEG process.                         

1A to 1C are flowcharts illustrating a SAC etching process of a semiconductor device according to the prior art. Referring to this, the SAC etching method of the prior art is as follows.

As shown in FIG. 1A, a word line (or bit line) 12 is formed on the semiconductor substrate 10 as a conductor pattern. The word line 12 has a structure in which a doped polysilicon layer and a tungsten layer W are stacked. In addition, a hard mask 14 and a capping layer 16 serving as a barrier in a subsequent contact process are formed on the word line 12. The word line 12, the hard mask 14, and the capping layer 16 have a stacked structure. A spacer 18 is formed on the side of the stack structure to form the contact hole in a self-aligned shape while preventing side exposure of the line during etching of the interlayer insulating layer for forming the contact hole. In this case, the hard mask 14, the capping layer 16, and the spacer 18 may all use an insulating material. For example, the capping layer 16 may include TEOS (TetraEtlyOrthoSilicate), the hard mask 14, and the spacer 18. Uses a nitride film as an insulating material having an interlayer insulating film and an etching selectivity.

Subsequently, an etch barrier layer 20 serving as an etch barrier in the contact hole etching process of the SAC structure is formed on the substrate surface between the spacers 18 on which the contact holes are to be formed. Thereafter, after forming the interlayer insulating film 22 on the structure and planarizing the surface by chemical mechanical polishing (hereinafter referred to as CMP), a photoresist pattern using an LPC mask is performed to form a photoresist pattern 24. To form.

Subsequently, as shown in FIG. 1B, an etching process using the photoresist pattern 24 for LPC is performed to etch the interlayer insulating layer 22 to form the contact hole 26 of the SAC structure. As a result, the contact hole 26 formed in the interlayer insulating layer 22 is self-aligned and etched in the spacer 18, thereby ensuring a misalignment margin. At this time, the etching barrier layer 20 remains at the bottom of the contact hole 26.

Then, as shown in FIG. 1C, the SAC etching process according to the prior art is terminated by removing the etch barrier layer 20 remaining in the contact hole 26.

However, in the prior art, during the etching process using the LPC photoresist pattern, the capping layer 16 and the hard mask 14 and the sidewall spacer 18 on the word line 12 are eroded from etching. As the stack height of the word line is increased, an effect such as isotropic etching is generated. In the prior art contact hole etching process, the capping layer 16 is removed according to the SAC etching profile 30 as shown in FIG. ) Is also lost and overetched.

Accordingly, in the conventional SAC etching method, when the capping layer 16 and the hard mask 14 are etched away, the tungsten layer of the word line 12 is exposed, thereby making the SAC etching profile defective. Such a poor etching of the SAC causes a non-growth in the subsequent application of a process such as ESL, causing a decrease in the yield and reliability of the semiconductor device.

An object of the present invention is to provide a method for forming a self-aligned contact hole in a semiconductor device capable of protecting an upper wall structure of a conductor pattern from etching erosion and thus ensuring a good SAC etching profile.

In order to achieve the above technical problem, a method of forming a self-aligned contact hole of a semiconductor device according to the present invention may include forming a conductor pattern on a semiconductor substrate, on which a hard mask is stacked, and a sidewall of the conductor pattern. Forming an insulating film spacer on the semiconductor substrate, forming an etch barrier film on the semiconductor substrate between the conductor patterns, forming an interlayer insulating film on the entire surface of the structure on which the etch barrier film is formed, and then revealing the etch barrier film. Forming a contact hole between the conductor patterns by etching the interlayer insulating layer, depositing a USG film in the structure in which the contact hole is formed, and etching the USG film to form an etch preventing spacer on a sidewall of the contact hole And removing the etch barrier film.
In the present invention, the USG film can be deposited to a thickness of 1200 Å ± 120 Å.
The etch stop spacer may be formed to a thickness of 45 kPa to 55 kPa.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3A to 3D are flowcharts illustrating a process of forming a self-aligned contact hole in a semiconductor device according to the present invention. Referring to these, the self-aligned contact forming method according to the present invention is as follows.

As shown in FIG. 3A, a word line (or bit line) 102 is formed as a conductor pattern on the semiconductor substrate 100. The word line 102 has a structure in which a doped polysilicon layer and a tungsten layer W are stacked. In addition, a capping layer 106 may be formed on the word line 102 to act as a barrier for the hard mask 104 and subsequent contact processes. The word line 102, the hard mask 104, and the capping layer 106 may have a stacked structure. A spacer 108 is formed on the side of the stack structure to form the contact holes in a self-aligned form while preventing side exposure of the line during etching of the interlayer insulating layer for forming the contact holes. At this time, the hard mask 104, the capping film 106 and the spacer 108 are all made of an insulating material, for example, the capping film 106 is TEOS, the hard mask 104 and the spacer 108 is an interlayer insulating film A nitride film is used as an insulating material having an over-etch selectivity.

Thereafter, an etching barrier layer 109 serving as an etching barrier in the contact hole etching process of the SAC structure is formed on the surface of the substrate between the spacers 108 where the contact holes are to be formed. Thereafter, after forming the interlayer insulating film 110 on the structure and planarizing the surface thereof with CMP, the photoresist pattern 112 is formed by performing a photolithography process using an LPC mask.

Subsequently, as shown in FIG. 3B, a contact hole having a SAC structure self-aligned and etched by the spacer 18 by etching the interlayer insulating layer 110 by performing an etching process using the photoresist pattern 112 for LPC. 114). In this case, an etching barrier layer 109 remains at the bottom of the contact hole 114.

Then, as shown in FIG. 3C, the USG film 116 is deposited on the structure in which the contact hole 114 is formed. Since the deposition thickness of the USG film 116 is an appropriate thickness due to the step coverage characteristic, the contact hole region of the SAC structure is narrowed so that voids do not occur between the USG film 116 of the side wall. In the present invention, the deposition thickness of the USG film 116 is in the range of 1200 Å ± 120 Å. As a result, the deposition thickness of the upper side and the side of the word line 102 is changed due to the step coverage characteristics of the USG film 116.

As shown in FIG. 3D, an etch back is performed until the surface of the interlayer insulating layer 110 is exposed to the sidewalls of the stack structure of the word line 12 / hard mask 14 / capping layer 16. An etch stop spacer 118 is further formed. In this embodiment, the thickness of the spacer 118 is set to 45 mm to 55 mm. Then, the etch barrier layer 109 at the bottom of the SAC contact hole 114 formed with the etch stop spacer 118 made of USG is removed. In this case, during the etching process of the etching barrier layer 109, the etching selectivity ratio of the etching barrier layer 109 to the USG layer is good, so that the etching preventing spacer 118 serves as a sufficient barrier.

Therefore, in the SAC fabrication process, the interlayer insulating film 110 is etched to form the contact hole 114 to secure the LPC region during the SAC manufacturing process, and the etching process is performed after the USG film 116 is deposited. The addition of an etching preventing spacer 118 to the side structure may reduce the etching loss of the capping layer 106, the hard mask 104, and the spacer 108, which may occur during the etching process of the subsequent etching barrier layer. To prevent erosion).

The USG film 116 used in the present invention has a step coverage characteristic in which the thickness deposited on the vertical sidewall is relatively thinner than the thickness deposited on the plane, as shown in FIG. In the present embodiment, when the deposition thickness of the USG film is in the range of 1200Å ± 120Å, the thickness deposited on the sidewall becomes 200Å ± 20Å.                     

Accordingly, the present invention proceeds to the etch back process to form the etching prevention spacer 118 made of USG only in the contact hole of the SAC structure and to increase the etching selectivity with respect to the etching prevention spacer 118 to increase the etching barrier film 109. By removing, the word line 12 and its surrounding structure are protected from etching by the etching preventing spacer 118, thereby eliminating the etching loss.

5 is a view showing a SAC etching profile according to the present invention.

Referring to Figure 5, the SAC etching profile 120 of the present invention is good vertically along the dotted line shape. Accordingly, the present invention can reduce the amount of etch loss of the word line and its surrounding structure during SAC etching by improving the SAC etching profile by using the step coverage characteristics of the USG film whose deposition thickness varies depending on the step.

As described above, the present invention proceeds with the SAC etching process, depositing a USG film on the interlayer insulating film, and etching back to form an spacer for preventing etching on the contact hole side, and then proceeds to remove the etching barrier film.

Therefore, the present invention can protect the upper wall structure of the word line (or bit line) from the etching erosion of the good SAC etch profile further formed in the contact hole can secure a good SAC etch profile. In addition, the present invention can prevent abnormal growth and inter-device bridge phenomenon in the subsequent ESL process after the SAC process, thereby improving the yield and reliability of the semiconductor device.
On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

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Claims (4)

delete Forming a conductor pattern having a hard mask stacked thereon on the semiconductor substrate; Forming an insulating film spacer on sidewalls of the conductor pattern; Forming an etch barrier layer on the semiconductor substrate between the conductor patterns; Forming an interlayer insulating film on an entire surface of the structure on which the etch barrier film is formed; Etching the interlayer insulating layer until the etch barrier layer is exposed to form contact holes between the conductor patterns; Depositing a USG film on the structure in which the contact hole is formed; Etching the USG film to form an etch stop spacer on a sidewall of the contact hole; And Removing the etch barrier layer; and forming a self-aligned contact hole in the semiconductor device. The method of claim 2, And depositing the USG film in a thickness of 1200 占 Å 120 占. The method of claim 2, The etching preventing spacer is a self-aligned contact hole forming method of the semiconductor device, characterized in that the thickness of 45 ~ 55Å.

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