KR20000015266U - Pseudo Noise Code Control Circuit of CDM Receiver - Google Patents

Abstract

The present invention relates to a PN code control circuit of a CDMA receiver. In particular, in order to despread the spread spectrum signal from the CDMA receiver back to the original signal, the PN code generation is controlled by adjusting the duty period of the digital device and the clock. By adjusting the phase delay input value, the initial synchronization performance of the CDMA receiver can be flexibly matched, and the hardware configuration can be flexibly adjusted. In order to achieve the above object, in one embodiment of the present invention, the energy is detected by despreading a received signal using the PN code output from the PN code generating means, and comparing the detected energy integral with an arbitrary reference value. A PN code control circuit of a CDMA receiver that searches for the PN code as a comparison result, wherein the PN code control signal is outputted according to the comparison output of the comparison unit by using a plurality of digital elements and an externally controllable clock signal. And a code control logic portion.

Description

Pseudo noise code control circuit of code division multiple access (CDMA) receiver

The present invention relates to a pseudo noise code (PN code) control circuit for synchronous acquisition of a code division multiple access (CDMA) receiver, in particular a CDMA receiver. A control device that matches an initial synchronization using a PN code generator to despread a spread spectrum signal back to an original signal, and relates to a PN code control device for implementing a serial synchronizer.

The initial synchronous search technology of the conventional CDMA receiver can be roughly divided into parallel search, serial search, and continuous search, and the most commonly used method is serial synchronous search technology. There are many ways to implement this.

The circuit diagram for the serial synchronous search is mainly implemented using a voltage control oscillator (VCO), the configuration of which is shown in FIG. As shown in the figure, the PN code generator 11 generates a PN code by using a VCO, and generates the PN code by using a VCO 12a, a switch 12b, and a logic gate (AND) 12c. A PN code generation control unit 12 for controlling the unit, a band pass filter (BPF) 13 for passing only signal components of a required frequency band among the received signals, an envelope detector 14 for detecting the energy, and An integrating unit 15 for integrating the detected energy, and a comparing unit 16 for comparing the energy of the integrated signal with a signal reference value.

Referring to the serial synchronous search operation of the conventional CDMA receiver having such a configuration, the PN code generator 11 generates a PN code (the same as that generated by the transmitter). g (t-iTc) ) And the input signal received through the multiplier 10 ( Multiply by) to remove the PN code. At this time, the switch 12b of the PN code generation controller 12 is initially connected to the first position to enable the logic gate AND 12c. At this time, the PN code generation controller 12 continues to supply the chip frequency to the PN code generator 11.

If there is a mismatch between the received PN code and the PN code produced at the receiver, the signal Vr (t) multiplied by the PN code is also a spread signal, which has a wide spectrum bandwidth. Since the signal is spread with power, the output of the bandpass filter 13 also has a small power distribution.

Therefore, because of this small power, the output of the bandpass filter 13 and the output of the envelope detector 14 are also small, and the integrated value thereof is smaller than the reference signal, so that the switch 12b of the PN code generation controller 12 is It is connected to the second position, thereby disabling the output of the logic gate (AND) 12c to stop the operation of the PN code generator 11, thereby causing a chip delay.

In the delay section, the integrating unit 15 sends the switch 12b of the PN code generation control unit 12 to the first position again, and repeats this process, thereby synchronizing the PN code.

If the PN code is synchronized, the output of the band pass filter 13 produces a desired signal, and the output value of the envelope detector 14 is high so that the integrated value is larger than the reference signal.

Therefore, the synchronization is synchronized, and the synchronized signal is passed to the PN code generation control unit 12.

However, the prior art of such a configuration uses a voltage-controlled oscillator to move the phase of the PN code, and therefore uses a digital device and an analog device, which is inconvenient for ASIC or simulation. In other words, since the delay of the PN code of the receiver is delayed by an integer multiple of the period, there is a problem that the flexibility of the phase delay is low.

Therefore, the present invention was created to solve the above problems, and the present invention controls the generation of the PN code by adjusting the duty period of the digital element and the clock to despread the spread spectrum signal back to the original signal at the CDMA receiver. The purpose of the present invention is to provide a PN code control circuit of a CDMA receiver that synchronizes serial initial synchronization.

In order to achieve the above object, in one embodiment of the present invention, the energy is detected by despreading a received signal using the PN code output from the PN code generating means, and comparing the detected energy integral with an arbitrary reference value. A PN code control circuit of a CDMA receiver that searches for the PN code as a comparison result, wherein the PN code control signal is outputted according to the comparison output of the comparison unit by using a plurality of digital elements and an externally controllable clock signal. It provides a PN code control circuit of a CDMA receiver comprising a code control logic.

The PN code control logic unit in the present invention generates an impulse signal to provide a signal for controlling the output of the integral control signal and the comparator; An impulse inverter for inverting the signal output from the impulse generator; A switch for controlling an output signal of the comparator to an output of the impulse inverter; An exclusive or gate, an end gate, a retarder, and a latch combined to compare the output of the comparator through the switch with the output of the impulse generator to generate a logic signal for controlling the PN code; An AND gate which phase-delays the latch output by multiplying the latch output with an externally input clock signal for duty cycle adjustment; According to an output of the AND gate, a multiplexer which selects one of a clock input signal such as chip time and a constant having a level of "0" and outputs the PN code generation control signal may be configured.

1 is a block diagram of a serial synchronization tracking circuit of a conventional CDMA receiver.

2A is a block diagram of a serial synchronization tracking circuit of a CDMA receiver according to the present invention.

Figure 2b is a detailed view of the PN code control logic portion of Figure 2a

3 is an integrator dump output waveform diagram of FIG. 2A;

4 is a multiplexer output waveform diagram of FIG. 2A;

<Explanation of symbols for main parts of the drawings>

10: multiplier 11: PN code generator

13 band pass filter 14 envelope detection unit

15: integrator 16: comparator

100: PN code control logic section 121: impulse generator

122: impulse inverter 123: switch

124: Exclusive Orgate 125, 127, 130: Andgate

126, 128: delay 129: latch

131: multiplexer 132: constant generator

Hereinafter, a configuration of a pseudo noise code control circuit of a CDMA receiver according to the present invention will be described in detail with reference to the accompanying drawings.

2A is a block diagram of a pseudo noise code control circuit of a CDMA receiver according to an embodiment of the present invention. g (t-iTc) Multiplier 10 multiplies the received input signal vr (r) by a band pass filter (BPF) 13 that passes only signal components of a required frequency band among the output signal vr (t) of the multiplier. And an envelope detector 14 for detecting the energy, an integrator 15 for integrating the detected energy, a comparator 16 for comparing the energy of the integrated signal with a signal reference value, A PN code control logic unit for outputting the PN code control signal according to the comparison output of the comparator using digital elements (logic gate, latch circuit, delay circuit, multiplexer, switch, etc.) and an externally controllable clock signal 100).

FIG. 2B is a circuit diagram showing an example of the configuration of the PN code control logic unit 100 in the configuration of the present invention in detail. A signal for generating an impulse signal to control the output of the integral control signal S3 and the comparator. Impulse generator 121 for providing a, an impulse inverter 122 for inverting the signal output from the impulse generator, and a switch to control the output signal (S2) of the comparator to the output of the impulse inverter 122 123 and an exclusive or gate 124 and two end gates 125 and 127 for generating a logic signal for controlling the PN code by comparing the output of the comparator passing through the switch with the output of the impulse generator. And an AND gate 130 for delaying the latch output by multiplying the latch output by a delay unit 126 (128) and a latch 129 and an externally input clock signal S6 for duty cycle adjustment. Wow The multiplexer 131 which selects one of the clock input signal S5 such as the chip time and the output of the constant generator 132 having the level "0" according to the output of the AND gate, and outputs it as the PN code generation control signal S4. The configuration is shown.

3 illustrates a dump output of the integrator, and FIG. 4 illustrates a switching output of the multiplexer. Referring to these drawings, the operation of the serial synchronization search of the CDMA receiver in the present invention will be described. As follows.

When the receiving signal is detected at the receiving end, first, the PN code generating unit 11 performs the same PN code as the PN code generated by the transmitter. g (t-iTc) ) And receive it via multiplier 10 Multiply by) to remove the PN Code.

The signal vr (t) multiplied with the PN code is passed through the band pass filter 13 and the envelope detector 14 in turn, and the energy of the signal is detected. Integrate by the number of chips.

The energy passing through the integral part 15 is input to the comparator 16 and compared with an arbitrary reference value. In this case, when the integrated energy is higher than the reference value, the energy passes through the comparator.

At this time, when the PN code is found and the integral value is larger than a predetermined reference value, this state is a state in which the PN code generated by the PN code generator 11 matches the PN code of the received signal. Therefore, the multiplexer 131 of the PN code control logic unit 100 according to the present invention has an action of a switch 123 using an output of the comparator, an exclusive or gate (XOR) 124, and a logic AND gate 127 (130). ) And the output of the constant generator 132 having a level of "0" by the action of the delayer 128 and the latch 129, and thus the output of the PN code generation control signal S4 is cut off to generate the PN code. The unit 11 no longer changes the PN code, and the desired PN code is kept as it is.

However, if the received PN code and the PN code produced by the receiver do not match, the signal Vr (t) multiplied by the PN code is also a spread signal and has a wide spectrum bandwidth. Since the signal is spread with power, the output of the bandpass filter 13 also has a small power distribution.

Because of this small power, the output of the bandpass filter 13 and the output of the envelope detector 14 are also small, and the integrated value is smaller than the reference signal, so that when the energy passing through the integrator 15 is less than the reference value, This state is a state in which the PN code generated by the PN code generator 11 does not coincide with the PN code of the received signal.

Therefore, the multiplexer 131 of the PN code control logic unit 100 according to the present invention has the opposite operation of the switch 123 using the output of the comparator, the exclusive or gate (XOR) 124, and the logic end gate. The clock signal S5 such as chip time is selected by the operation of the counter 130, the delay 128, and the latch 129, and accordingly the output of the PN code generation control signal S4 is supplied to supply the PN code. The generator 11 keeps changing the PN code. At this time, the amount converted by the PN code is controlled by the clock input signal S6 supplied from the outside for the duty cycle control.

According to the present invention as described above, the initial synchronization of the CDMA receiver is flexibly adjusted by easily adjusting the phase delay input value by performing serial initial synchronization search using simple digital logic at the CDMA receiver and simply adjusting the duty cycle value. It can be tailored and has the advantage of flexibility in hardware configuration.

Claims (2)

PN code of the CDMA receiver for despreading the received signal using the PN code output from the PN code generating means to detect the energy, comparing the detected energy integrated value with an arbitrary reference value and searching for the PN code as a result of the comparison. In the control circuit, And a PN code control logic unit for outputting the PN code control signal according to the comparison output of the comparator using a plurality of digital elements and an externally controllable clock signal. 2. The apparatus of claim 1, wherein the PN code control logic unit comprises: an impulse generator for generating an impulse signal to provide a signal for controlling the output of the integral control signal and the comparator; An impulse inverter for inverting the signal output from the impulse generator; A switch for controlling an output signal of the comparator to an output of the impulse inverter; An exclusive or gate, an end gate, a retarder, and a latch combined to compare the output of the comparator through the switch with the output of the impulse generator to generate a logic signal for controlling the PN code; An AND gate which phase-delays the latch output by multiplying the latch output with an externally input clock signal for duty cycle adjustment; And a multiplexer which selects one of a clock input signal such as chip time and a constant having a level of "0" according to the output of the AND gate, and outputs the PN code generation control signal to the PN code control circuit of the CDMA receiver.