KR20000003590A - Semiconductor equipment having esd device - Google Patents
Semiconductor equipment having esd device Download PDFInfo
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- KR20000003590A KR20000003590A KR1019980024850A KR19980024850A KR20000003590A KR 20000003590 A KR20000003590 A KR 20000003590A KR 1019980024850 A KR1019980024850 A KR 1019980024850A KR 19980024850 A KR19980024850 A KR 19980024850A KR 20000003590 A KR20000003590 A KR 20000003590A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
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Abstract
본 발명은 ESD 소자가 구비된 반도체장치에 관한 것으로, CMOS 구조의 데이타 출력 드라이버의 반도체 집적회로의 ESD 보호회로에 있어서 PMOS의 Vcc 단자쪽에 n+ Vcc 픽업을 부팅 콘택 개념으로 p+에 인접하게 구조를 형성하여 Vss가 포지티브인 모드에서 PMOS에서 Vcc를 통하여 Vss로 가는 PNPN 패스의 저항을 극소화하여 메인 바이폴라(main bipolar)인 NMOS 트랜지스터를 보호함으로써 ESD 특성을 개선하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with an ESD device. In the ESD protection circuit of a semiconductor integrated circuit of a data output driver having a CMOS structure, an n + Vcc pickup is formed adjacent to p + on the Vcc terminal side of a PMOS as a boot contact concept. By minimizing the resistance of the PNPN pass from PMOS to Vss through Vcc in the positive Vss mode, the main bipolar NMOS transistor is protected to improve ESD characteristics and thereby improve the characteristics and reliability of semiconductor devices. Technology.
Description
본 발명은 ESD 소자가 구비된 반도체장치에 관한 것으로서, 특히 CMOS 구조의 데이타 출력 드라이버의 반도체 집적회로의 ESD 보호회로에 있어서, PMOS의 Vcc쪽 단에 n+ Vcc 픽업을 부팅 콘택 개념으로 p+에 인접하게 구조를 형성하여 Vss가 포지티브인 모드에서 상기 PMOS의 Vcc를 통하여 Vss로 가는 PNPN 패스의 저항을 극소화하여 메인 바이폴라인 NMOS 트랜지스터를 보호하고, ESD 및 래치-업 특성을 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with an ESD device. In particular, in an ESD protection circuit of a semiconductor integrated circuit of a data output driver having a CMOS structure, n + Vcc pickup is placed adjacent to p + on the Vcc side of the PMOS as a boot contact concept. Forming the structure to minimize the resistance of the PNPN pass from the PMOS to Vss through the Vcc of the PMOS in positive mode to protect the main bipolar NMOS transistor, improve the ESD and latch-up characteristics, characteristics and reliability of the semiconductor device It is about a technique to improve.
일반적으로 반도체소자가 정전기 방전에 노출되었을 때 내부회로가 손상을 받게 되어 소자가 오동작하거나 신뢰성에 문제가 발생한다.In general, when a semiconductor device is exposed to an electrostatic discharge, the internal circuit is damaged, resulting in a malfunction of the device or a problem in reliability.
이러한 내부회로 손상은 정전기 방전때 입력단자를 통해 주입된 전하가 내부회로를 거쳐 최종적으로 다른 단자로 빠져나가면서 일으키는 주울(Joule)열로 인해 취약한 곳에서 정션 스파이킹(junction spiking), 산화막 균열(rupture) 현상 등을 일으키기 때문이다.This internal circuit damage is caused by junction spiking and oxide cracking in the place where the charge injected through the input terminal during electrostatic discharge is vulnerable to Joule heat, which is caused to finally escape to the other terminal through the internal circuit. This is because it causes a phenomenon.
그래서 이를 해결하기 위해서는 정전기 방전 때 주입된 전하가 내부회로를 통하여 빠져나가기 전에 입력 단에 주입된 전하를 곧바로 전원공급 단자 쪽으로 방전시킬 수 있는 정전기 방지용 회로를 삽입하여야만 정전기 방전으로 인한 반도체소자의 손상을 방지할 수 있는 것이다.Therefore, in order to solve this problem, it is necessary to insert an antistatic circuit capable of discharging the injected charge directly to the power supply terminal before the injected charge is discharged through the internal circuit to prevent damage to the semiconductor device due to the electrostatic discharge. It can be prevented.
도 1 에 도시된 종래기술 기술에 따른 CMOS 구조의 데이타 출력 드라이버를 ESD 보호회로로 사용하는 경우 도 2 에 도시된 바와 같이 Vss가 포지티브인 모드에서 Vcc를 통하여 Vss로 가는 PNPN 패스를 이용하여 메인 바이폴라인 NMOS 트랜지스터를 보호하는 점에 있어서 도 3 에 도시된 NMOS 구조보다는 ESD 내성 측면에서 유리하다.When the data output driver of the CMOS structure according to the prior art illustrated in FIG. 1 is used as an ESD protection circuit, as shown in FIG. 2, the main bipolar circuit uses a PNPN pass from Vcc to Vss in the Vss positive mode. In terms of protecting the NMOS transistor, it is advantageous in terms of ESD immunity rather than the NMOS structure shown in FIG.
그러나, 상기와 같은 종래기술에 따른 ESD 소자가 구비된 반도체장치는, n+ Vcc 픽업 까지의 n-웰 저항때문에 상기 PNPN 패스로의 전류가 줄어들어 ESD 내성이 약해지는 문제점이 있다.However, the semiconductor device having the ESD device according to the related art as described above has a problem that the current resistance to the PNPN pass decreases due to the n-well resistance up to n + Vcc pickup, thereby weakening the ESD resistance.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, Vss가 포지티브 모드에서 PMOS의 Vcc단자를 통하여 Vss단자로 통하는 PNPN 패스의 저항을 극소화하여 메인 바이폴라인 NMOS 트랜지스터를 보호하여 ESD 특성을 향상시키는 ESD 소자가 구비된 반도체장치를 제공하는데 그 목적이 있다.In order to solve the above-mentioned problems of the prior art, ESD in which the Vss minimizes the resistance of the PNPN pass through the Vcc terminal of the PMOS to the Vss terminal in the positive mode protects the main bipolar NMOS transistor to improve the ESD characteristics. It is an object of the present invention to provide a semiconductor device with an element.
도 1 내지 도 3 은 종래기술에 따른 CMOS 구조의 데이타 출력 드라이버를 ESD 소자로 사용하는 반도체장치의 회로도 및 단면도.1 to 3 are circuit diagrams and cross-sectional views of a semiconductor device using a data output driver having a CMOS structure according to the prior art as an ESD device.
도 4 및 도 5 는 본 발명의 제1실시예에 따른 ESD 소자가 구비된 반도체장치의 단면도.4 and 5 are cross-sectional views of a semiconductor device having an ESD device according to a first embodiment of the present invention.
도 6 및 도 7 은 본 발명의 제2실시예에 따른 ESD 소자가 구비된 반도체장치의 단면도.6 and 7 are cross-sectional views of a semiconductor device having an ESD device according to a second embodiment of the present invention.
도 8 은 NMOS 필드 트랜지스터와 PMOS 필드 트랜지스터를 ESD 보호회로로 사용하는 반도체장치의 ESD 보호회로.8 is an ESD protection circuit of a semiconductor device using an NMOS field transistor and a PMOS field transistor as an ESD protection circuit.
도 9 는 본 발명의 제3실시예에 따른 상기 도 8 의 PMOS 필드 트랜지스터의 단면도.9 is a cross-sectional view of the PMOS field transistor of FIG. 8 in accordance with a third embodiment of the present invention.
도 10 은 본 발명의 제4실시예에 따른 상기 도 8 의 NMOS 필드 트랜지스터의 단면도.10 is a cross-sectional view of the NMOS field transistor of FIG. 8 in accordance with a fourth embodiment of the present invention.
도 11 은 본 발명의 제5실시예에 따른 상기 도 8 의 NMOS 필드 트랜지스터의 단면도.FIG. 11 is a cross-sectional view of the NMOS field transistor of FIG. 8 according to the fifth embodiment of the present invention; FIG.
도 12 는 본 발명의 제6실시예에 따른 상기 도 8 의 PMOS 필드 트랜지스터의 단면도.12 is a cross-sectional view of the PMOS field transistor of FIG. 8 according to the sixth embodiment of the present invention;
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
10 : n+ Vcc 픽업 20 : p+ 확산층10: n + Vcc pickup 20: p + diffusion layer
30 : p+ Vss 픽업 40 : n+ 확산층30: p + Vss pickup 40: n + diffusion layer
이상의 목적을 달성하기 위하여 본 발명에 따른 ESD 소자가 구비된 반도체장치는,In order to achieve the above object, a semiconductor device having an ESD device according to the present invention is provided.
Vcc단자와 연결되어 있는 PMOS와 Vss단자와 연결되어 있는 NMOS가 구비된 CMOS 구조의 데이타 출력 드라이버가 구비되는 ESD 소자가 구비된 반도체장치에 있어서,A semiconductor device having an ESD device including a data output driver having a CMOS structure having a PMOS connected to a Vcc terminal and an NMOS connected to a Vss terminal.
상기 Vcc단자와 접속되어 있는 p+ 확산층 사이에 n+ Vcc 픽업을 구비하는 것을 특징으로 한다.An n + Vcc pickup is provided between the p + diffusion layers connected to the Vcc terminal.
또한, 이상의 목적을 달성하기 위하여 본 발명에 따른 ESD 소자가 구비된 반도체장치는,In addition, the semiconductor device provided with an ESD device according to the present invention in order to achieve the above object,
Vcc단자와 연결되어 있는 PMOS 필드 트랜지스터와 Vss단자와 연결되어 있는 NMOS 필드 트랜지스터가 구비된 ESD 소자가 구비된 반도체장치에 있어서,A semiconductor device comprising an ESD device having a PMOS field transistor connected to a Vcc terminal and an NMOS field transistor connected to a Vss terminal.
상기 Vcc단자와 접속되는 p+ 확산층 사이에 n+ Vcc 픽업이 구비되는 것을 특징으로 한다.An n + Vcc pickup is provided between the p + diffusion layers connected to the Vcc terminal.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 4 는 본 발명의 제1실시예에 따른 CMOS 구조의 데이타 출력 드라이버의 반도체 집적소자의 ESD 보호회로로서, PMOS의 Vcc 단자쪽에 n+ Vcc 픽업(10)이 부팅 콘택(butting contact)개념으로 p+확산층(20)과 인접하게 형성되어 있다. 이는 Vss가 포지티브인 모드에서 상기 Vcc 단자를 통하여 Vss단자로 가는 PNPN 패스의 저항을 극소화하여 메인 바이폴라인 NMOS 트랜지스터를 보호한다.FIG. 4 is an ESD protection circuit of a semiconductor integrated device of a data output driver having a CMOS structure according to a first embodiment of the present invention, in which a n + Vcc pickup 10 is attached to a Vcc terminal side of a PMOS with a booting contact concept. It is formed adjacent to (20). This protects the main bipolar NMOS transistor by minimizing the resistance of the PNPN pass through the Vcc terminal to the Vss terminal in the positive Vss mode.
도 5 는 PMOS의 Vcc 단자쪽에 n+ Vcc 픽업(10)으로 p+확산층(20)이 고립되게 형성한다. 이는 상기 도 4 와 같은 효과를 갖는다.FIG. 5 shows that the p + diffusion layer 20 is isolated by the n + Vcc pickup 10 on the Vcc terminal side of the PMOS. This has the same effect as in FIG. 4.
도 6 은 본 발명의 제2실시예에 따른 CMOS구조의 데이타 출력 드라이버의 반도체 집적소자의 ESD 보호회로로서, NMOS의 Vss 단자쪽에 p+ Vss 픽업(30)이 부팅 콘택 개념으로 n+확산층(40)에 인접하게 형성되어 있다. 이때, NMOS에서 패드와 연결된 n+ 확산층으로 입력된 전류는 Vss 단자와 연결된 PMOS 의 n+확산층(40)에 인접한 p+ Vss픽업(30)을 통하여 흐르게 된다.6 is an ESD protection circuit of a semiconductor integrated device of a data output driver having a CMOS structure according to a second embodiment of the present invention, in which a p + Vss pickup 30 is connected to an n + diffusion layer 40 in a boot contact concept at a Vss terminal side of an NMOS. It is formed adjacent. At this time, the current input to the n + diffusion layer connected to the pad in the NMOS flows through the p + Vss pickup 30 adjacent to the n + diffusion layer 40 of the PMOS connected to the Vss terminal.
도 7 은 CMOS 구조의 데이타 출력 드라이버의 반도체 집적회로의 ESD 보호회로로서, NMOS의 Vss 단자쪽의 p+ Vss 픽업(30)은 n+확산층(40)으로 고립되도록 형성되어 있다.Fig. 7 is an ESD protection circuit of a semiconductor integrated circuit of a data output driver having a CMOS structure, wherein the p + Vss pickup 30 at the Vss terminal side of the NMOS is isolated to the n + diffusion layer 40.
도 8 은 NMOS 필드 트랜지스터와 PMOS 필드 트랜지스터를 ESD 보호회로로 사용하는 반도체 집적소자의 ESD 보호회로로서, Vcc단에 PMOS 필드 트랜지스터의 소오스영역과 게이트가 Vcc에 접지된 게이트 다이오드 트랜지스터(TR2)의 소오스영역이 병렬으로 연결되어 있고, 상기 PMOS 필드 트랜지스터와 게이트 다이오드 트랜지스터(TR2)의 드레인영역에 NMOS 필드 트랜지스터와 게이트 다이오드 트랜지스터(TR1)의 드레인영역이 각각 직렬으로 연결되어 있으며, 패드에 연결된 저항 R 이 상기 각 트랜지스터의 드레인영역에 연결되어 내부회로와 접속된다.8 is an ESD protection circuit of a semiconductor integrated device using an NMOS field transistor and a PMOS field transistor as an ESD protection circuit, wherein a source region of the PMOS field transistor and a gate of the gate diode transistor TR2 having the gate grounded to Vcc at the Vcc stage. Regions are connected in parallel, drain regions of the NMOS field transistor and the gate diode transistor TR1 are connected in series to drain regions of the PMOS field transistor and the gate diode transistor TR2, and a resistor R connected to the pad is provided. It is connected to the drain region of each transistor and is connected to the internal circuit.
도 9 는 본 발명의 제3실시예에 따라 상기 도 8 과 같은 ESD 보호회로를 반도체 집적소자의 ESD 보호회로로 사용하는 경우로서, PMOS 필드 트랜지스터의 Vcc단자쪽에 n+ Vcc 픽업(10)을 부팅 콘택 개념으로 p+확산층(20)에 인접하게 형성되어 있다.FIG. 9 illustrates a case in which an ESD protection circuit as shown in FIG. 8 is used as an ESD protection circuit of a semiconductor integrated device according to a third embodiment of the present invention, wherein n + Vcc pickup 10 is booted on the Vcc terminal side of a PMOS field transistor. The concept is formed adjacent to the p + diffusion layer 20.
도 10 은 본 발명의 제4실시예에 따라 상기 도 8 과 같은 ESD 보호회로를 반도체 집적소자의 ESD 보호회로로 사용하는 경우로서, NMOS 필드 트랜지스터의 Vcc단자쪽에 n+ Vcc 픽업(10)이 p+확산층(20)에 고립되게 형성되어 있다.FIG. 10 illustrates a case in which an ESD protection circuit as shown in FIG. 8 is used as an ESD protection circuit of a semiconductor integrated device according to a fourth embodiment of the present invention, in which an n + Vcc pickup 10 is connected to a V + terminal of an NMOS field transistor. It is formed so that it is isolated in 20.
도 11 은 본 발명의 제5실시예에 따라 상기 도 8 과 같은 ESD 보호회로를 반도체 집적소자의 ESD 보호회로로 사용하는 경우로서, NMOS 필드 트랜지스터의 Vss단자쪽에 p+ Vss 픽업(30)을 부팅 콘택 개념으로 n+확산층(40)에 인접하게 형성되어 있다.FIG. 11 illustrates a case in which an ESD protection circuit as shown in FIG. 8 is used as an ESD protection circuit of a semiconductor integrated device according to a fifth embodiment of the present invention, wherein a p + Vss pickup 30 is connected to a Vss terminal of an NMOS field transistor The concept is formed adjacent to the n + diffusion layer 40.
도 12 는 본 발명의 제6실시예에 따라 상기 도 8 과 같은 ESD 보호회로를 반도체 집적소자의 ESD 보호회로로 사용하는 경우로서, NMOS 필드 트랜지스터의 Vss단자쪽에 p+ Vss 픽업(30)이 n+확산층(40)에 고립되게 형성되어 있다.FIG. 12 illustrates a case in which an ESD protection circuit as shown in FIG. 8 is used as an ESD protection circuit of a semiconductor integrated device according to a sixth embodiment of the present invention, wherein p + Vss pickup 30 is n + diffused on the Vss terminal side of an NMOS field transistor. It is formed in isolation from 40.
상기 제3실시예 내지 제6실시예는 상기 도 8 의 회로에서 R 또는 게이트 다이오드 트랜지스터(TR1) 또는 게이트 다이오드 트랜지스터(TR2) 가 없어도 도 9 내지 도 12 와 같이 실시될 수 있다.9 to 12 may be implemented in the circuit of FIG. 8 without R or the gate diode transistor TR1 or the gate diode transistor TR2.
이상에서 설명한 바와 같이 본 발명에 따른 ESD 소자가 구비된 반도체장치는, CMOS 구조의 데이타 출력 드라이버의 반도체 집적회로의 ESD 보호회로에 있어서 PMOS의 Vcc 단자쪽에 n+ Vcc 픽업을 부팅 콘택 개념으로 p+에 인접하게 구조를 형성하여 Vss가 포지티브인 모드에서 PMOS에서 Vcc를 통하여 Vss로 가는 PNPN 패스의 저항을 극소화하여 메인 바이폴라인 NMOS 트랜지스터를 보호함으로써 ESD 특성을 개선하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the semiconductor device having an ESD device according to the present invention, in the ESD protection circuit of a semiconductor integrated circuit of a data output driver having a CMOS structure, n + Vcc pickup is adjacent to p + as a boot contact concept on the Vcc terminal side of a PMOS. This structure is designed to minimize the resistance of the PNPN pass from PMOS to Vss through Vcc in the positive Vss mode to protect the main bipolar NMOS transistor, thereby improving ESD characteristics and thereby improving the characteristics and reliability of semiconductor devices. There is an advantage.
Claims (9)
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| KR1019980024850A KR20000003590A (en) | 1998-06-29 | 1998-06-29 | Semiconductor equipment having esd device |
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| KR1019980024850A KR20000003590A (en) | 1998-06-29 | 1998-06-29 | Semiconductor equipment having esd device |
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| KR20000003590A true KR20000003590A (en) | 2000-01-15 |
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| KR100369361B1 (en) * | 2001-03-30 | 2003-01-30 | 주식회사 하이닉스반도체 | Integration circuit with self-aligned silicided ESD protection transistors |
| KR100676699B1 (en) * | 2004-10-27 | 2007-01-31 | 삼성전자주식회사 | Polygon mirror motor assembly |
| KR100878439B1 (en) * | 2007-08-30 | 2009-01-13 | 주식회사 실리콘웍스 | ESD protection device at output driver stage |
| KR100909303B1 (en) * | 2005-09-02 | 2009-07-24 | 캐논 가부시끼가이샤 | Optical scanning device |
| KR101418044B1 (en) * | 2012-12-06 | 2014-08-13 | 주식회사 케이이씨 | Device for protecting electrostactic discharge |
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| JPH06275787A (en) * | 1993-03-19 | 1994-09-30 | Toshiba Corp | Cmosfet circuit device |
| US5406105A (en) * | 1993-08-18 | 1995-04-11 | Goldstar Electron Co., Ltd. | Electro static discharge protecting circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100369361B1 (en) * | 2001-03-30 | 2003-01-30 | 주식회사 하이닉스반도체 | Integration circuit with self-aligned silicided ESD protection transistors |
| KR100676699B1 (en) * | 2004-10-27 | 2007-01-31 | 삼성전자주식회사 | Polygon mirror motor assembly |
| KR100909303B1 (en) * | 2005-09-02 | 2009-07-24 | 캐논 가부시끼가이샤 | Optical scanning device |
| KR100878439B1 (en) * | 2007-08-30 | 2009-01-13 | 주식회사 실리콘웍스 | ESD protection device at output driver stage |
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| KR101418044B1 (en) * | 2012-12-06 | 2014-08-13 | 주식회사 케이이씨 | Device for protecting electrostactic discharge |
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