KR19980065713A - Method for manufacturing semiconductor device with improved step - Google Patents

Abstract

Disclosed is a method of manufacturing a semiconductor device having improved steps, which can improve a problem caused by a difference in density of a pattern in a chemical mechanical polishing (CMP) process. To this end, the present invention comprises the steps of forming a gate pattern and a bit line on the center portion where the chip is formed on the semiconductor substrate and the edge portion where the dummy chip is formed, and forming an insulating film on the center portion and the edge portion to compensate for the step difference of the edge portion. And chemical mechanical polishing the wafer on which the insulating film is formed.

Description

A method of manufacturing a semiconductor device having improved step.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor device having improved steps, which can improve a problem caused by a difference in density of a pattern in a chemical mechanical polishing (CMP) process. will be.

As the manufacturing technology of semiconductor devices develops, the size of semiconductor devices becomes smaller and the vertical structure thereof becomes more complicated. In response, high performance of stepper is required in the photolithography process, and the depth of focus becomes shallow due to the increase in the numerical aperture of the lens and the short wavelength of light in the exposure process. If there is a step on the surface of the device, sufficient resolution cannot be obtained. Accordingly, in order to eliminate surface irregularities and steps, global planarization of the surface of the semiconductor device is required, and a chemical mechanical polishing (CMP) technique, which is one of the global planarization methods, has been in the spotlight.

Chemical mechanical polishing (CMP) is applied in many applications because of the simplicity of the process compared to etchback, low cost, and the advantages of generating fewer particles, but also causes some other problems.

1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1, a plan view illustrating a die formed on a wafer. A center portion 3 in which chips are formed on the wafer 1 and an edge portion 5 in which the dummy chips 7 are formed will be described with reference to the plan view of the wafer. Typically, a wafer is formed of hundreds to thousands of square chips (also called dies) according to the size of the chip to be formed. In the center portion 3 of the wafer, these chips are formed without any damage, but the edge portion 5 ) Will generate a dummy chip (7) that is not fully equipped with a square. In general, a pattern is not formed in the edge portion 5 in which the dummy chips 7 are generated in the manufacturing process of the semiconductor device.

2 is a cross-sectional view illustrating a step generated when a gate pattern is not formed in a region where a dummy chip is located as described above in the process of forming a gate pattern. The step formed in the area where the dummy chip is generated may damage the normal chip pattern in the center part in the chemical mechanical polishing (CMP) process, which is performed in a subsequent process, or the photoresist may flow in the area where the step is severe. This is happening. In the drawing, reference numeral 10 denotes a central portion where a normal chip is formed, 12 denotes an edge portion 12 on which a dummy chip is formed, 14 denotes a trench region in which a semiconductor substrate is etched, 16 denotes a gate pattern, and 18 denotes a gate pattern. 11 denotes an insulating film for flattening the step formed by the semiconductor substrate. However, it can be seen that a step is formed because the pattern is not formed at the edge portion 12.

The technical problem to be achieved by the present invention is to form a pattern on the edge of the wafer that does not form a pattern of the semiconductor device that improves the step that can solve the problem in the chemical mechanical polishing process caused by the difference in density of the pattern formed on the wafer It is to provide a manufacturing method.

1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

3 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device having improved steps according to the present invention.

Brief description of symbols for the main parts of the drawings

100: semiconductor substrate, 102: trench,

104: gate pattern, 106: first insulating film,

108: wafer edge portion, 110: wafer center portion,

112: bit line pattern, 114: second insulating film,

116: capacitor pattern, 118: third insulating film

In order to achieve the above technical problem, the present invention comprises the steps of forming a gate pattern and a bit line on the center portion where the chip is formed on the semiconductor substrate and the edge portion where the dummy chip is formed, and forming an insulating film on the center portion and the edge portion Comprising a step of compensating the step difference, and the step of performing a chemical mechanical polishing of the wafer on which the insulating film is formed.

According to the present invention, a dummy pattern may also be formed on the edge of the wafer to solve the problems occurring in the chemical mechanical polishing (CMP) process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device having improved steps according to an embodiment of the present invention.

3 is a cross-sectional view when a dummy pattern is formed at an edge portion of a wafer in a process of forming a gate pattern, stacking an insulating film, and performing a chemical mechanical polishing process in a semiconductor device manufacturing process. In detail, the trench 102 is formed in the semiconductor substrate 100, and the gate pattern 104 is formed. Subsequently, a first insulating layer 106 is formed to planarize a step generated in the process of forming the gate pattern. In the present invention, the dummy gate pattern is formed on the edge portion 108 of the wafer in the same manner as the center portion 110 to suppress the error caused by the step in the chemical mechanical polishing process, and the gate pattern 104 in the center portion 110. The problem of damage in the chemical mechanical polishing process of the first insulating film 106 can be prevented.

4 is a cross-sectional view of a dummy pattern formed at an edge of a wafer in a process of forming a bit line pattern, stacking an insulating layer, and performing a chemical mechanical polishing process in a semiconductor device manufacturing process. In detail, the cross-sectional view when the second insulating layer 114 is formed after the double contact hole and the bit line pattern 112 are formed in the resultant of FIG. 3. Since the dummy bit line pattern 112 is formed at the edge portion 108 of the wafer, the bit line pattern 112 at the center portion 110 may be prevented from being damaged during the chemical mechanical polishing process of the second insulating layer 114. can do.

Referring to FIG. 5, a contact hole is formed on the resultant of FIG. 4, and a capacitor pattern 116 is formed, and a third insulating layer 118, for example, an undoped silica glass (USG), is formed thereon. It is sectional drawing when formed. Since the step difference is sufficiently compensated while the gate pattern 104 and the bit line pattern 112 are formed in the processes of FIGS. 3 and 4, the photoresist is formed at the edge of the wafer in the photolithography process of the contact hole for forming the capacitor pattern 116. The problem that flows down to (108) can be solved. In this case, the third insulating film 118 may be formed to have a sufficient thickness of 3500 to 5000 mm 3 to prevent damage to the central portion of the pattern during the final chemical mechanical polishing process of the third insulating film.

The present invention is not limited to the above-described embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs.

Therefore, according to the present invention described above, a dummy pattern is formed on the edge of the wafer in the manufacturing process of the semiconductor device to suppress the planarization error generated in the chemical mechanical polishing (CMP) process, the center portion of the wafer in the chemical mechanical polishing process A method of manufacturing a semiconductor device having improved steps can be realized, which prevents a problem that a pattern formed on a chip in the chip is damaged and solves a problem in which a photoresist flows down to a lower step in a photographic process.

Claims (1)

Forming a gate pattern and a bit line on a center portion where a chip is formed and an edge portion where a dummy chip is formed on a semiconductor substrate; Forming an insulating film on the center portion and the edge portion to compensate for the step difference of the edge portion; And chemical mechanical polishing the wafer having the insulating film formed thereon.