KR100335770B1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR100335770B1 KR100335770B1 KR1019990024210A KR19990024210A KR100335770B1 KR 100335770 B1 KR100335770 B1 KR 100335770B1 KR 1019990024210 A KR1019990024210 A KR 1019990024210A KR 19990024210 A KR19990024210 A KR 19990024210A KR 100335770 B1 KR100335770 B1 KR 100335770B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 238000005498 polishing Methods 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims description 27
- 150000004767 nitrides Chemical class 0.000 claims description 21
- 239000010410 layer Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 4
- 239000011324 bead Substances 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract 2
- 238000001459 lithography Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, CMP 공정에 의해 평탄화를 실현하는 반도체 소자의 제조 방법중 감광제 코팅후 웨이퍼 가장자리에서 비정상적으로 두껍게 코팅된 감광제를 제거하면서 생성되는 EBR(edge bead removal) 라인 폭을 마스크 공정별로 최적화하여 후속 CMP 공정시 이 부분에서의 과도한 연마를 최소화하여 하부 패턴이 노출되는 현상을 방지하고 폴리실리콘막의 결함 발생을 최소화한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, wherein an edge bead removal (EBR) line is generated while removing an abnormally thick photoresist at the edge of a wafer after photoresist coating in a method of fabricating a semiconductor device to realize planarization by a CMP process. The width is optimized for each mask process to minimize excessive polishing in this area during subsequent CMP processes to prevent the underlying pattern from being exposed and to minimize the occurrence of defects in the polysilicon film.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 CMP 공정에 의해 평탄화를 실현하는 반도체 소자의 제조 방법중 감광제 코팅후 웨이퍼 가장자리에서 비정상적으로 두껍게 코팅된 감광제를 제거하면서 생성되는 EBR(edge bead removal) 라인 폭을 마스크 공정별로 최적화하여 후속 CMP 공정시 이 부분에서의 과도한 연마를 최소화하여 하부 패턴이 노출되는 현상을 방지하고 폴리실리콘막의 결함 발생을 최소화하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, an EBR (edge bead removal) produced by removing an abnormally thick photosensitive agent from the edge of a wafer after coating the photosensitive agent in a method of manufacturing a semiconductor device that realizes planarization by a CMP process. The present invention relates to a method of fabricating a semiconductor device by optimizing line widths for each mask process, minimizing excessive polishing in this region during subsequent CMP processes, thereby preventing the underlying pattern from being exposed and minimizing defects in the polysilicon film.
도 1(a) 및 도 1(b)는 종래의 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도로서, 종래의 방법에 의해 EBR 영역을 형성한 경우를 나타낸다.1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device, and show a case where an EBR region is formed by a conventional method.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 제 1 폴리실리콘막(12) 및 마스크막(13)을 형성한 후 워드라인 마스크를 이용한 리소그라피 공정 및 식각 공정을 실시하여 워드라인을 형성한다. 워드라인 패턴을 형성할 때 생성되는 EBR 라인(L1) 경계(B1)는 웨이퍼 가장자리에서 5㎜ 안쪽에 위치하도록 한다. 전체 구조 상부에 질화막(14)을 형성한 후 주변 회로 영역(B)만을 노출시키는 마스크를 이용한 리소그라피 공정 및 전면식각 공정으로 주변 회로 영역(B)의 질화막(14)을 제거한다. 이때, 주변 회로 영역(B)의 워드라인의 측벽에는 질화막 스페이서(14A)가 형성된다. 질화막을 제거할 때 생성되는 EBR 라인(L2) 경계(B2)는 워드라인 패턴을 형성할 때 생성되는 EBR 라인(L1)의 경계(B1)보다 웨이퍼 가장자리에서 웨이퍼 안쪽에 위치시킨다. 전체 구조 상부에 층간 절연막(15)을 증착하고, 셀 영역(A)의 워드라인 사이의 반도체 기판(11)이 노출되도록 콘택 홀(16)을 형성한다. 콘택 홀(16)을 형성하기 위한 식각 공정을 실시할 때 형성되는 EBR 라인(L3) 경계(B3)는 워드라인을 형성할 때 형성되는 EBR 라인(L1) 경계(B1)보다 웨이퍼 가장자리에서 웨이퍼 안쪽으로 형성되고, 질화막을 제거할 때 생성되는 EBR 라인(L2) 경계(B2)보다 웨이퍼 가장자리쪽으로 형성되도록 한다.Referring to FIG. 1A, a first polysilicon layer 12 and a mask layer 13 are formed on a semiconductor substrate 11, and then a word line is formed by performing a lithography process and an etching process using a word line mask. Form. The EBR line L1 boundary B1 generated when forming the word line pattern is positioned 5 mm from the edge of the wafer. After the nitride film 14 is formed over the entire structure, the nitride film 14 of the peripheral circuit region B is removed by a lithography process and a front etching process using a mask that exposes only the peripheral circuit region B. In this case, a nitride film spacer 14A is formed on the sidewall of the word line of the peripheral circuit region B. The EBR line L2 boundary B2 generated when the nitride film is removed is positioned inside the wafer at the edge of the wafer than the boundary B1 of the EBR line L1 generated when the word line pattern is formed. The interlayer insulating layer 15 is deposited on the entire structure, and the contact hole 16 is formed so that the semiconductor substrate 11 between the word lines of the cell region A is exposed. The EBR line L3 boundary B3 formed when performing an etching process for forming the contact hole 16 is inside the wafer at the wafer edge than the EBR line L1 boundary B1 formed when the word line is formed. It is formed so as to be formed toward the wafer edge than the EBR line (L2) boundary (B2) generated when the nitride film is removed.
도 1(b)를 참조하면, 콘택 홀(16)이 매립되도록 전체 구조 상부에 제 2 폴리실리콘막(17)을 증착한 후 전면 식각하여 콘택 홀(16)내에 플러그(17A)를 형성한다. CMP 공정을 실시하여 층간 절연막(15)이 셀 영역(A)에서 일정 두께(t1)로 잔류하도록 한다. 이때, EBR 영역(C)에서 과도한 연마로 인해 층간 절연막(15)의 두께(t2)가 얇게 형성되므로 마스크 산화막(13) 및 플러그(17A)를 형성하기 위해 형성된 제 2 폴리실리콘막(17)이 노출되게 된다.Referring to FIG. 1B, a plug 17A is formed in the contact hole 16 by etching the entire surface of the second polysilicon layer 17 on the entire structure such that the contact hole 16 is embedded. The CMP process is performed so that the interlayer insulating film 15 remains at a predetermined thickness t1 in the cell region A. FIG. At this time, since the thickness t2 of the interlayer insulating film 15 is formed to be thin due to excessive polishing in the EBR region C, the second polysilicon film 17 formed to form the mask oxide film 13 and the plug 17A is formed. Exposed.
상기와 같이 EBR 영역(C)에서 하부 패턴이 노출되면 소자의 결함을 발생시켜 신뢰성을 저하시킨다.As described above, when the lower pattern is exposed in the EBR region C, defects of the device are generated, thereby lowering reliability.
따라서, 본 발명은 CMP 공정시 EBR 영역에서 하부 패턴이 노출되는 현상을 방지하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the reliability of the device by preventing the lower pattern is exposed in the EBR region during the CMP process.
상술한 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 제 1 폴리실리콘막 및 마스크 산화막을 형성한 후 패터닝하여 셀 영역 및 주변 회로 영역에 워드라인 패턴을 형성하고, 이때 생성되는 EBR 라인은 웨이퍼 가장자리로부터 웨이퍼 안쪽으로 소정 간격 이격되도록 하는 단계와, 전체 구조 상부에 질화막을 증착한 후 주변 회로 영역의 질화막만 제거되도록 식각 공정을 실시하고, 이때 생성되는 EBR 라인은 상기 워드라인 패턴을 형성할 때 생성되는 EBR 라인보다 웨이퍼 가장자리쪽으로 생성되도록 하는 단계와, 전체 구조 상부에 제 1 층간 절연막을 형성한 후 1차 CMP 공정을 실시하여 연마하는 단계와, 상기 셀 영역의 제 1 층간 절연막 및 질화막을 식각하여 제 1 콘택 홀을 형성하고, 이때 생성되는 EBR 라인은 상기 질화막을 식각할 때 생성되는 EBR 라인보다 웨이퍼 가장자리쪽으로 생성되도록 하는 단계와, 상기 제 1 콘택 홀이 매립되도록 전체 구조 상부에 제 2 폴리실리콘막을 형성한 후 2차 CMP 공정을 실시하여 상기 제 2 폴리실리콘막 및 제 1 층간 절연막을 연마하여 폴리실리콘 플러그를 형성하는 단계와, 전체 구조 상부에 제 2 층간 절연막을 형성한 후 상기 셀 영역의 폴리실리콘 플러그가 노출되도록 제 2 콘택 홀을 형성하고, 이때 생성되는 EBR 라인은 상기 제 1 콘택 홀을 형성할 때 생성되는 EBR 라인보다 웨이퍼 가장자리쪽으로 생성되도록 하는 단계와, 전체 구조 상부에 제 3 폴리실리콘막을 형성한 후 패터닝하여 비트라인을 형성하고, 이때 생성되는EBR 라인은 상기 제 2 콘택 홀을 형성할 때 생성되는 EBR 라인보다 웨이퍼 가장자리쪽으로 생성되도록 하는 단계와, 전체 구조 상부에 제 3 층간 절연막을 형성한 후 선택된 영역을 식각하여 제 3 콘택 홀을 형성하고, 이때 생성되는 EBR 라인은 상기 비트라인을 형성할 때의 EBR 라인보다 웨이퍼 가장자리쪽으로 생성되도록 하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention forms a first polysilicon layer and a mask oxide layer on a semiconductor substrate, and then patterns the word line pattern in a cell region and a peripheral circuit region. Spaced apart from the inside of the wafer by a predetermined interval, and depositing a nitride film over the entire structure, and performing an etching process so that only the nitride film in the peripheral circuit region is removed, wherein the generated EBR line is generated when the word line pattern is formed. Forming the first interlayer insulating film over the entire structure, followed by polishing by performing a first CMP process, and etching the first interlayer insulating film and the nitride film of the cell region. An EBR line is formed when the first contact hole is formed, and the EBR line is formed by etching the nitride layer. Forming a second polysilicon film over the entire structure such that the first contact hole is buried, and then performing a second CMP process to form the second polysilicon film and the first interlayer insulating film. Polishing to form a polysilicon plug, forming a second interlayer insulating film on the entire structure, and forming a second contact hole to expose the polysilicon plug of the cell region, wherein the generated EBR line is the first Forming the contact hole toward the edge of the wafer rather than the EBR line generated when forming the contact hole, forming a third polysilicon film on the entire structure, and then patterning the bit line to form a bit line, wherein the generated EBR line is the second contact Causing the edges to be formed toward the wafer edge rather than the EBR lines produced when forming the holes, and forming a third interlayer above the entire structure. And forming a third contact hole by etching the selected region after forming the insulating film, wherein the generated EBR line is formed toward the wafer edge rather than the EBR line when the bit line is formed. .
도 1(a) 및 도 1(b)는 종래의 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.
도 2(a) 내지 도 2(g)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.2 (a) to 2 (g) are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
A : 셀 영역 B : 주변 회로 영역A: cell area B: peripheral circuit area
C : EBR 영역C: EBR area
11 및 21 : 반도체 기판 12 및 22 : 제 1 폴리실리콘막11 and 21: semiconductor substrate 12 and 22: first polysilicon film
13 및 23 : 제 1 마스크막 14 및 24 : 질화막13 and 23: first mask film 14 and 24: nitride film
14A 및 24A : 질화막 스페이서 15 및 25 : 제 1 층간 절연막14A and 24A: nitride film spacers 15 and 25: first interlayer insulating film
16 및 26 : 제 1 콘택 홀 17 및 27 : 제 2 폴리실리콘막16 and 26: first contact hole 17 and 27: second polysilicon film
17A 및 27A : 폴리실리콘 플러그17A and 27A: Polysilicon Plugs
28 : 제 2 층간 절연막28: second interlayer insulating film
29 : 제 2 콘택 홀 30 : 제 3 폴리실리콘막29: second contact hole 30: third polysilicon film
31 : 제 2 마스크막 32 : 제 3 층간 절연막31 second mask layer 32 third interlayer insulating film
33 : 제 3 콘택 홀33: third contact hole
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 2(a) 내지 도 2(g)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.2 (a) to 2 (g) are cross-sectional views of devices for explaining the method for manufacturing a semiconductor device according to the present invention.
도 2(a)를 참조하면, 반도체 기판(21) 상부에 제 1 폴리실리콘막(22) 및 제 1 마스크막(23)을 형성한 후 워드라인 마스크를 이용한 리소그라피 공정 및 식각 공정을 실시하여 워드라인을 형성한다. 이때 생성되는 EBR 라인(L11)은 웨이퍼 가장자리로부터 웨이퍼 안쪽으로 5㎜ 떨어진 위치에 형성되도록 한다. 전체 구조 상부에 질화막(24)을 증착한 후 주변 회로 영역(B)의 질화막(24)만 제거되도록 식각 공정을 실시한다. 이에 의해 주변 회로 지역(B)의 워드라인 측벽에 질화막 스페이서(24A)가 형성된다. 질화막 제거시 생성되는 EBR 라인(L12)은 웨이퍼의 가장자리로부터 웨이퍼 안쪽으로 4.8 내지 5㎜ 떨어진 위치에 형성되도록 한다. 전체 구조 상부에 제 1 층간 절연막(25)을 형성한다. 이러한 구조에서 평탄화를 위해 제 1 층간 절연막(25)을 연마할 때 EBR 영역(C)에 가해지는 압력(Ep)이 셀에 가해지는 압력(Cp)보다 크게 작용한다.Referring to FIG. 2A, after forming the first polysilicon layer 22 and the first mask layer 23 on the semiconductor substrate 21, a lithography process and an etching process using a word line mask are performed. Form a line. The generated EBR line L11 is formed at a position 5 mm away from the wafer edge into the wafer. After the nitride film 24 is deposited on the entire structure, an etching process is performed such that only the nitride film 24 in the peripheral circuit region B is removed. As a result, a nitride film spacer 24A is formed on the word line sidewalls of the peripheral circuit region B. FIG. The EBR line L12 generated when the nitride film is removed is formed at a position 4.8 to 5 mm away from the edge of the wafer into the wafer. The first interlayer insulating film 25 is formed over the entire structure. In this structure, when polishing the first interlayer insulating film 25 for planarization, the pressure Ep applied to the EBR region C is greater than the pressure Cp applied to the cell.
도 2(b)는 제 1 층간 절연막(25)을 CMP 공정으로 연마한 후의 단면도이다. 연마 공정을 실시한 후 셀 영역(A)의 제 1 층간 절연막(25)의 두께(t11)에 비해 EBR 영역(C)의 제 1 층간 절연막(25)의 두께(t12)가 얇게 형성된다.2B is a cross-sectional view after polishing the first interlayer insulating film 25 by the CMP process. After the polishing process, the thickness t12 of the first interlayer insulating layer 25 of the EBR region C is thinner than the thickness t11 of the first interlayer insulating layer 25 of the cell region A.
도 2(c)는 폴리실리콘 플러그를 형성하기 위해 셀 영역(A)의 제 1 층간 절연막(25) 및 질화막(24)을 식각하여 제 1 콘택 홀(26)을 형성한 상태의 단면도이다. 이때 생성되는 EBR 라인(L13)은 웨이퍼 가장자리로부터 웨이퍼 안쪽으로 4.5 내지 4.8㎜ 떨어진 위치에 형성되도록 한다.2C is a cross-sectional view of a first contact hole 26 formed by etching the first interlayer insulating film 25 and the nitride film 24 in the cell region A to form a polysilicon plug. The generated EBR line L13 is formed at a position 4.5 to 4.8 mm away from the wafer edge into the wafer.
도 2(d)는 제 1 콘택 홀(26)이 매립되도록 전체 구조 상부에 제 2 폴리실리콘막(27)을 형성한 후 CMP 공정을 실시하여 제 2 폴리실리콘막(27) 및 제 1 층간 절연막(25)을 연마하여 폴리실리콘 플러그(27A)를 형성한 상태의 단면도이다. EBR 영역(C)의 2차 CMP 공정에 의해 형성된 제 1 층간 절연막(25)의 두께(t14)는 셀 영역(A)의 2차 CMP 공정에 의해 형성된 제 1 층간 절연막(25)의 두께(t13)보다 얇게 형성되기는 하지만 일정한 두께로 잔류하게 된다.FIG. 2 (d) shows that the second polysilicon film 27 and the first interlayer insulating film are formed by forming a second polysilicon film 27 on the entire structure to fill the first contact hole 26 and then performing a CMP process. (25) is sectional drawing in the state which grind | polished and the polysilicon plug 27A was formed. The thickness t14 of the first interlayer insulating film 25 formed by the secondary CMP process of the EBR region C is the thickness t13 of the first interlayer insulating film 25 formed by the secondary CMP process of the cell region A. It is thinner than) but remains in a certain thickness.
도 2(e)는 전체 구조 상부에 제 2 층간 절연막(28)을 형성한 후 셀 영역(A)의 폴리실리콘 플러그(27B)가 노출되도록 제 2 콘택 홀(29)을 형성한 상태의 단면도이다. 이때 생성되는 EBR 라인(L14)은 웨이퍼 가장자리로부터 4.3 내지 4.5㎜ 웨이퍼 안쪽으로 생성되도록 한다.FIG. 2E is a cross-sectional view of the second contact hole 29 formed to expose the polysilicon plug 27B in the cell region A after forming the second interlayer insulating film 28 over the entire structure. . EBR line (L14) generated at this time is to be generated inside the wafer 4.3 to 4.5mm from the wafer edge.
도 2(f)는 전체 구조 상부에 비트라인용 제 3 폴리실리콘막(30) 및 제 2 마스크막(31)을 형성한 후 패터닝하여 비트라인을 형성한 상태의 단면도이다. 이때형성되는 EBR 라인(L15)은 웨이퍼의 가장자리로부터 4 내지 4.3㎜ 웨이퍼 안쪽으로 형성되도록 한다. 이와 같은 상황에서 폴리실리콘 식각 공정을 진행할 경우 이전까지 EBR 영역(C)에 잔류하던 제 2 폴리실리콘막(27)의 일부가 제거된다.FIG. 2F is a cross-sectional view of a bit line formed by forming a third polysilicon layer 30 and a second mask layer 31 for a bit line on the entire structure and then patterning the bit line. EBR line (L15) formed at this time is to be formed into the wafer 4 ~ 4.3mm from the edge of the wafer. In this situation, when the polysilicon etching process is performed, a part of the second polysilicon layer 27 remaining in the EBR region C is removed.
도 2(g)는 전체 구조 상부에 제 3 층간 절연막(32)을 형성한 후 선택된 영역을 식각하여 제 3 콘택 홀(33)을 형성한 상태의 단면도이다. 이때 생성되는 EBR 라인(L16)은 웨이퍼 가장자리로부터 3.5 내지 4㎜ 웨이퍼 안쪽으로 형성되도록 한다.FIG. 2G is a cross-sectional view of the third contact hole 33 formed by etching the selected region after forming the third interlayer insulating layer 32 over the entire structure. At this time, the generated EBR line L16 is to be formed into the 3.5 to 4mm wafer from the wafer edge.
상술한 바와 같이 본 발명에 의하면 셀 영역 및 주변 회로 영역에 반도체 소자를 제조하기 위한 공정을 실시할 때 EBR 영역의 라인 폭을 조절하므로써 CMP 공정시 EBR 영역에서 하부 패턴이 노출되는 것을 방지할 수 있어 소자의 결함을 방지할 수 있다.As described above, according to the present invention, when the process for manufacturing a semiconductor device is performed in the cell region and the peripheral circuit region, the lower pattern is prevented from being exposed in the EBR region during the CMP process by adjusting the line width of the EBR region. Defects of the device can be prevented.
Claims (8)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5314843A (en) * | 1992-03-27 | 1994-05-24 | Micron Technology, Inc. | Integrated circuit polishing method |
| KR980005761A (en) * | 1996-06-29 | 1998-03-30 | 김주용 | Method of manufacturing semiconductor device |
| JPH10189509A (en) * | 1996-12-26 | 1998-07-21 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| KR19980065713A (en) * | 1997-01-14 | 1998-10-15 | 김광호 | Method for manufacturing semiconductor device with improved step |
| JPH11297695A (en) * | 1998-04-08 | 1999-10-29 | Nec Corp | Method and apparatus for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5314843A (en) * | 1992-03-27 | 1994-05-24 | Micron Technology, Inc. | Integrated circuit polishing method |
| KR980005761A (en) * | 1996-06-29 | 1998-03-30 | 김주용 | Method of manufacturing semiconductor device |
| JPH10189509A (en) * | 1996-12-26 | 1998-07-21 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| KR19980065713A (en) * | 1997-01-14 | 1998-10-15 | 김광호 | Method for manufacturing semiconductor device with improved step |
| JPH11297695A (en) * | 1998-04-08 | 1999-10-29 | Nec Corp | Method and apparatus for manufacturing semiconductor device |
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