KR19980046872U - Interface circuit between central processing unit and system bus - Google Patents

Abstract

The present invention relates to an interface circuit of a CPU and a system bus that improves the performance of peripheral devices by adjusting the clock speed in the middle so that the CPU can control peripheral devices that operate relatively slow compared to the clock frequency of the CPU.

In the circuit of the present invention, an interface circuit between a CPU and a system bus includes clock generation means for generating a constant clock signal to operate a CPU that controls the entire system, and is connected between the CPU and the clock generation means to provide a CPU and peripheral devices. Clock control means for regenerating and supplying a clock suitable for the current system situation to control, and a system bus for transmitting the control signal and the variable clock signal from the CPU to the peripheral device and the memory device.

According to the present invention, it is possible to improve the performance of the peripheral device of the computer system, and to implement the interface part connecting each peripheral device and the bus simply and easily according to the unified standard.

Description

Interface circuit between central processing unit and system bus

1 is a block diagram schematically illustrating a conventional manner in which a CPU interfaces to control peripherals connected to a computer through a system bus.

Figure 2 is a block diagram schematically showing the configuration of the interface method according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: CPU12: system bus

14: peripheral device 16: memory

20: clock generator 22: CPU interface unit

24: clock register 26: clock divider circuit

The present invention relates to an interface between a central processing unit (CPU) and a system bus of a computer system, and in particular, by adjusting the clock speed in the middle so that the CPU can control peripheral devices that operate relatively slow compared to the clock frequency of the CPU. It is about the interface circuit of the CPU and the system bus to improve their performance.

In recent years, with the diversification of the functions of the personal computer, the use of a personal computer in which a so-called multimedia system in which various peripheral devices and the like are connected is widely used.

Figure 1 schematically illustrates a conventional manner in which the CPU interfaces to control peripherals connected to a computer via a system bus. The interface scheme of FIG. 1 includes a CPU 10 for controlling the operation of the entire system, a system bus 12 for transmitting control signals from the CPU 10, and a peripheral device 14 connected to the system bus 12. ) And the memory device 16. In the conventional interface system having such a configuration, the clock entering the CPU 10 has always been constant. That is, the frequencies of the clock signals CLK1 and CLK2 as shown in FIG. 1 were always constant. For example, in ARM7 / OA, the CPU has two clock sources, FCLK and MCLK, but they always operate at a constant frequency.

In such a conventional interface method, it is difficult to interface a computer with a peripheral device having a slow operation speed. In addition, even when a relatively fast peripheral speed is connected, the peripheral device performance is not improved as the peripheral speed increases.

The conventional method proposed to solve this problem generally provides a wait signal to the CPU when the CPU attempts to access peripheral devices so that the CPU cannot proceed to the next cycle while the signal is coming in. . As described above, as the frequency used increases, it becomes more difficult to match the time when the standby signal comes in, that is, when the standby command is given, and the controllers of the respective devices must provide the standby signal toward the bus. Have Therefore, this conventional method has not been very useful in the embedded microcomputer field because it is necessary to reduce the number of logics as much as possible.

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the performance of peripheral devices by adjusting the clock speed so that the CPU can control peripheral devices that operate relatively slower than the CPU clock frequency. And to provide the interface circuitry for the system bus.

Another object of the present invention is to provide an interface circuit that enables simple and easy implementation of the interface portion connecting each device and buses of a computer system to a unified standard.

In order to achieve these objects, the interface circuit between the CPU and the system bus according to the present invention comprises a clock generating means for generating a constant clock signal to operate a CPU that controls the entire system, and between the CPU and the clock generating means. Clock control means for regenerating and supplying a clock suitable for the current system situation so as to control the CPU and peripheral devices, and a system bus for transmitting control signals and variable clock signals from the CPU to peripheral devices and memory devices. do.

The above and other objects and advantages of the present invention will become more apparent from the detailed description of the embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIG. 2.

2 is a block diagram schematically showing the configuration of the interface method according to the present invention. The interface method of FIG. 2 is suitable for the current system situation to control the clock generator 20 and the CPU 10 and the peripheral device 14 to generate a constant clock to operate the CPU 10 for controlling the entire system. A CPU interface unit 22 for regenerating and supplying a clock and a system bus 12 for transmitting a control signal and a variable clock signal from the CPU 100 to the peripheral device 14 and the memory device 16 are provided. The CPU interface unit 22 includes a clock divider circuit 26 for dividing a clock signal of a constant frequency from the clock generator 20 and a clock register 24 for adjusting a clock speed.

The principle of the interface system between the CPU and the system bus configured as described above is to change the clock frequency by lowering the clock frequency by the CPU interface 22 when the clock is to be changed to access the relatively slow peripheral devices. Is to adjust the clock speed according to the situation so that the CPU 10 can control the peripheral devices by increasing the clock frequency.

Now, the operation of the interface circuit configuration according to the present invention will be described in detail. In FIG. 2, the CPU interface 22 receives a clock signal of a constant frequency generated by one clock generator 20, regenerates a clock suitable for the current situation, and generates the adjusted clock to the CPU 10. And the control unit of the peripheral device 14.

At this time, the role of regenerating the clock is as follows. First of all, the CPU 10 accesses the memory 16 which is usually composed of a ROM to obtain an instruction. Then, the CPU 10 analyzes and executes the instruction code, and initializes the clock register 24 in the CPU interface unit 22 at this time. The clock speed is then adjusted by the clock divider 26 and clock register 24. This register 24 is composed of 32 bits, and 2 bits are allocated to each device so that the clock speed can be adjusted for a total of 16 devices. Although the definition of the clock speed is different depending on which clock source is used, in this embodiment, it is assumed that a clock generator of 40 MHz is used, and is defined as follows.

00: 8min [5MHz]

01: 4 divisions [10MHz]

10: 2 min [20 MHz]

11: just use [40MHz]

With the value of register 24 defined as above, CPU 10 accesses either peripheral 14. This access process is described in detail as follows.

First, in the first step, the CPU 10 transmits signals necessary for accessing a peripheral device such as an address, data, read / write signal, etc. to the CPU interface 22.

In the second step, the CPU interface unit 22 then checks the address according to the address signal to determine which device to select, and activates one of the select [15: φ] signals, for example.

In a third step, the clock register 24 is accessed with the signal activated in the above step to find out the clock frequency needed by the selected device.

In the fourth step, a clock is generated based on the frequency value found in the previous step and inserted into the bus 12 side and the CPU 10 side, and at the same time, the address, data and lead are synchronized to the bus 12 side. Creates signals such as lights.

In a fifth step, when all accesses to the device are completed, the clock is restored to its original state so that the CPU 10 does not take time to perform internal operations.

On the other hand, when the CPU 10 wants to access another device, the steps from the first step to the fifth step may be repeated.

When the above-described interface method is used, the interface part connecting each peripheral device and the bus can be simply and easily implemented in accordance with a unified standard. Of course, in some cases it may be necessary to set a register value that determines the clock frequency, but in this case it is easy to determine the minimum time required to access each device in advance.

As described above, according to the present invention, the performance of peripheral devices can be improved by adjusting the clock speed so that the CPU can control peripheral devices that operate relatively slow compared to the CPU clock frequency.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the utility model registration claims.

Claims (3)

Clock generation means for generating a constant clock signal to operate a CPU that controls the entire system; Clock adjusting means connected between the CPU and the clock generating means for regenerating and supplying a clock suitable for the current system situation to control the CPU and peripherals; And a system bus for transmitting a control signal and a variable clock signal from the CPU to peripherals and a memory device. The method of claim 1, The clock adjusting means includes a clock dividing circuit for dividing a clock signal of a constant frequency from the clock generating means, and a clock register for adjusting a clock speed, wherein the interface circuit between the central processing unit and the system bus is provided. . The method of claim 2, Wherein the clock register is configured with 32 bits to adjust clock speeds for a total of 16 devices, and 2 bits are allocated to each of the devices.