JPH10133766A - Adaptive power-down clock control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption in a peripheral equipment added to a host processor by generating a control signal in response to a data transferring request from the host processor, and changing the frequency of a clock. SOLUTION: A clock signal to be controlled is operated with a relatively low frequency in a power saving mode from a time T0 to a time T2 at first. In this period, an IO CHRDY signal is asserted, and a voltage on a signal line 404 is turned into a high level. At the time T1 , a host processor issues a reading request and turns a voltage on a control line 403 into a low level. At the time T2 , a voltage on a signal line 413 is turned into a low level, and the frequency of a clock to be controlled is increased to a higher level by a frequency-divider 407 to be controlled. This is equal to the frequency of a system clock on a signal line 406. An MODEM executes a normal function with the higher frequency of the clock to be controlled, and interface with a bus 402 is executed at a normal speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing power consumption in a device added for communicating with a host processor via a bus.

[0002]

BACKGROUND OF THE INVENTION The reduction in power consumption of integrated circuits (ICs) is important in many system designs, especially when battery life and / or heat dissipation is a concern. It is a problem. In some cases, power saving modes are implemented that turn off various parts of the IC when power is not needed. For example, U.S. Pat. No. 5,423,047, entitled "Method and Apparatus for Reducing Power Consumption Using Address Transition Detection (Metho)
dsand Apparatus for Using
Address Transition Decec
Tion to Reduce Power Cons
"umption" describes how to switch from a low power mode to a normal function for one memory block using an external event (eg, an address transition). In the low power mode, a part of the circuit is deactivated until the next event (for example, address transition) is detected.

[0003] CMOS (Complementary Metal Oxide Semiconductor) IC
It is well known that the major part of the power consumption is proportional to the switching frequency of the circuits on the IC. The internal frequency of the circuit is usually derived from the system clock. Adjustment of the system frequency is usually performed under the control of an on-chip microcontroller, and its function is part of the microcontroller software. Therefore, C
One technique for powering down a MOS integrated circuit, or a portion thereof, is to use software control to reduce the frequency of the system clock when the system design permits in the process flow. For example, US Patent No. 5,428,790 entitled "Computer Power Management System"
er Management System) describes a power management system under software control that turns off or reduces the frequency of clock signals supplied to various parts of a computer. Frequency dividers are often employed to reduce the system clock frequency. However, the system
Decreasing the frequency of the clock slows down all synchronous operations within the integrated circuit. Furthermore, the I
C often must interface with a peripheral bus operating at a fixed fixed frequency, such as an ISA or PCMCIA bus. Therefore, it is not desirable to reduce the clock frequency, at least for those parts of the circuit that interface directly with such a bus. Also, using software control is often too slow and impractical to save power in many cases.

An example of a peripheral device communicating with a host personal computer on a bus is described below. FIG.
Referring to FIG. 1, a typical prior art modem 100 is IS
A (Industry Standard Archi)
(Industrial Standard Architecture) Bus 10
2 interfaces with the host processor 101 of the personal computer. The modem in this illustrative example includes an interface circuit 105, a controlled frequency divider 107, and an arbiter 108, and a microcontroller 109. Further, the I / O register 112 and the mixed type memory 111 communicate with the arbiter 108 via the bus 110. This modem operates under the control of a system clock 106. Referring to FIG. 2, the host processor issues a read request (HOST READ_N) on signal line 103 to read I / O register space 112 or external mixed memory 111. Such operations include arbitration by the arbiter 108 between the interface circuit 105 and the microcontroller 109. It may also request access to the bus. Next, the operation proceeds by accessing the external memory 111 or the I / O register 112 and returning the data to the bus 102.

However, if the modem is unable to respond immediately to the host over bus 102, then the modem will respond to signal line 1 as described in more detail in FIG.
Withholding access to the host by asserting the signal IO CHRDY low at 04. When the transfer of data (read or write) can be completed, the IO CHRDY signal is deasserted by its peripheral (ie, signal line 104 goes high). This peripheral action causes the host to deassert the READ_N signal (or WRITE_N, not shown) on signal line 103. I / O
A similar situation occurs when two consecutive writes to a register or external memory are attempted, and the first write is not completed when the second write is initiated by the host PC. Can occur.

[0006]

SUMMARY OF THE INVENTION The present invention is directed to techniques for reducing power consumption in peripheral devices that are added to interface with a host processor by a bus. The peripheral operates in a power saving mode at a relatively low clock frequency or in an operating mode at a relatively high clock frequency. The peripheral device includes a clock control circuit that generates a control signal in response to a data transfer request from a host processor, thereby increasing a clock frequency. The control signal is a type of signal that indicates whether the peripheral device is ready to perform the data transfer requested by the host processor. In the description example of the ISA bus, this control signal is “IO CHRDY (Input
"Output Channel Ready" (input / output channel ready) signal.

[0007]

DETAILED DESCRIPTION The following detailed description relates to techniques for reducing power consumption in devices that are added to communicate with a host processor over a bus. The host processor is typically a microprocessor in a personal computer or portable communication device, but other types of host processors are possible. Referring to FIG. 3, a timing diagram of an exemplary embodiment of the present invention is shown, and FIG. 4 is a block diagram of a circuit embodying the present invention. FIG. 4 is similar to FIG. However, IO CHRD
An additional control signal line 413 is included between the Y signal line 404 and the controlled frequency divider 407. In the present technique, the operating frequency of the peripheral device (ie, the modem in the exemplary embodiment) is reduced to conserve power. The frequency setting for the power saving mode is typically controlled by software for the microcontroller 409. The host processor issues a read or write data transfer request to the modem, and the operating frequency of the modem is raised to an appropriate operating level to service the data transfer request.
In most cases, this is the maximum frequency available for the modem. For example, the frequency of the system clock (SYSTEM CLOCK) on the signal line 406. The function of the additional control signal lines for achieving this purpose is described below.

Referring to FIG. 3, the controlled clock signal (on line 414 in FIG. 4) is initially at a relatively low frequency during a power saving mode of time from T ₀ to T _2. Operate. Note that this includes the possibility of stopping the controlled clock signal altogether, in which case the frequency is zero. During this period, IO CHR
The DY signal is asserted, causing the voltage V1 on the signal line 404 to go high. At time T _1, the host processor issues a read request (HOST READ_N), the voltage V ₂ on the control signal line 403 is set to be low. In response to this change on the control signal line 403, the interface circuit 405 causes the IO CHRDY signal line to be deasserted and the IO CHRDY on the signal line 404,
Therefore, the voltage V ₁ on the signal line 413 is set to be low at the time T ₂ . This indicates to the host processor that the modem is not ready to respond immediately to access requests from the host processor. The low voltage on the control signal line 413 causes the controlled frequency divider 407 to increase the frequency of the controlled clock to a higher level. This is usually the signal line 406
Equal to the frequency of the above system clock. The higher frequency of the controlled clock causes the modem to perform normal functions and interface with bus 402 at normal operating speeds. For example, in the case of an ISA bus, the clock speed of the bus is 8 MHz. At the operating system clock frequency, the modem can provide the requested data to the host processor and perform other necessary functions.

At time T ₃ , interface circuit 405 returns voltage V 1 on line 404 of signal line IO CHRDY to a high voltage state so that the requested data has been provided during the read operation, or Instead, it informs the host processor that the write operation has been completed. This high voltage state is also supplied to the control signal line 413 and the controlled frequency divider 40
7 serves to reduce the frequency of the controlled clock on line 414 to a lower frequency state specified by software, as shown in FIG. Furthermore, I
In response to the O CHRDY signal line going high,
The host processor completes its read request by returning the voltage V ₂ on the signal line 403 to a high state.

Referring to FIG. 5, a block diagram of a portion of the circuitry within controlled frequency divider 407 is shown. While this circuit provides one convenient way to change the controlled clock from a lower frequency state in the power saving mode to a higher frequency state in the operating mode, various other methods are possible. In particular, multiplexer 501 selects signal line 502 by selecting either the system clock (input 0 from signal line 504) or a lower frequency from programmable divider 506 (input 1 from signal line 505). Provide the above controlled clock (connected to signal line 414 in FIG. 4). The multiplexer 501 is preferably of the "glitch-free" type so that the waveform of the clock signal does not become discontinuous when switching from one input to another. Various designs for glitch-free multiplexers are well known in the art. further,
Multiplexer 501 is connected to IO CHR on signal line 503.
Controlled by the DY signal, it performs the functions described above in connection with FIGS. The low frequency clock is divided by a programmable frequency divider
7 derived from the system clock. The frequency division ratio of the clock is set by the contents of the register 508. It is usually controlled by software, but may be fixedly programmed if necessary.

The above embodiment has shown that the clock speed of the modem can be increased in order for the modem to perform data transfers to and from the host processor. However, the clock speed can be increased for other purposes than during the "operation mode", as normally controlled by the modem's microcontroller. Although the above exemplary embodiment has been provided for a modem connected to a PC host by an ISA bus,
Many other applications are possible. For example, the techniques of the present invention can be used with various other peripheral devices, including digital communication devices (eg, ISDN adapters), network communication devices (eg, Ethernet adapters), video display devices, and the like. Other bus types can also be used to advantage. For example, the PCI bus is TRDY # (t
arget ready). This can be used to control the clock frequency instead of the IO CHRDY signal used on the ISA bus. As another example, the PCMCIA bus (also called the PC Card bus) uses a WAIT # signal, which can be employed in a similar manner for use in the techniques of the present invention. That is, each of these signals indicates to the host processor whether its peripheral is ready to supply the requested data. Therefore, these signals are also commonly referred to herein as "ready" signals. In some cases,
The bus operates at the clock frequency defined by the standard. In addition, two or more bus frequencies may be selected from a plurality of frequencies, and the selection depends on the system design. Still other types of buses and applications are possible.

[Brief description of the drawings]

FIG. 1 illustrates an example of a prior art peripheral that interfaces with a computer via a bus.

FIG. 2 shows prior art control and data signals used with the example apparatus of FIG. 1;

FIG. 3 illustrates examples of clock and control signals used in an apparatus implementing the techniques of the present invention.

FIG. 4 illustrates one embodiment of the technique of the present invention.

FIG. 5 illustrates a control circuit that can be used in implementing the techniques of the present invention.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Vladimir Sinardovsky United States 18944 Pennsylvania, Parkasi, Highland Drive 602

Claims (7)

[Claims] A peripheral device (400) operating at a device clock frequency and capable of communicating with a host processor (401) by means of a bus (402).
And the peripheral device outputs a ready signal (IO CHRD).
Y) to the host processor by means of the bus to indicate whether the peripheral device is ready to transfer the data requested by the host processor; Changing the clock frequency of the device in response to the clock frequency of the device to a relatively high value during the operation mode and the clock frequency of the device to a relatively low value during the power saving mode. Peripheral device, characterized in that it comprises means (413) for providing 2. The bus according to claim 1, wherein said bus is an industry standard architecture (I).
ndustry Standard Architec
2. The invention according to claim 1, wherein the bus is a true (ISA) bus. 3. The invention according to claim 1, wherein said bus is a PCMCIA bus. 4. The invention according to claim 1, wherein said bus is a PC card bus. 5. The bus according to claim 1, wherein said bus is a Peripheral Component Interconnect (Peripheral Component Interconnect).
components interconnect (PCI)
2. The invention according to claim 1, wherein the invention is a bus. 6. The invention according to claim 1, wherein said peripheral device is a modem. 7. The invention of claim 1, wherein said peripheral device includes at least one integrated circuit including a CMOS transistor.