KR19980026518A - Low Decoder in Nonvolatile Semiconductor Memory Devices - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a row decoder of a nonvolatile semiconductor memory device for selecting word lines of a memory cell array and driving the same to a voltage required for each operation mode. According to this apparatus, in order to prevent the GIBV of the transfer transistor of the row decoder from lowering, a predetermined voltage level is applied to the gate of the transfer transistor corresponding to the unselected external address by using precharge means. As a result, the GIBV of the transfer transistor corresponding to the unselected external address can be increased. Thus, by applying the voltage of 0 volts to the gate of the transfer transistor corresponding to the non-selected external address as in the prior art at a predetermined voltage level through the precharge means, the program voltage is sufficiently worded through the transfer transistor corresponding to the selected external address. You can now pass on the line. Therefore, not only can the program speed be increased, but the program yield can be prevented from being lowered.

Description

Row decoder in a nonvolatile semiconductor memory device. (row decoder of non volatile semicondcutor memory device)

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a row decoder of a nonvolatile semiconductor memory device for selecting word lines of a memory cell array and driving the same to a voltage required for each operation mode.

A NAND flash memory device or an electrically erasable programmable read only memory (EEPROM) is composed of a plurality of NAND cell units composed of a plurality of memory cells. Each of the memory cells has a structure in which a source and a drain are formed between channels, and a gate oxide film, a floating gate, an ONO film, and a control gate are sequentially formed on the channel. Each word line is connected to a control gate of each memory cell of each NAND cell unit. Each memory cell is programmed using F-N tunneling, in which electrons move from the channel region to the floating gate through the gate oxide layer. At this time, in order to program the memory cells, a high voltage is applied to a control gate of the memory cells and applied to a selected word line. There is a need for a row decoder capable of writing or erasing data by maintaining the high voltage at a constant reference value and transferring it only to the required word lines.

1 is a circuit diagram illustrating a circuit of a row decoder of a conventional nonvolatile semiconductor memory device.

Referring to FIG. 1, the memory cell array 10 includes a plurality of NAND cell units CU, each NAND cell unit CU having a floating gate and a control gate. It consists of a number of memory cells. The control gates of the memory cells of the NAND cell units CU are commonly connected to corresponding word lines W / Lk to W / Ln (where k and n are positive integers). Each word line W / Lk to W / Ln of the memory cell array 10 is selected by the row decoder 20 and receives the word line voltage required in each operation mode from the row decoder 20. The row decoder 20 includes row decoder blocks 22k to 22n corresponding to each word line W / Lk to W / Ln of the memory cell array 10. Each row decoder block 22k-22n includes a NAND gate G1, depletion MOS transistors D1 and D2, a switch pump 11, and a transfer transistor T1. Address k_address, clock signal 1o, and control signal Transfers a high voltage (VSi + Vth, where VSi represents an external high voltage applied from the outside during a program or read operation, and Vth represents a threshold voltage of the transfer transistor T1) to the gate of the transfer transistor T1. do.

That is, the selected external address is applied at a high level, the unselected external address is applied at a low level, and the clock signal 1o is applied as a square wave having a predetermined frequency. The NAND gate G1 is enabled only when an external address is selected to transfer the clock signal 1o to the switch pump 11 to operate the switch pump 11 to operate the high voltage VSi +. Vth) is output and the high voltage VSi + Vth is applied to the gate of the transfer transistor T1. Accordingly, the high voltage VSi (high voltage for performing a program or read operation) applied from the outside through the transfer transistor T1 is transferred to the word line corresponding to the selected external address.

Hereinafter, an operation will be described with reference to FIG. 1 according to a reference row decoder according to a conventional row decoder.

Among the external addresses (k_address-n_address) input to the row decoder 20 during the program operation or the read operation, the selected external address is applied at the high level, and the unselected external address is applied at the low level, respectively, and the clock signal 1o is applied. It is applied as a square wave having a predetermined frequency. The NAND gate G1 which receives an external address k_address selected from the outside and a clock signal 1o having a predetermined frequency is enabled by the signals k_address '1o' to switch the clock signal 1o. It is delivered to the pump (11). Accordingly, the switch pump 11 performs a voltage pumping operation by the clock signal 1o to generate a high voltage (VSi + Vth), and the high voltage (VSi + Vth) generated from the switch pump 11 is a conductive path. Is passed to L1. As a result, the transfer transistor T1 having the gate connected to the conductive path L1 is turned on and the high voltage having the external voltage VSi applied to the drain of the transfer transistor T1 is a word line corresponding to the selected external address k_address. (W / Lk).

On the other hand, when the external address applied from the outside is unselected, the control signal applied from the outside ( ), Both the depletion MOS transistor D1 having a gate connected to the control terminal 3 to which the gate is applied and the depletion MOS transistor D2 having its gate connected to the power terminal 5 to which the power supply voltage Vss is applied are turned on. A low level unselected external address n_address is transferred to the conductive path L1. Accordingly, the transfer transistor T1 having a gate connected to the conductive path L1 is turned off to a word line W / Ln corresponding to an external address n_address in which a high voltage VSi applied from the outside is unselected. It will block delivery.

However, according to the row decoder as described above, a high voltage (external high voltage Vsi applied from the outside + threshold voltage Vth of the transfer transistor) is applied to the gate of the transfer transistor corresponding to the selected external address during the program operation. 0 volts is applied to the gate of the transfer transistor corresponding to the selected external address. The gate induced breakdown voltage (GIBV) of a MOS transistor has a lower GIBV when zero volts is applied to its gate and lowers the voltage level that can be delivered through the transistor. That is, since 0 volt is applied to the gate of the transfer transistor corresponding to the unselected external address, the GIBV value of the transistor is lowered. Thus, when a high voltage VSi above the GIBV value of the transfer transistor is caught in its drain, current leakage occurs due to the down GIBV value.

Therefore, even if the external high voltage VSi is applied high, the program voltage applied to the word line of the cell cannot rise above the GIBV value of the transfer transistor corresponding to the unselected external address. As a result, the high voltage VSi required for the word line corresponding to the selected external address during the program operation is limited to the down GIBV value, thereby applying a high voltage to the word line. Therefore, since the external high voltage (VSi) (program voltage) required for the program operation is limited to the down GIBV value, the cell program time is lengthened due to insufficient transfer to the word line. In addition, when the memory cell is not programmed by the down GIBV, a yield may be reduced.

Accordingly, an object of the present invention is to provide a row decoder of a nonvolatile semiconductor memory device for improving the GIBV value of a transfer transistor that transfers a high voltage to a word line, which has been proposed to solve the aforementioned problems.

1 is a circuit diagram showing a circuit of a row decoder of a conventional nonvolatile semiconductor memory device;

2 is a circuit diagram showing a circuit of a row decoder of a nonvolatile semiconductor memory device according to a first preferred embodiment of the present invention;

3 is a circuit diagram showing a circuit of a row decoder of a nonvolatile semiconductor memory device according to a second preferred embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

10: memory cell array 22k-20n, 32k-32n, 42k-42n: row decoder block

11: switching pump

According to one aspect of the present invention for achieving the object as described above, the control gate and the control gate and the gate of the control cell of the memory cells of each NAND cell unit comprising a plurality of memory cells having a floating gate Selects a memory cell array and each word line of the memory cell array that are commonly connected to the corresponding word lines, and transfers a predetermined voltage required in each operation mode to the selected word lines, and corresponds to each word line. A row decoder of a nonvolatile semiconductor memory device having four row decoder blocks, each row decoder block comprising: a conductive path charged with a predetermined voltage; A clock signal having an external address applied from the outside and a clock signal having a predetermined frequency is input, and outputs the clock signal in response to the external address of the first level and the clock signal in response to the external address of the second level. Input means for blocking the output; A switch pump receiving the clock signal output from the input means and performing a voltage boosting operation to output a predetermined high voltage through the conductive path, but not operating when the clock signal is not output from the input means; The conductive path receives the first control signal and the second control signal applied from the external address and externally, and before the selected or unselected external address is input when a high voltage is required for a predetermined word line of the memory cell array. Precharge means for precharging to a predetermined voltage level; When the external address selected as the input means is input, the high voltage transmitted from the switch pump to the conductive path is received, and in response thereto, the external voltage applied from the outside is transferred to the corresponding word line, and the non-transmitted voltage is input to the input means. And a transmission means for receiving the predetermined voltage level charged in the conductive path when the selected external address is input and blocking the external voltage from being transmitted to the word line in response thereto.

In a preferred embodiment of the apparatus, the precharge means has a source-drain between a node 1 and a first input terminal to which a gate is connected to a first control terminal to which the first control signal is applied, and to which the external address is applied. A first transistor connected with a channel; A second transistor having a gate connected to a second power terminal to which a power voltage is applied from the outside, and a source-drain channel connected between the node 1 and the conductive path; And a third transistor having a gate connected to the second control terminal to which the second control signal is applied, and a source-drain channel connected between the second power terminal and the conductive path.

In a preferred embodiment of the device, the first transistor and the third transistor are provided with an MOS transistor of an n-channel conductivity type.

In a preferred embodiment of the device, the second transistor is characterized by being a depletion type MOS transistor.

According to another feature of the present invention, a NAND cell unit including a plurality of memory cells having a control gate and a floating gate is provided, and the control gates of the memory cells of each NAND cell unit are common to the corresponding word lines. A nonvolatile device having a plurality of row decoder blocks corresponding to each word line, selecting a memory cell array connected to each other and each word line of the memory cell array and transferring a predetermined voltage required in each operation mode to the selected word line A row decoder of a semiconductor memory device, each row decoder block comprising: a first input terminal to which an external address is input from an external device; A second input terminal to which a clock signal having a predetermined frequency is input from the outside; A first control terminal to which a first control signal is applied from the outside; A first power supply terminal receiving an external voltage applied to the word lines in each operation mode; A second power supply terminal to which a power supply voltage is applied from the outside; A second control terminal to which a second control signal is applied from the outside; A conductive path charged with a predetermined voltage; A NAND gate connected to each of the first input terminal and the second input terminal; A switch pump connected between the output terminal of the NAND gate and the conductive path; An NMOS transistor having a source-drain channel connected between the first input terminal and node 1 and a gate connected to the first control terminal; A depletion MOS transistor having a source-drain channel connected between the node 1 and the conductive path and a gate connected to the second power terminal; An NMOS transistor having a source-drain channel connected between the second power terminal and the conductive path and a gate connected to the second control terminal; The NMOS transistor includes a source-drain channel connected between the first power terminal and a word line of the memory cell array.

According to another feature of the present invention, a NAND cell unit including a plurality of memory cells having a control gate and a floating gate is provided, and the control gates of the memory cells of each NAND cell unit are corresponding to each word line. Selects a memory cell array and a word line of the memory cell array that are connected in common, transfers a predetermined voltage required in each operation mode to the selected word line, and includes a plurality of row decoder blocks corresponding to each word line. A row decoder of a volatile semiconductor memory device, each row decoder block comprising: a first conductive path charged with a predetermined voltage; A second conductive path charged with a predetermined voltage; A clock signal having an external address applied from the outside and a clock signal having a predetermined frequency is input, and outputs the clock signal in response to the external address of the first level and the clock signal in response to the external address of the second level. Input means for blocking the output; Receiving the clock signal output from the input means in response to the voltage boosting operation to output a predetermined high voltage to the first conductive path, the switch pump does not operate when the clock signal is not output from the input means Wow; In response to the external address, the first control signal, the second control signal, and the third control signal applied from the outside, when a high voltage is required for a predetermined word line of the memory cell array, a selected or unselected external address is input. Precharge means for precharging the second conductive path to a predetermined voltage level before being input; When the external address selected by the input means is input, the high voltage transferred from the switch pump to the conductive path and the predetermined voltage level charged in the second conductive path are received, and in response thereto, the word corresponding to the external voltage is received. When a non-selected external address is input to the input means, a second level voltage and a predetermined voltage level charged in the second conductive path are respectively received from the conductive path. And transmission means for blocking delivery to the line.

In a preferred embodiment of the apparatus, the procharge means is connected to a first control terminal to which a source-drain channel is connected between the first input terminal to which the external address is applied and the node 2, and to which the first control signal is applied. A fourth transistor having a gate connected thereto; A fifth transistor having a source-drain channel connected between the node 2 and the first conductive path and a gate connected to a second power terminal to which a power voltage is applied; A sixth transistor having a source-drain channel connected between the first conductive path and the second conductive path and having a gate connected to the first conductive path; A seventh transistor having a source-drain channel connected between the second power supply terminal and the second conductive path and a gate connected to the second control terminal; An eighth transistor having a source-drain channel connected between the second conductive path and node 3 and a gate connected to the second power terminal; A source-drain channel is connected between the node 3 and a third power terminal to which a ground voltage is applied, and a ninth transistor is connected to a gate of a third control terminal to which the third control signal is applied.

In a preferred embodiment of the device, the fourth transistor and the fifth transistor are provided with depletion MOS transistors.

In a preferred embodiment of the device, the sixth through ninth transistors are provided with MOS transistors of n-channel conductivity type.

In a preferred embodiment of the device, the ninth transistor is configured to discharge the second conductive path in response to the third control signal after each operation mode ends.

In a preferred embodiment of the device, the transfer means comprises: a first transfer transistor coupled between a word-drain channel between the word line and node 4 of the memory cell array and a gate coupled to the first conductive path; And a source-drain channel connected between the node 4 and the first power supply terminal, and a second transfer transistor connected to a gate of the second conductive path.

In a preferred embodiment of the device, the first transfer transistor is characterized in that it is provided with an n-channel conductive MOS transistor.

In a preferred embodiment of the device, the second transfer transistor is characterized by being a depletion MOS transistor.

According to another feature of the present invention, a NAND cell unit including a plurality of memory cells having a control gate and a floating gate is provided, and the control gates of the memory cells of each NAND cell unit are corresponding to each word line. Selects a memory cell array and a word line of the memory cell array that are connected in common, transfers a predetermined voltage required in each operation mode to the selected word line, and includes a plurality of row decoder blocks corresponding to each word line. A row decoder of a volatile semiconductor memory device, each row decoder block comprising: a first input terminal to which an external address is input from the outside; A second input terminal to which a clock signal having a predetermined frequency is input from the outside; A first control terminal to which a first control signal is applied from the outside; A first power supply terminal receiving an external voltage applied to the word lines in each operation mode; A second power supply terminal to which a power supply voltage is applied from the outside; A second control terminal to which a second control signal is applied from the outside; A third control terminal to which a third control signal is applied from the outside; A third power supply terminal to which a ground voltage is applied from the outside; A first conductive path charged with a predetermined voltage; A second conductive path charged with a predetermined voltage; A NAND gate connected to each of the first input terminal and the second input terminal; A switch pump connected between the output terminal of the NAND gate and the first conductive path; A depletion MOS transistor having a source-drain channel connected between the first input terminal and node 2 and a gate connected to the first control terminal; A depletion MOS transistor having a source-drain channel connected between the node 2 and the first conductive path and having a gate connected to the second power terminal; An NMOS transistor having a source-drain channel connected between the first conductive path and the second conductive path and having a gate connected to the first conductive path; An NMOS transistor having a source-drain channel connected between the second power supply terminal and the second conductive path and having a gate connected to the second control terminal; An NMOS transistor having a source-drain channel connected between the second conductive path and node 3 and having a gate connected to the second power terminal; An NMOS transistor having a source-drain channel connected between the node 3 and the third power terminal and a gate connected to the third control terminal; A first transfer transistor having a source-drain channel coupled between a node 4 and a word line of the memory cell array, the NMOS transistor having a gate connected to the first conductive path; A source-drain channel is connected between the first power terminal and the node 4, and a second transfer transistor is formed of a depletion MOS transistor having a gate connected to the second conductive path.

Such a device makes it possible to increase the GIBV value of the transfer transistor through the precharge means, which can lower the program speed and the yield due to current leakage.

Reference to the drawings according to an embodiment of the present invention will be described in detail with reference to Figs.

2 to 3, the same reference numerals are given to the components having the same functions as the components shown in FIG.

First embodiment

2 is a circuit diagram showing a circuit of a row decoder of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 2, the memory cell array 10 includes NAND cell units UC including a plurality of memory cells having a control gate and a floating gate, and the memory cells of each of the NAND cell units UC. The control gate is commonly connected to each word line W / Lk-W / Ln corresponding thereto. The row decoder 30 selects each word line (W / Lk-W / Ln) of the memory cell array 10, transfers a voltage required in each operation mode to the selected word line, and supplies each word line (W). / Lk-W / Ln). Each row decoder block 32 includes an input means 33 composed of a NAND gate G1, precharge means 34 composed of NMOS transistors MN1, MN2 and a depletion MOS transistor D5, It consists of a voltage pump means 11 and a transfer means 35 composed of an NMOS transistor T1. Each row decoder block 32k to 32n includes an external address k_address, a clock signal 1o, and first and second control signals , WE) and external voltage (VSi) are input and operate in response.

The input unit 33 receives an external address (k_address) and a clock signal 1o applied from the outside and outputs the clock signal 1o in response thereto. That is, when the external address k_address is the selected external address, a low level 'low level' is applied when the high level 'high level' is an unselected external address, and the clock signal 1o is a square wave having a predetermined frequency. Is approved. Therefore, when the signals k_address 1o are applied to the NAND gate G1 of the input unit 33, when the first external address k_address is selected, the clock signal 1o is received from the NAND gate G1. Is output and the non-selected external address is applied, the clock signal 1o is not output from the NAND gate G1. In response to the clock signal 1o being output from the input means 33, the switch pump 11 performs a voltage pumping operation in response to the high voltage (threshold voltage VSi + threshold voltage Vth of the NMOS transistor T1). L2), and does not perform the voltage pumping operation when the clock signal 1o is not output from the input means 33.

In addition, when performing an operation that does not require a high voltage on the word line, the NMOS transistor MN2 of the precharge means 34 is turned off and the NMOS transistor MN1 is turned on to the same decoder path as a conventional circuit. The voltage is transferred to the gate of the transfer transistor. The precharge means 34 includes the external address k_address and the first control signal. And the second control signal WE are precharged to the conductive path L2 at a predetermined voltage level (Vcc-Vth2). In the case where a high voltage is required, each of the row decoder blocks 32 is divided into a row decoder block 32k into which an external address (k_address) is input and a row decoder block 32n into which an unselected external address (n_address) is input. Suppose In the case of an operation requiring a high voltage, the conductive path L2 is precharged to a predetermined voltage level Vcc + Vth2 before the selected external address k_address and the unselected external address n_address are input. That is, the NMOS transistors MN1 and MN2 of the precharge means 34 have a high level first control signal ( ) Is turned on in response to the second control signal WE, and the conductive path L2 is precharged to the voltage level Vcc-Vth2 through the NMOS transistor MN2 to the gate of the transfer transistor T1 corresponding thereto. Is approved.

In addition, the row decoder block 32k into which the selected external address k_address is input is connected to the conductive path L2 through the input means 33 and the switch pump 11 to the high voltage VSi + Vth, where VSi is the external voltage. Vth represents the threshold voltage of the transfer transistor. The external voltage VSi (programmed) is applied from the outside by turning on the NMOS transistor T1 of the transfer means 35 whose gate is connected to the conductive path L2. Voltage) is transferred to the word line W / Lk corresponding to the selected external address k_address. If the non-selected external address n_address is input, the row decoder block 32n is disabled by the input means 33 by the low level external address n_address so that the switch pump 11 does not perform a voltage pumping operation. Will not. As a result, the voltage level Vcc-Vth2 is applied to the gate of the transfer transistor T1 corresponding to the conductive path L2 of the row decoder block 32n that is initially precharged to the voltage level Vcc-Vth2. . Accordingly, it is possible to increase the GIBV of the transfer transistor T1 of the row decoder block 32n to prevent current leakage of the external voltage VSi so that the word line W / Lk corresponding to the selected external address k_address. Sufficient external voltage (VSi) can be delivered.

In other words, in an operation in which no high voltage is required, the NMOS transistor MN1 of the precharge means 34 is turned on and the NMOS transistor MN2 is turned off so that the transfer transistor corresponding thereto in the same decoder path as the existing circuit. Becomes the voltage at the gate. On the other hand, in the case of transferring a high voltage such as a program operation, the NMOS transistor MN1 of the precharge means 34 is turned off and the NMOS transistor MN2 is turned on to turn off each row decoder block 32k-32n. Each conductive path L2 is precharged to a predetermined voltage level (Vcc-Vth2). At this time, when the selected external address (k_address) is input to the row decoder block 32k, the switch pump 11 performs a voltage pumping operation through the input means 33 to generate a high voltage (VSi + Vth), which is a conductive path ( It is applied to the gate of the transfer transistor T1 through L2). On the other hand, when the unselected external address n_address is input to the row decoder block 32n, the switch pump 11 is not operated so that the initial precharge voltages Vcc-Vth2 remain as transfer transistors of the row decoder block 32n. It is applied to the gate of T1 to transfer the external voltage VSi required for the cell program to the word line.

Second embodiment

3 is a circuit diagram illustrating a circuit of a row decoder of a nonvolatile semiconductor memory device according to a second exemplary embodiment of the present invention.

Referring to FIG. 3, the memory cell array 10 is formed of NAND cell units UC including a plurality of memory cells having a control gate and a floating gate, but the memory cells of each of the NAND cell units UC are included. The control gate is commonly connected to each word line W / Lk-W / Ln corresponding thereto. The row decoder 40 selects each word line (W / Lk-W / Ln) of the memory cell array, transfers a voltage required in each operation mode to the selected word line, and selects each word line (W / Lk-). A plurality of row decoder blocks 42k-42n corresponding to W / Ln). Each row decoder block 42k-42n includes an input means 43 composed of a NAND gate G1, and precharge means composed of NMOS transistors MN3-MN6 and depletion MOS transistors D4 and D5. And 44, a switch pump 11, and a transmission means 45 composed of an NMOS transistor T1 and a depletion MOS transistor T2. Each row decoder block 42k to 42n includes an external address (k-address), a clock signal 1o, and first to third control signals , WE, REC) and external voltage (VSi) are input and operate in response.

The input means 43 receives an external address (k_address) and a clock signal 1o applied from the outside and outputs the clock signal 1o in response thereto. That is, when the external address k_address is the selected external address, a low level 'low level' is applied when the high level 'high level' is an unselected external address n_address, and the clock signal 1o has a square wave having a predetermined frequency. Is applied. Therefore, when the signals k_address 1o are applied to the NAND gate G1 of the input means 43, the clock signal 1o is output from the NAND gate G1 when the first external address is selected. When the non-selected external address is applied, the clock signal 1o is not output from the NAND gate G1. In response to the clock signal 1o being output from the input means 43, the switch pump 11 performs a voltage pumping operation in response to the high voltage (threshold voltage VSi + threshold voltage Vth of the NMOS transistor T1). When outputted to the path L3, and the clock signal 1o is not output from the input means 43, the voltage pumping operation is not performed.

The precharge means 44 has an external address and a first control signal applied from the outside ( ), The second control signal WE and the third control signal REC are input to precharge the second conductive path L4 to a predetermined voltage level (Vcc-Vth). In the case of an operation requiring high voltage, the row decoder block 42k into which the selected external address k_address is input among the row decoder blocks 42k through 42n and the row decoder block into which the unselected external address n_address is input Suppose that it is divided by (42n). In an operation requiring a high voltage, the first and second conductive paths L3 and L4 are precharged to a predetermined voltage level before the selected external address k_address and the unselected external address n_address are input. That is, the depletion MOS transistors D4 and D5 of the precharge means 44 are turned on to charge the first conductive path L3 of each row decoder block 42k-42n to 0 volts, The NMOS transistors MN5 and MN6 are turned on to precharge the second conductive path L4 of each row decoder block 42k-42n to a predetermined voltage level Vcc-Vth. Here, the third control signal REC applied to the gate of the NMOS transistor MN7 of the precharge means 44 is temporarily enabled to discharge the unnecessary voltage of the second conductive path L4. Except in the case, it remains turned off during the operation period.

First, in the row decoder block 42k to which the selected external address k_address is input, a high voltage VSi + Vth is transmitted to the first conductive path L3 through the input means 43 and the switch pump 11. The NMOS transistor T1 of the transfer means 45 having the gate connected to the first conductive path L3 is turned on. In addition, an NMOS transistor MN6 having a gate connected to the first conductive path L3 is also turned on so that a high voltage VSi + Vth charged in the first conductive path L3 is thresholded through the transistor MN6. The high voltage VSi lowered by the voltage Vth is transmitted to the second conductive path L4. Thus, the depletion MOS transistor T2 of the transfer means 45 having the gate connected to the second conductive path L4 and the external voltage VSi applied from the outside through the NMOS transistor T1 correspond to this. It is transferred to the word line W / Lk.

If the non-selected external address (n_address) is input, the row decoder block 42n has the NAND gate G1 of the input means 43 disabled by the external address (n_address), thereby causing a switch pump. The first conductive path L3 is charged to the low level since the 11 does not perform the voltage pumping operation. Accordingly, the NMOS transistor T1 of the transfer means 45 having the gate connected to the first conductive path L3 is turned off and applied to the external voltage VSi applied to the drain thereof. Can be blocked from passing to Ln). The NMOS transistor MN6 of the precharge means 44 is turned off by the first conductive path L3 charged to the low level. At this time, the second conduction path L4 is charged to the predetermined voltage level (Vcc-Vth) by the NMOS transistor MN3 of the precharge means 44 and depletion of the transfer means 45 connected to the gate thereof. Since the GIBV of the MOS transistor T2 can be increased, current leakage of the external voltage VSi can be prevented. Therefore, sufficient external voltage VSi is transferred to the word line W / Lk corresponding to the selected external address k_address.

In other words, during the program operation, the NMOS transistor MN5 of the precharge means 44 is turned on, and the switch pump 11 is driven by the selected external address to transfer the gate connected to the first conductive path L3. The high voltage VSi + Vth is applied to the NMOS transistor T1 at 45. In addition, the NMOS transistor MN6 of the precharge means 44 is turned on by the high voltage VSi + Vth charged in the first conductive path L3, and the voltage is dropped by the threshold voltage Vth thereof. The VSi value is transferred to the second conductive path L4. Accordingly, the depletion MOS transistor T2 and the NMOS transistor T1 are applied to the depletion MOS transistor T2 having a gate connected to the second conductive path L4 so as not to drop the external voltage VSi. ) Transfers the external voltage VSi to the corresponding word line. On the other hand, since the switch pump 11 is not driven by an unselected external address, the first conductive path L3 is charged at a low level, and zero volts is applied to the NMOS transistor T1 of the transmission means 45 connected to the gate. Therefore, no voltage is transmitted to the word line. The GIBV can be increased by applying a predetermined voltage level (Vcc-Vth) to the gate of the depletion MOS transistor T2 of the transfer means 45 through the NMOS transistor MN3 of the precharge means 44. It became.

As described above, in order to prevent the GIBV of the transfer transistor of the row decoder from lowering, a predetermined voltage level is applied to the gate of the transfer transistor corresponding to the unselected external address by using precharge means. As a result, the GIBV of the transfer transistor corresponding to the unselected external address can be increased. Thus, by applying the voltage of 0 volts to the gate of the transfer transistor corresponding to the non-selected external address as in the prior art at a predetermined voltage level through the precharge means, the program voltage is sufficiently worded through the transfer transistor corresponding to the selected external address. You can now pass on the line. Therefore, not only can the program speed be increased, but the program yield can be prevented from being lowered.

Claims (14)

NAND cell units UC including a plurality of memory cells having a control gate and a floating gate, wherein the control gates of the memory cells of each NAND cell unit UC correspond to each word line W / Lk. A memory cell array 10 commonly connected to W / Ln (where k and n are positive integers) and each word line W / Lk-W / Ln of the memory cell array 10; A nonvolatile semiconductor memory having a plurality of row decoder blocks 32k-32n selected and transferring a predetermined voltage required in each operation mode to the selected word line, and corresponding to the word lines W / Lk-W / Ln. In the row decoder of the device, Each row decoder block 32k-32n, A conductive path L2 charged to a predetermined voltage; Receives an external address (k_address) applied from the outside and a clock signal (1o) applied from the outside and has a predetermined frequency, respectively, and outputs the clock signal (1o) in response to the external address (k_address) at a first level. Input means (33) for blocking the output of the clock signal (1o) in response to the external address (k_address) at a second level; In response to the clock signal 1o output from the input means 33, a voltage boosting operation is performed in response thereto, and a predetermined high voltage is output to the conductive path L2, wherein the clock signal is input from the input means 33. A switch pump 11 which does not operate when 1o is not output; The external address k_address and the first control signal applied from outside ) And the second control signal WE, and in response thereto, when a high voltage is required for a predetermined word line of the memory cell array 10, before the selected or unselected external address k_address is input, the conductive path L2 is input. Precharge means (34) for precharging?) To a predetermined voltage level; When the selected external address (k_address) is input to the input means 33, the external voltage VSi applied from the outside in response to the high voltage transmitted from the switch pump 11 to the conductive path L2 is received. Is transmitted to the corresponding word line (W / Lk), and when the non-selected external address (k_address) is input to the input means (33), the predetermined voltage level charged in the conductive path (L2) is received. And transfer means (35) for blocking the external voltage (VSi) from being transmitted to the word line (W / Ln) in response. The method of claim 1, The precharge means 34 may include the first control signal ( And a first transistor (MN1) having a gate connected to the first control terminal (3) to which is applied) and a source-drain channel connected between the first input terminal (1) and node 1 to which the external address (k_address) is applied. ; A second transistor (D3) having a gate connected to a second power supply terminal (5) to which a power supply voltage (Vcc) is applied from the outside, and a source-drain channel connected between the node 1 and the conductive path (L2); A third transistor having a gate connected to the second control terminal 6 to which the second control signal WE is applied, and a source-drain channel connected between the second power terminal 5 and the conductive path L2; MN2), characterized in that the row decoder of the nonvolatile semiconductor memory device. The method of claim 2, And the first transistor (MN1) and the third transistor (MN3) are n-channel conductive MOS transistors. The method of claim 2, The second transistor (D3) is a row decoder of the nonvolatile semiconductor memory device, characterized in that provided with a depletion-type MOS transistor. NAND cell units UC including a plurality of memory cells having a control gate and a floating gate, wherein the control gates of the memory cells of each NAND cell unit UC correspond to each word line W / Lk. A memory cell array 10 commonly connected to W / Ln (where k and n are positive integers) and each word line W / Lk-W / Ln of the memory cell array 10; A nonvolatile semiconductor memory having a plurality of row decoder blocks 32k-32n selected and transferring a predetermined voltage required in each operation mode to the selected word line, and corresponding to the word lines W / Lk-W / Ln. In the row decoder of the device, Each row decoder block 32k-32n, A first input terminal 1 to which an external address k_address is input from the outside; A second input terminal 2 to which a clock signal 1o having a predetermined frequency is input from the outside; The first control signal from the outside ( A first control terminal 3 to which is applied; A first power supply terminal 4 for receiving an external voltage VSi applied to the word lines W / Lk to W / Ln in each operation mode; A second power supply terminal 5 to which a power supply voltage Vcc is applied from the outside; A second control terminal 6 to which a second control signal WE is applied from the outside; A conductive path L2 charged to a predetermined voltage; A NAND gate (G1) connected to each of the first input terminal (1) and the second input terminal (2); A switch pump 11 connected between an output terminal of the NAND gate G1 and the conductive path L2; An NMOS transistor MN1 having a source-drain channel connected between the first input terminal 1 and node 1 and a gate connected to the first control terminal 3; A depletion MOS transistor (D3) having a source-drain channel connected between the node 1 and the conductive path (L2) and a gate connected to the second power supply terminal (5); An NMOS transistor (MN2) having a source-drain channel connected between the second power supply terminal (5) and the conductive path (L2) and a gate connected to the second control terminal (6); The NMOS transistor T1 has a source-drain channel connected between the first power supply terminal 4 and the word line W / Lk of the memory cell array 10. Low Decoder. NAND cell units UC including a plurality of memory cells having a control gate and a floating gate, wherein the control gates of the memory cells of each NAND cell unit UC correspond to each word line W / Lk. A memory cell array 10 commonly connected to W / Ln (where k and n are positive integers) and each word line W / Lk-W / Ln of the memory cell array 10; A nonvolatile semiconductor memory having a plurality of row decoder blocks 42k-42n corresponding to each word line (W / Lk-W / Ln) and transferring a predetermined voltage required for each operation mode to the selected word line. In the row decoder of the device, Each row decoder block 42k-42n is, A first conductive path L3 charged to a predetermined voltage; A second conductive path L4 charged with a predetermined voltage; The clock signal 1o is output in response to the external address k_address applied from the outside and the clock signal 1o applied from the outside and having a predetermined frequency, and outputs the clock signal 1o in response to the external address k_address of the first level. Input means (43) for blocking the output of the clock signal (1o) in response to the external address (k_address) at two levels; In response to the clock signal 1o output from the input means 33, a voltage boosting operation may be performed to output a predetermined high voltage to the first conductive path L3, from the input means 33. A switch pump 11 which does not operate when the clock signal 1o is not output; The external address k_address and the first control signal applied from outside ), A second control signal WE and a third control signal REC are received, and in response to this, when a high voltage is required for a predetermined word line of the memory cell array 10, a selected or unselected external address k_address Precharge means (44) for precharging the second conductive path (L4) to a predetermined voltage level before is inputted; When the external address k_address selected by the input means 33 is input, the high voltage transferred from the switch pump 11 to the conductive path L3 and the predetermined voltage charged in the second conductive path L4. In response to the level, the external voltage VSi is transferred to the word line W / Lk corresponding thereto, and when the non-selected external address k_address is input to the input means 33, the conductive path ( A second level voltage and a predetermined voltage level charged in the second conductive path L4 are respectively received from L2, and in response thereto, the external voltage VSi is blocked from being transferred to the word line W / Ln. And a transfer means (45). The method of claim 6, The procharge means 44 has a source-drain channel connected between the first input terminal 1 and the node 2 to which the external address (k_address) is applied, and the first control signal ( A fourth transistor D4 having a gate connected to the first control terminal 3 to which is applied; A fifth transistor (D5) having a source-drain channel connected between the node 2 and the first conductive path (L3) and having a gate connected to the second power terminal (5); A sixth transistor MN6 having a source-drain channel connected between the first conductive path L3 and the second conductive path L4 and a gate connected to the first conductive path L3; A second control terminal 6 to which a source-drain channel is connected between the second power supply terminal 5 to which the power supply voltage Vcc is applied and the second conductive path L4 and to which the second control signal WE is applied. A seventh transistor MN3 having a gate connected thereto; An eighth transistor MN4 having a source-drain channel connected between the second conductive path L4 and node 3 and a gate connected to the second power terminal 5; A source-drain channel is connected between the node 3 and the third power terminal 8 to which the ground voltage Vss is applied, and a gate is connected to the third control terminal 7 to which the third control signal REC is applied. The row decoder of the nonvolatile semiconductor memory device, characterized in that the ninth transistor (MN5). The method of claim 7, wherein The fourth transistor (D4) and the fifth transistor (D5) are provided as a depletion MOS transistor, the row decoder of the nonvolatile semiconductor memory device. The method of claim 7, wherein The sixth through ninth transistors (MN6, MN3, MN4, and MN5) are n-channel conductive MOS transistors. The row decoder of the nonvolatile semiconductor memory device. The method according to claim 7 or 9, And the ninth transistor (MN5) discharges the second conductive path (L4) in response to the third control signal (REC) after each operation mode ends. The method of claim 6, The transfer means 45 includes a first transfer transistor having a source-drain channel connected between the word line W / Lk and the node 4 of the memory cell array 10 and a gate connected to the first conductive path L3. (T1); And a second transfer transistor T2 having a source-drain channel connected between the node 4 and the first power terminal 1 and having a gate connected to the second conductive path L4. Row decoder of the memory device. The method of claim 11, And the first transfer transistor (T1) is an n-channel conductive MOS transistor. The method of claim 11, The second transfer transistor (T2) is a row decoder of a nonvolatile semiconductor memory device, characterized in that provided with a depletion MOS transistor. NAND cell units UC including a plurality of memory cells having a control gate and a floating gate, wherein the control gates of the memory cells of each NAND cell unit UC correspond to each word line W / Lk. A memory cell array 10 commonly connected to W / Ln (where k and n are positive integers) and each word line W / Lk-W / Ln of the memory cell array 10; A nonvolatile semiconductor memory having a plurality of row decoder blocks 42k-42n corresponding to each word line (W / Lk-W / Ln) and transferring a predetermined voltage required for each operation mode to the selected word line. In the row decoder of the device, Each row decoder block 42k-42n is, A first input terminal 1 to which an external address k_address is input from the outside; A second input terminal 2 to which a clock signal 1o having a predetermined frequency is input from the outside; The first control signal from the outside ( A first control terminal 3 to which is applied; A first power supply terminal 4 for receiving an external voltage VSi applied to the word lines W / Lk to W / Ln in each operation mode; A second power supply terminal 5 to which a power supply voltage Vcc is applied from the outside; A second control terminal 6 to which a second control signal WE is applied from the outside; A third control signal 7 to which a third control signal REC is applied from the outside; A third power supply terminal 8 to which a ground voltage Vss is input from the outside; A first conductive path L3 charged to a predetermined voltage; A second conductive path L4 charged with a predetermined voltage; A NAND gate (G1) connected to each of the first input terminal (1) and the second input terminal (2); A switch pump 11 connected between the output terminal of the NAND gate G1 and the first conductive path L3; A depletion MOS transistor (D4) having a source-drain channel connected between the first input terminal (1) and node 2 and a gate connected to the first control terminal (3); A depletion MOS transistor (D5) having a source-drain channel connected between the node 2 and the first conductive path (L3) and having a gate connected to the second power terminal (5); An NMOS transistor MN6 having a source-drain channel connected between the first conductive path L3 and the second conductive path L4 and having a gate connected to the first conductive path L3; An NMOS transistor (MN3) having a source-drain channel connected between the second power supply terminal (5) and the second conductive path (L4) and having a gate connected to the second control terminal (6); An NMOS transistor MN4 having a source-drain channel connected between the second conductive path L4 and node 3 and having a gate connected to the second power supply terminal 5; An NMOS transistor MN5 having a source-drain channel connected between the node 3 and the third power terminal 8 and a gate connected to the third control terminal 7; A first transfer transistor T1 comprising an NMOS transistor connected between a node 4 and a word line W / Lk of the memory cell array 10 and having a gate connected to the first conductive path L3. )Wow; A source-drain channel is connected between the first power supply terminal 4 and the node 4 and is provided as a second transfer transistor T2 made of a depletion MOS transistor having a gate connected to the second conductive path L4. And a row decoder of a nonvolatile semiconductor memory device.