KR102766820B1 - Display device having narrow bezel - Google Patents

Abstract

In the display device of the present invention, since the common voltage link line is arranged on the same layer as the common electrode line and no separate connecting wire is provided, an increase in contact resistance due to contact between the connecting wire and the common voltage link line and the common electrode line is prevented, and a connection area due to the connecting wire is unnecessary. The common voltage link line and the common electrode line are arranged on the same layer and are integrally formed with the same metal, and a transparent conductive layer is arranged below the common voltage link line and the common electrode line.

Description

DISPLAY DEVICE HAVING NARROW BEZEL

The present invention relates to a display device, and more particularly, to a display device capable of stabilizing a common voltage by changing a connection structure of a common voltage link line and reducing the area of a bezel by minimizing a connection area of the common voltage link line.

Recently, with the development of various portable electronic devices such as mobile phones, PDAs, and notebook computers, the demand for thin, compact, and light flat panel display devices that can be applied to these devices is gradually increasing. Liquid crystal displays, plasma display panels, organic electroluminescent display devices, and electrophoretic display devices are being actively studied as such flat panel display devices.

These flat panel displays are not only used in small portable electronic devices such as mobile phones and tablet PCs, but are also being used in large electronic devices such as TVs recently.

Fig. 1 is a drawing showing a conventional flat panel display device. As shown in Fig. 1, the conventional display device (1) is composed of a display panel (10) on which an actual image is implemented, a plurality of flexible films (40) having one end attached to the display panel (10), and a printed circuit board (30) attached to the other end of the flexible films (40) and electrically connected to the display panel (10) through the flexible films (40).

Although not shown in the drawing, the display panel (10) is composed of a display area where an actual image is implemented and a pad area that is arranged outside the display area and electrically connects the display panel to the outside. The display area is provided with a plurality of pixel areas defined by a plurality of gate lines and data lines that are arranged perpendicular to each other, and a thin film transistor, which is a switching element, is arranged in each pixel area.

In the pad area, gate pads and data pads are arranged to which the gate lines and data lines of the display area are connected, so that external scanning signals and image signals are applied to the gate lines and data lines through the gate pads and data pads.

A flexible film (40) is attached to the pad area of the display panel (10). Although not shown in the drawing, metal wiring is arranged on the flexible film (40) and a link line is arranged on the pad area of the display panel (10), so that the metal wiring is electrically connected to the pad of the pad area to supply an external signal to the display panel.

Various components such as a connector, a timing control unit, and a power supply unit are mounted on the PCB (30), and various signals such as a control signal are applied to the display panel (10) through the flexible film (40). At this time, although not shown in the drawing, a metal wiring is formed on the PCB (30), and is electrically connected to the metal wiring of the PCB (30) and at the same time electrically connected to the link line of the display panel (10), so that the signal of the PCB (30) is applied to the flexible film (40) and the display panel (10).

However, the display device with the above structure has the following problems.

In general, a flexible film (40) is attached to a pad area of a display panel (10), and a metal wiring of the flexible film (40) is connected to a link line of the pad area, so that a signal is applied to the display panel (10). There are various link lines such as a gate link line, a data link line, and a common voltage link line, and these link lines are electrically connected to the gate line, data line, and common electrode line of the display panel, respectively.

Accordingly, a connection area exists in the pad area where the link line is connected to the signal line of the display panel, and this connection area causes an increase in the area of the pad area, which in turn increases the area of the bezel of the display device. In addition, a separate connection wire must be provided to connect the link line and the signal line, and since this connection wire causes contact resistance when connected to the link line, a delay occurs in the signal applied to the display panel, and this signal delay causes a deterioration in the picture quality of the display device.

The present invention has been made in consideration of the above points, and aims to provide a display device capable of preventing signal delay due to contact resistance and an increase in bezel area due to a connection area by forming a common voltage link line integrally on the same layer as a common electrode line.

To achieve the above purpose, in the display device according to the present invention, the common voltage link line is arranged on the same layer as the common electrode line, so that no separate connection wiring is provided, thereby preventing an increase in contact resistance due to contact between the connection wiring and the common voltage link line and the common electrode line, and eliminating the need for a connection area due to the connection wiring.

The display panel is composed of a display area where an actual image is implemented and a pad area arranged on the periphery of the display area where various link lines are arranged. The display area includes a plurality of pixel areas having thin film transistors, common electrodes, and pixel electrodes. A common electrode line that is connected to the common electrode and applies a common voltage to the common electrode is arranged on the periphery of the display area.

Various link lines including a common voltage link line are arranged in the pad area, and the link lines are electrically connected to the metal wiring of a flexible film attached to a display panel, so that an external signal is input to the link lines through the metal wiring.

The common voltage link line and the common electrode line are arranged on the same layer (e.g., a protective layer) and can be formed integrally with a metal having good conductivity, such as copper (Cu). In addition, a transparent conductive layer is arranged below the common voltage link line and the common electrode line, and the transparent conductive layer extends to the pixel area of the display area to become a common electrode.

The present invention forms a common voltage link line integrally with a common electrode line on the same layer. Accordingly, when the common voltage link line and the common electrode line are arranged on different layers, a connecting wire for connecting them is not required, and the occurrence of contact resistance due to the connecting wire can be prevented. As a result, it is possible to prevent image quality degradation due to signal delay of the common voltage.

In addition, since the common voltage link line is formed integrally on the same layer as the common electrode line in the present invention, a connection area by a connecting wire is not required, and thus an increase in the area of the pad area can be prevented, and as a result, an increase in the bezel area can be prevented.

Figure 1 is a drawing schematically showing the structure of a conventional display device.
Figure 2 is a drawing schematically showing the structure of a display device according to the present invention.
Figure 3 is a cross-sectional view of a display device according to the present invention.
Figures 4a and 4b are cross-sectional views showing the structure of the pad area of the display device.
FIGS. 5A to 5D are drawings showing a method for manufacturing a display device according to the present invention.

Hereinafter, the present invention will be described in detail with reference to the attached drawings.

FIG. 2 is a drawing showing the structure of a display device according to the present invention. As shown in FIG. 2, the display device according to the present invention is composed of a display panel (110) on which an actual image is implemented, a plurality of flexible films (140) attached to the display panel (110) to apply various signals including image signals to the display panel (110), and a PCB (130) on which various elements such as a timing control unit and a power supply unit are mounted and attached to the flexible film (140) to apply various signals to the display panel (110) through the flexible film (140).

The display panel (110) may be applied with various flat panel display panels. For example, the display panel (110) may include a liquid crystal display panel, an organic electroluminescent display panel, an electrophoretic display panel, a plasma display panel, etc. Although not shown in the drawing, the display panel (110) is composed of a first substrate and a second substrate made of a transparent material such as glass or plastic, a plurality of gate lines and data lines arranged on the first substrate to define a plurality of pixel areas, a thin film transistor which is a switching element arranged in each pixel area to apply an external signal to the pixel area, a pixel electrode and a common electrode arranged in each of the pixel areas, a color filter layer arranged in each pixel area to implement color, and an image implementing means arranged in each pixel area to apply voltage to the pixel electrode and the common electrode as a signal is applied from the outside to display an image.

The above image display means varies depending on the type of the display panel. If the display panel (110) is an organic electroluminescent display panel, the image display means is an organic light-emitting layer. If the display panel (110) is a liquid crystal display panel, the display panel is a liquid crystal layer. If the display panel (110) is an electrophoretic display panel, the image display means is an electrophoretic layer. If the display panel (110) is a plasma display panel, the image display means is a plasma layer.

The above display panel (110) includes a display area (AA) and a pad area (DA). The display area (AA) is an area where a plurality of pixel areas are arranged, and when an image signal is applied, an image display means is driven to display an actual image. The pad area (DA) is an area formed on the outer edge of the display area (AA), and gate pads and data pads that connect gate lines and data lines to external wiring, and various link lines that apply various signals to the gate pad and data pad are arranged.

In the drawing, the pad area (DA) is arranged along the entire perimeter of the display panel (110), but the pad area (DA) may be formed on one or both sides of the display area (AA).

First and second gate drivers (116a, 116b) are arranged in the left and right pad areas (DA) of the display device, respectively. The first and second gate drivers (116a, 116b) receive a gate control signal from the PCB (130) through a flexible film (140), generate a gate signal, and then output the signal to a thin film transistor of the display area (AA) to drive the thin film transistor, and are electrically connected to the gate pad of the pad area (DA).

The above first and second gate driving units (116a, 116b) may be of the COP (Chip On Glass) type in which a semiconductor chip is mounted on a first substrate, or of the GIP (Gate In Panel) type in which various elements such as transistors are formed directly on a glass substrate.

In the drawing, the first and second gate driving units (116a, 116b) are arranged in multiples on both sides of the display area (AA) to apply gate signals to the inside of the display area (AA) through both sides of the display area (AA), but the gate driving units (116a, 116b) may be arranged only on one side of the display area (AA) to apply gate signals through one side of the display area (AA).

As illustrated in FIG. 1, various link lines such as a gate link line (152), a common voltage link line (154), and a data link line (156) are arranged in the pad area (DA). The gate link line (152), the common voltage link line (154), and the data link line (156) are each connected to a metal wire formed on a flexible film (140) to apply a signal output from the flexible film (140) to the display panel (110).

The gate link line (152) is extended and arranged from the bonding area of the flexible film (140) to the first and second gate drivers (116a, 116b), and applies the gate control signal input through the flexible film (140) to the input terminals of the first and second gate drivers (116a, 116b). The data link line (156) is extended and arranged from the bonding area of the flexible film (140) to the bottom of the display area (AA), and is electrically connected to a data pad (not shown in the drawing), and applies the gate control signal input through the flexible film (140) to the display area (AA).

The common voltage link line (154) is arranged to extend from the adhesive area of the flexible film (140) to the bottom of the display area (AA) and is electrically connected to the common electrode, thereby applying the common voltage input through the flexible film (140) to the display area (AA). At this time, a common electrode line (160) is arranged along the perimeter of the display area (AA), and the common electrode line (160) is electrically connected to the common electrode arranged in the display area (AA) to apply the common voltage to the display area (AA). The common voltage link line (154) is connected to the common electrode line (160) to apply the common voltage to the common electrode line (160), and the common voltage is transmitted from the common electrode line (160) to the common electrode, thereby applying the common voltage to the display area (AA).

Meanwhile, the structure of the common electrode line (160) and the common voltage may vary depending on the type of the display device (e.g., the type of display mode in the display device such as a liquid crystal display (LCD) or an organic light emitting display (OLED) device, for example, N (Twisted Nematic) mode or IPS (In Plane Switching) mode in the case of a liquid crystal display), but in the present invention, the common electrode line (160) of such various structures may be electrically connected to the common voltage link line (154) arranged in the pad area (DA).

The PCB (130) is equipped with various components such as a timing control unit, a power supply unit, and a connector, and supplies a control signal and power to the display panel (110) according to a signal applied from an external system (such as an electronic product on which a display device is installed). When an external power, an image signal, and a plurality of timing signals are input from an external system such as a TV or a graphic card through the connector, the power supply unit generates and outputs a plurality of powers required for the display device using the external power, and the timing control unit generates and outputs image data, a plurality of gate control signals, and a plurality of data control signals using the image signal and the plurality of timing signals. For example, the plurality of powers may include a power supply voltage (VDD), a base voltage (VSS), a common voltage (VCOM), a gate high voltage (VGH), and a gate low voltage (VGL).

Additionally, the plurality of timing signals may include a data enable signal (DE), a horizontal sync signal (HSY), a vertical sync signal (VSY), and a clock signal (CLK), the plurality of gate control signals may include a gate start pulse signal (GSP), a gate shift clock signal (GSC), and a gate output enable signal (GOE), and the data control signals may include a source start pulse signal (SSP), a source sampling clock signal (SSC), a source output enable signal (SOE), a polarity control signal (POL), a gamma reference signal (GAMMA), and a panel interface signal (EPI).

Although not shown in the drawing, various metal wirings are arranged on the upper and lower surfaces of the PCB (130) to transmit various signals output from various components such as a timing control unit, a power unit, and a connector to the flexible film (140) and the display panel (110). At this time, the metal wirings on both sides of the PCB (130) are electrically connected to each other through through holes.

Various components such as the above timing control unit, power supply unit, and connector may be mounted on the upper surface of the PCB (130), but considering that a plurality of flexible films (140) are attached to the upper surface of the PCB (130), they may be mounted on the rear surface of the PCB (130) to optimize, i.e. minimize, the area of the PCB (130).

FIG. 3 is a cross-sectional view of a display device according to the present invention. In the drawing, only one pixel area arranged in the display area (AA) and a portion of the pad area (DA) are illustrated for convenience of explanation. Although the drawing illustrates a liquid crystal display as an example, the present invention is not limited to such a liquid crystal display, but may be applied to various display devices such as an organic electroluminescence display or an electrophoretic display.

As illustrated in FIG. 3, a thin film transistor is arranged in a pixel area of a display area (AA) on a first substrate (210) made of a transparent material such as glass or plastic. The thin film transistor is composed of a gate electrode (221) arranged on the first substrate (210), a gate insulating layer (212) laminated over the entire first substrate (210), a semiconductor layer (222) arranged on the gate insulating layer (212), and a source electrode (224) and a drain electrode (225) arranged on the semiconductor layer (222).

The above gate electrode (221) is composed of a single layer or multiple layers made of an opaque metal with good conductivity, such as Cr, Mo, Ta, Cu, Ti, Al or an Al alloy, and although not shown in the drawing, a gate line is formed on the first substrate (210) simultaneously with the gate electrode (221). The gate insulating layer (212) is composed of a single layer or double layers made of an inorganic insulating material, such as SiOx or SiNx, and the semiconductor layer (222) may be composed of a semiconductor material, such as amorphous silicon (a-Si) or crystalline silicon, and an oxide semiconductor, such as IGZO (Indium Gallium Zinc Oxide). In addition, the source electrode (224) and the drain electrode (225) may be composed of an opaque metal with good conductivity, such as Cr, Mo, Ta, Cu, Ti, Al or an Al alloy. Although not shown in the drawing, a data line is formed simultaneously with the formation of the source electrode (224) and the drain electrode (225) on the gate insulating layer (212).

Although not shown in the drawing, a semiconductor material with impurities added thereto is formed between the semiconductor layer (222) and the source electrode (225) and the drain electrode (225), thereby forming an ohmic contact layer that ohmically contacts the semiconductor layer (222), the source electrode (224), and the drain electrode (225).

Meanwhile, in the drawing, the thin film transistor is disclosed as a bottom gate type, but the present invention is not limited to a thin film transistor of this specific structure, and may be applied to various thin film transistors such as a top gate type thin film transistor or a coplanar type thin film transistor.

A first protective layer (214) is laminated on the above thin film transistor, and a common electrode (232) is arranged in the display area (AA) of the first protective layer (214), and a common electrode line (160) and a common voltage link line (154) are arranged in the pad area (DA).

The common electrode (232) is formed over the entire area of each pixel area arranged in the display area (AA), and is composed of a transparent metal oxide such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The common electrode line (160) is arranged along the perimeter of the display area (AA) and is connected to the common electrode (232) to apply a common voltage to the common electrode (232), and may be composed of a metal with good conductivity such as copper (Cu). Meanwhile, the common electrode line (160) may be arranged in various structures, such as a structure in which it is arranged along two adjacent sides, rather than being formed along the perimeter of the display area (AA).

In addition, a transparent conductive layer (232a) is arranged below the common electrode line (160). The transparent conductive layer (232a) is formed integrally with the common electrode (232) and is electrically connected to the common electrode line (160), so the common electrode (232) and the common electrode line (160) are electrically connected by the transparent conductive layer (232a).

Meanwhile, since the common electrode line (160) is arranged along the perimeter of the display area (AA), it can be considered to be arranged in the display area or can be said to be arranged in the pad area (DA). In the drawing, it is illustrated as being arranged in the pad area (DA) for convenience of explanation.

In addition, a common voltage link line (154) is arranged in the pad area (DA) of the first protective layer (214). The common voltage link line (154) is made of a metal having good conductivity, such as copper (Cu). In particular, in the present invention, the common voltage link line (154) is formed integrally with the common electrode line (160), so that a separate connecting wire for electrically connecting the common voltage link line (154) and the common electrode line (160) is not required. Like the common electrode line (160), a transparent metal layer may be arranged under the common voltage link line (154).

As described above, a second protective layer (216) is laminated over the entire first substrate (210) on the second protective layer (214) on which the common electrode (232) and the common voltage link line (154) are arranged. At this time, the second protective layer (216) may be composed of an organic insulating layer such as photoacrylic, and may also be composed of a double layer of an organic insulating layer and an inorganic insulating layer.

A pixel electrode (236) is arranged in the display area (AA) of the second protective layer (216). At this time, the pixel electrode (236) may be composed of a transparent metal oxide such as ITO or IZO. The pixel electrode (236) is provided with a plurality of slits (236a) extending in one direction, so that an electric field is formed between the upper surface of the lower common electrode (232) and the edge area of the slits (236a).

Although not shown in the drawing, the pixel electrode (236) is electrically connected to a data link line through a data line (not shown in the drawing), so that an image signal is applied to the pixel electrode (236).

Meanwhile, in the drawing, the common electrode (232) is formed in a dummy shape over the entire pixel area and the pixel electrode (236) is formed in a shape having a plurality of slits (236a), but the common electrode (232) may be provided with a plurality of slits and the pixel electrode (236) may be formed in a dummy shape. In addition, the common electrode (232) and the pixel electrode (236) may be formed in a plurality of band shapes extending in a certain direction with a certain width and a certain interval, respectively.

A black matrix (252) and a color filter layer (254) are arranged on a second substrate (250) made of a transparent material such as glass or plastic. The black matrix (252) is intended to prevent light from leaking into areas where actual images are not realized, such as between pixel areas and thin film transistor formation areas, thereby deteriorating the image quality, and may be composed of a metal oxide such as CrO or CrOx, or a black resin. In addition, the color filter layer (254) is intended to realize an actual image, and is composed of a resin containing pigments or dyes, and is composed of R (Red), G (Green), and B (Blue) sub-color filter layers. Although not shown in the drawing, a planarizing film may be formed on the color filter layer (134).

As described above, a first substrate (210) on which a thin film transistor is formed and a second substrate (250) on which a color filter layer (254) is arranged are bonded together, and a liquid crystal layer (240) is formed between them to complete a liquid crystal display device.

As described above, in the present invention, the common electrode (232) is disposed on the first protective layer (214) and the pixel electrode (234) is disposed on the second protective layer (216). The common electrode (232) is connected to the common voltage link line (154) through the common electrode line (160) so that a common voltage is applied, and the pixel electrode (234) is connected to the data link line so that an image signal is applied.

In particular, in the present invention, the common voltage link line (154) is formed integrally with the common electrode line (160) on the first protective layer (214), and the reason for this will be described in detail with reference to the drawings.

FIG. 4a is a drawing showing a part of a pad area of a liquid crystal display device having a structure in which a common voltage link line (154) is not formed integrally with a common electrode line (160).

As shown in Fig. 4a, in the liquid crystal display device of this structure, a common voltage link line (154) is arranged on a first substrate (210) and a common electrode line (160) is arranged on a first protective layer (214). At this time, the common voltage link line (154) may be composed of the same metal as the gate electrode of the thin film transistor.

The common voltage link line (154) and the common electrode line (160) are arranged in different layers, and thus are electrically connected by a connecting wire (237). A second contact hole (216b) is formed in the gate insulating layer (212), the first protective layer (214), and the second protective layer (216) above the common voltage link line (154), and a third contact hole (216c) is formed in the second protective layer (216) above the common electrode line (160), and a connecting wire (237) is arranged inside the second protective layer (216), the second contact hole (216b), and the third contact hole (216c), so that the common voltage link line (154) and the common electrode line (160) are electrically connected. At this time, the connecting wire (237) may be composed of a transparent metal oxide such as ITO or IZO.

In addition, a first contact hole (216a) is formed in the gate insulating layer (212), the first protective layer (214), and the second protective layer (216) on the upper portion of the common voltage link line (154), and a transparent metal oxide layer is formed thereon, so that when the flexible film (140) is attached to the display panel (110), the common voltage link line (154) is electrically connected to the metal wiring formed on the flexible film (140). At this time, the transparent metal oxide layer may be formed separately from the connecting wiring (237), but may also be formed integrally.

As described above, when the common voltage link line (154) and the common electrode line (160) are not formed integrally on the same layer but are arranged on different layers, a separate connecting wire (237) must be provided to electrically connect the common voltage link line (154) and the common electrode line (160). However, in this case, since the connecting wire (237) made of metal oxide must be electrically connected to the common voltage link line (154) and the common electrode line (160) made of metal, contact resistance occurs between the connecting wire (237) and the common voltage link line (154) and between the connecting wire (237) and the common electrode line (160). Since the occurrence of such contact resistance causes a signal delay due to an increase in resistance when a common voltage is applied, it becomes an important factor in deteriorating the image quality of the display device.

In addition, in order to electrically connect the common voltage link line (154) and the common electrode line (160) by the connecting wire (237), a second contact hole (216b) and a third contact hole (216c) must be formed in the gate insulating layer (212), the first protective layer (214), and the second protective layer (216). That is, in the display device of this structure, a connection area of a set width (d) must be secured in order to electrically connect the common voltage link line (154) and the common electrode line (160), and this connection area causes an increase in the pad area (DA), which ultimately increases the bezel area of the display device.

On the other hand, as illustrated in FIG. 4b, in the present invention, since the common voltage link line (154) and the common electrode line (160) are integrally formed with a metal such as copper (Cu) on the first protective layer (214), a separate connecting wire is not required. Accordingly, contact resistance due to contact between the connecting wire made of metal oxide and the metal does not occur, so that image quality degradation due to signal delay can be prevented. In addition, since a connection area such as a contact hole for connecting the common voltage link line (154) and the common electrode line (160) by the connecting wire is not required, the bezel area does not increase due to an increase in the pad area (DA).

Meanwhile, in FIG. 4b, a contact hole (216a) is formed in the second protective layer (216) above the common voltage link line (154), and a transparent conductive layer (273) is formed thereon, so that when the common voltage link line (154) and the flexible film (140) are attached to the display panel (110), the common voltage link line (154) is electrically connected to the metal wiring formed on the flexible film (140).

Hereinafter, a method for manufacturing a display device according to the present invention will be described in detail with reference to the attached drawings.

FIGS. 5a to 5d are drawings showing a method for manufacturing a display device according to the present invention.

As shown in Fig. 5a, first, Cr, Mo, Ta, Cu, Ti, Al or Al alloy is laminated on a substrate (210) made of a transparent material such as glass or plastic material by a sputtering method, and then etched to form a gate electrode (221) in a display area (AA), and then a gate insulating layer (212) made of an organic insulating material such as SiOx or SiNx is laminated thereon. At this time, the gate insulating layer (212) may be composed of a single layer or double layers.

After that, a semiconductor material such as an amorphous semiconductor, a crystalline semiconductor, or an oxide semiconductor is laminated and etched on the gate insulating layer (212) to form a semiconductor layer (222), and then Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy is laminated over the entire first substrate (210) by a sputtering method and then etched to form a source electrode (224) and a drain electrode (225).

Next, as shown in Fig. 5b, a first protective layer (214) is formed over the entire first substrate (210), and then a common electrode (232) is formed in the display area (AA) and a common electrode line (160) and a common voltage link line (154) are formed in the dummy area (DA).

At this time, the first protective layer (214) can be formed by laminating an organic material such as photoacrylic, and can also be formed by continuously laminating an inorganic material and an organic material.

In addition, the common electrode (232), common electrode line (160), and common voltage link line (154) are formed by sequentially stacking a metal oxide such as ITO or IZO and a metal such as Cu, and then selectively etching the double metal layers stacked by a half tone mask, thereby forming a common electrode (232) made of a transparent metal oxide in the display area (AA), and forming a common electrode line (160) and a common voltage link line (154) made of Cu and a transparent conductive layer (232a) thereunder in the dummy area (DA). That is, the common electrode (232), the common electrode line (160), and the common voltage link line (154) are formed by a single mask process.

Thereafter, as illustrated in FIG. 5c, an organic material or an organic material/inorganic material is laminated and etched over the entire first substrate (210) to form a second protective layer (216) composed of an organic layer or an organic layer/inorganic layer, and then a transparent metal oxide such as ITO or IZO is laminated and etched thereon to form a pixel electrode (236). At this time, a plurality of slits (236a) extending in one direction may be formed in the pixel electrode (236), and the pixel electrode (236) is electrically connected to the drain electrode (225) through contact holes formed in the first and second protective layers (214, 216).

In addition, although not shown in the drawing, a contact hole is formed in the second protective layer (216) of the pad area (DA) so that the common voltage link line (154) is exposed to the outside, and a metal oxide layer is disposed thereon so that the common voltage link line (154) can be electrically connected to the metal wiring of the flexible film.

Next, as shown in FIG. 5d, a metal oxide such as CrO or CrOx is laminated on a second substrate (250), and then etched, or a black resin is laminated and then patterned to form a black matrix (252) in the display area (AA), and a resin containing pigment or dye is laminated and patterned to form a color filter layer (254) in the display area (AA).

Thereafter, a sealant is applied to the outer area of at least one of the first substrate (210) and the second substrate (250) to bond the first substrate (210) and the second substrate (250), and a liquid crystal layer (240) is provided between the first substrate (210) and the second substrate (250), thereby completing the liquid crystal display device.

As described above, in the present invention, since the common voltage link line is formed integrally on the same layer as the common electrode line, signal delay due to contact resistance and reduction in bezel area can be prevented compared to a structure in which the common voltage link line and the common electrode line are arranged on different layers.

Meanwhile, although the above detailed description has described a display device of a specific structure as an example, the present invention is not limited to the display device of this specific structure. For example, the above detailed description has described a liquid crystal display as an example, but the present invention is not limited to the liquid crystal display, but can be applied to all structures of display devices equipped with a common voltage link line, such as an organic light emitting display, a plasma display, and an electrophoretic display.

In addition, although the above description discloses a specific display mode and a specific electrode structure (e.g., the structure of the common electrode and the pixel electrode), the present invention is not limited to this specific display mode and the specific electrode structure, but can be applied to display devices of all currently known display modes and electrode structures.

110: Display panel 130: Printed circuit board
140 : Soft film 152,154,156 : Link line
160: Common electrode line 210,250: Substrate
232: Common electrode 236: Pixel electrode

Claims (8)

A display panel including a display area and a pad area located at the periphery of the display area;
A common electrode line arranged along the outer perimeter of the display area and applying a common voltage to the display area; and
It is composed of a common voltage link line that is arranged in the above pad area and electrically connected to the common electrode line to apply a common voltage to the common electrode line.
The above common voltage link line is placed on the same layer as the common electrode line,
The above display panel,
A gate line arranged on a substrate;
A plurality of pixel areas defined by the above gate lines and data lines;
A thin film transistor arranged in each pixel area;
A first protective layer disposed on the gate line and the thin film transistor;
A pixel electrode disposed on the first protective layer in each pixel area;
A common electrode disposed on the first protective layer in each pixel area and in direct contact with the common electrode line and the outer edge of the display area; and
A transparent conductive layer disposed below the common voltage link line and extending integrally from the common electrode,
A display device in which the transparent conductive layer is in direct contact with the common voltage link line in the pad area and does not directly contact the common voltage link line in the display area and the pixel area. In the first paragraph, the common voltage link line is a display device made of copper. In the second paragraph, a display device in which the common voltage link line is formed integrally with the common electrode line. delete In the first paragraph, a display device in which the common electrode is composed of a transparent conductive layer. delete In the first paragraph,
A flexible film having one end attached to the above display panel; and
A display device further comprising a printed circuit board attached to the other end of the above flexible film. In the first paragraph, the display panel is a display device including a liquid crystal display panel, an organic electroluminescent display panel, a plasma display panel, or an electrophoretic display panel.

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