KR102747783B1 - Clock Data Recovery Device and Operation Method for Receiver of Wireless Optical Communication - Google Patents

Abstract

The present invention relates to a clock data recovery device for a wireless optical communication receiver. According to the present invention, the clock data recovery device includes: an amplifier which converts an input current into a voltage and converts a single analog signal into a differential analog signal; an analog equalizer which generates a data signal by removing ISI (Inter Symbol Interference) of the differential analog signal; and a clock data recovery device which samples the data signal, recovers the clock and data of the data signal, and outputs a recovered data signal, wherein the clock data recovery device recovers the clock and data based on the position of the rising edge of the clock signal corresponding to the phase of the data signal.

Description

Clock data recovery device and operation method for receiver of wireless optical communication {Clock data recovery device and operation method for receiver of wireless optical communication}

The present invention relates to a clock data recovery device and an operating method thereof for a wireless optical communication receiver in a wavelength division multiplexing (WDM) environment.

Wavelength Division Multiplexing (WDM) is an optical transmission system that assigns two or more channels distinguished by optical wavelengths to one optical waveguide. Specifically, in WDM wireless communication, two or more wired transmitters (TX _E ) output RF signals. The RF signals, which are electrical signals, are transmitted to a plurality of modulators (e.g., Mach-Zehnder Modulators, MZMs) and converted into optical signals. At this time, two or more optical signals having different wavelengths are combined into one signal through a PMOC (Polarization Maintaining Optical Coupler), so that two or more optical signals are transmitted through one channel.

And the above two or more optical signals are amplified by EDFA (Erbium-Doped Fiber Amplifiers) equipment and then transmitted to a wireless receiver (R _X ) through a wireless channel. Then, optical signals of different specific wavelengths are separated from the two or more optical signals transmitted to the wireless receiver by a WDM demultiplexer (Demux). Here, the WDM demultiplexer separates an optical signal of a specific wavelength from multiple wavelengths by utilizing the fact that each wavelength of light has a different refractive index.

Then, in order to extract the modulated data, the separated optical signal is converted into an electrical signal by a photo detector (PD). Then, the data converted into an electrical signal is converted from an analog signal to a digital signal through a wired receiver (RX _E ).

Here, the converted electrical signal has an unstable data phase due to the path of the light that varies depending on each wavelength. An electrical signal with an unstable data phase has the problem that it cannot guarantee the best sampling voltage margin in a wired receiver.

In other words, the main causes of inter-symbol interference (ISI) are the modulator that converts RF signals into optical signals, the long-distance wireless channel, and the optical detector that changes the optical signals into electrical signals. In the case of compensating for ISI, the receiver can have a bit error rate (BER) of 10-12 or less.

Therefore, in order to ensure the best sampling voltage margin, a wired receiver that converts an analog signal into a digital signal must have a clock and data recovery circuit (CDR). In other words, a high-performance equalizer capable of compensating for the ISI of a transmitter and receiver and a receiver including the same are required.

Korean Registered Patent No. 10-2132437

The present invention provides a clock data recovery device for a wireless optical communication receiver and an operating method thereof.

As an embodiment of the present invention, a wireless optical communication receiver clock data recovery device is provided, including: an amplifier for converting an input current into a voltage and converting a single analog signal (RF) into a differential analog signal (RF1, RF2); an analog equalizer for generating data signals (IN _P , IN _N ) by removing ISI (Inter Symbol Interference) of the differential analog signal; and a clock data recovery unit for sampling the data signal, restoring the clock and data of the data signal, and outputting restored data signals (RD1, RD2), wherein the clock data recovery unit recovers the clock and data based on the position of a rising edge of a clock signal corresponding to a phase of the data signal.

And as an embodiment of the present invention, the present invention provides an analog equalizer including a continuous-time linear equalizer (CTLE) which receives the differential analog signal (RF1, RF2) which is an output signal of the amplifier and removes the ISI, a first amplifier into which the differential analog signal with the ISI removed is input, a second amplifier which is connected in series with the first amplifier and has an output signal of the first amplifier input thereto and outputs the data signal (IN _P , IN _N ) based on the fed-back output signal of the continuous-time linear equalizer, a low-level amplifier into which a low-level band output signal of the first amplifier is input, and a gain controller (Gain Controller, Gc) which receives an output signal of the low-level amplifier and feeds back an output signal of the continuous-time linear equalizer, wherein the gain controller determines a damping factor of the analog equalizer and controls a frequency bandwidth of the analog equalizer.

And as an embodiment of the present invention, the clock data recovery unit including a sampler which samples the data signal in response to the clock signal and outputs the recovered data signal in which the clock and data are recovered, a plurality of integrators which generate a difference between output voltages at both ends according to the position of a rising edge of the clock signal corresponding to the phase of the data signal, a voltage-current converter (VI Converter) which converts a voltage corresponding to a difference value between the output voltages at both ends of the plurality of integrators into a current, a voltage controlled oscillator (VCO) which controls the frequency of an output signal according to an input voltage corresponding to the converted current and generates the clock signal based on the frequency, and a buffer which transmits the clock signal to the plurality of integrators.

In addition, in another embodiment of the present invention, a method for operating a clock data recovery device of a wireless optical communication receiver is provided, including a step of an amplifier converting an input current into a voltage and converting a single analog signal into a differential analog signal, a step of an analog equalizer removing ISI (Inter Symbol Interference) of the differential analog signal to generate a data signal, and a step of a clock data recovery unit sampling the data signal, recovering the clock and data of the data signal, and outputting a recovered data signal, wherein the clock data recovery unit recovers the clock and data based on a position of a rising edge of the clock signal corresponding to a phase of the data signal.

In another embodiment of the present invention, the step of removing ISI of the differential analog signal by the analog equalizer to generate the data signal may include the step of a continuous-time linear equalizer (CTLE) receiving the differential analog signal, which is an output signal of the amplifier, and removing the ISI, the step of inputting the differential analog signal with the ISI removed to a first amplifier, the step of inputting the output signal of the first amplifier to a second amplifier connected in series with the first amplifier, the step of inputting a low-level band output signal of the first amplifier to a low-level amplifier, the step of a gain controller (Gc) receiving the output signal of the low-level amplifier and feeding back the output signal of the continuous-time linear equalizer, and the step of the second amplifier outputting the data signal based on the fed-back output signal of the continuous-time linear equalizer, wherein the gain controller determines a damping factor of the analog equalizer and controls a frequency bandwidth of the analog equalizer.

In another embodiment of the present invention, the step of the clock data recovery unit restoring the clock and data of the data signal and outputting the restored data signal may include the step of a sampler sampling the data signal in response to the clock signal, the step of generating a difference between the output voltages of a plurality of integrators according to the position of a rising edge of the clock signal corresponding to the phase of the data signal, the step of a voltage-current converter (VI Converter) converting a voltage corresponding to the difference between the output voltages of the plurality of integrators into a current, the step of a voltage controlled oscillator (VCO) controlling the frequency of an output signal according to an input voltage corresponding to the converted current and generating the clock signal based on the frequency, the step of a buffer inputting the clock signal to the plurality of integrators, and the step of the sampler outputting the restored data signal in which the clock and data are restored based on the clock signals received from the plurality of integrators.

A clock data recovery device and an operating method of a wireless optical communication receiver, which are embodiments of the present invention, can compensate for ISI occurring in a wavelength division multiplexing environment.

Figure 1 is a block diagram of a wireless optical communication receiver clock data recovery device (10) according to an embodiment of the present invention.
Figure 2 is a circuit diagram of an amplifier (100) according to one embodiment of the present invention.
Figure 3 is a circuit diagram of an analog equalizer (200) according to one embodiment of the present invention.
FIG. 4a is an example of a circuit diagram for a continuous-time linear equalizer (210) of an analog equalizer (200), FIG. 4b is a graph of a gain according to a frequency of a transfer function of a continuous-time linear equalizer (210) circuit, FIG. 4c is an example of a circuit diagram for an amplifier (220, 230, 240) of an analog equalizer (200), and FIG. 4d is an example of a circuit diagram for a gain controller (250) of an analog equalizer (200).
Figure 5 is a circuit diagram of a clock data recovery unit (300) according to one embodiment of the present invention.
Fig. 6 is an example of a circuit diagram for an integrator (320) of a clock data recovery unit (300).
FIGS. 7A to 7C are examples of output voltages across multiple integrators (320) according to the rising edge position (center, left, right) of the clock signal based on the phase of the digital signal.
Figure 8 is a circuit diagram of a clock data recovery unit (300) according to another embodiment of the present invention.
FIG. 9a is an example of a circuit diagram of a clock data recovery unit (300) according to another embodiment of the present invention, and FIG. 9b is a graph of an enable signal (EN) according to an output voltage of an SR latch (312) of the clock data recovery unit (300).
Figure 10 is an output voltage experimental data for a wireless optical communication receiver depending on the presence or absence of a clock data recovery unit (300) according to one embodiment of the present invention.
FIG. 11 is a flowchart of an operation method of a clock data recovery device (10) of a wireless optical communication receiver according to one embodiment of the present invention.
Figure 12 is a flowchart of an operation method of an analog equalizer (200) according to one embodiment of the present invention.
Figure 13 is a flowchart of an operation method of a clock data recovery unit (300) according to one embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the attached drawings in order to explain the technical idea of the present invention in detail to a level where a person having ordinary skill in the art can easily implement the present invention.

Figure 1 is a block diagram of a clock data recovery device (10) of a wireless optical communication receiver according to an embodiment of the present invention.

Referring to FIG. 1, a clock data recovery device (10) of a wireless optical communication receiver may include an amplifier (100), an analog equalizer (200), and a clock data recovery unit (300).

The amplifier (100) can convert input current into voltage and can convert a single analog signal (RF) into a differential analog signal (RF1, RF2). A detailed description will be given with reference to Fig. 2. Here, the differential analog signal (RF1, RF2) may include ISI, and the differential analog signal (RF1, RF2) may be transmitted to an analog equalizer (200) to remove the ISI.

Figure 2 is a circuit diagram of an amplifier (100) according to one embodiment of the present invention.

Referring to FIG. 2, the amplifier unit (100) may include a trans-impedance (110) amplifier and a single-to-differential (S2D, Single-to-Differential, 120) amplifier.

The transimpedance amplifier (110) can convert the input current, which is the output current (I _PD ) of the photodetector (1), into a voltage (V _IN ).

A single-differential amplifier (S2D, 120) connected in series with a transimpedance amplifier (110) can convert the single analog signal (V _IN ), which is an output signal of the transimpedance, into a differential analog signal (RF1, RF2).

As illustrated in FIG. 2, the amplifier (100) may additionally include various types of amplifiers in addition to the amplifiers described above, depending on the received signal.

An analog equalizer (200) can generate data signals (IN _P , IN _N ) by removing ISI (Inter Symbol Interference) of differential analog signals (RF1, RF2). A detailed description will be provided with reference to FIG. 3.

Figure 3 is a circuit diagram of an analog equalizer (200) according to one embodiment of the present invention.

Referring to FIG. 3, the analog equalizer (200) may include a continuous time linear equalizer (CTLE, 210), a first amplifier (AMP1, 220), a second amplifier (AMP2, 230), a low level amplifier (AMP _LBW , 240), and a gain controller (250).

Here, the gain according to the transfer function of the analog equalizer (200) is as shown in the following mathematical expression 1.

H _IN (s) is an input transfer function, H _OUT (s) is an output transfer function, H _C (s) is a transfer function of a continuous-time linear equalizer (210), Gc is a control gain value of a gain controller (250), H _H (s) is a transfer function of the first and second amplifiers (220, 230), and H _L (s) is a transfer function of a low-level amplifier (240).

Here, when the control gain value Gc of the analog equalizer (200) increases, the analog equalizer (200) operates in the same manner as a second-order complex system, generating a complex pole and making the damping ratio approach 0. Therefore, the system becomes unstable as the gain and damping ratio of the analog equalizer (200) ultimately decrease, but the inter-symbol interference removal performance of the analog equalizer (200) can be improved.

FIG. 4a is an example of a circuit diagram for a continuous-time linear equalizer (CTLE, 210) of an analog equalizer (200).

Referring to FIG. 4a, a continuous-time linear equalizer (210) can receive the differential analog signal (RF1, RF2), which is an output signal of an amplifier (100), and remove the ISI.

A continuous-time linear equalizer (210) may be composed of three resistors (two R _D , one R _S ), a capacitor (C _S ), and two MOSFETs (N ₁ , N ₂ ). Specifically, the capacitor C _S and the resistor R _S may be connected in parallel, and two MOSFETs (N ₁ , N ₂ ) may be connected in parallel to each end of the capacitor C _S and the resistor R _S . In addition, two resistors R _D connected in series may be connected between the series-connected MOSFETs (N ₁ , N ₂ ).

Here, the transfer function of the continuous-time linear equalizer (210) circuit is as shown in mathematical expression 2.

Here, g _m1,2 is the transconductance (gm) of the MOSFET (N ₁ , N ₂ ) and C _L is the load capacitor (C _L ) of the continuous-time linear equalizer (210).

Figure 4b is a graph of the gain according to frequency of the transfer function of a continuous-time linear equalizer (210) circuit.

Referring to Fig. 4b and mathematical expression 2, ω _z is the zero frequency of the molecule, and ω _p1 is The frequency of the denominator's pole 1, ω _p2 is the frequency of the denominator's pole 2. Specifically, a gain difference occurs between the frequency before the zero point and the frequency after the zero point based on one zero point of the numerator, and the two poles of the denominator can generate a peak gain at the operating frequency to eliminate ISI.

And the first amplifier (220) can input a differential analog signal (RF1, RF2) from which ISI has been removed from a continuous-time linear equalizer (CTLE, 210). The second amplifier (230) is connected in series with the first amplifier (220) and can input an output signal of the first amplifier (220). In addition, the second amplifier (230) can output the data signal (IN _P , IN _N ) based on the output signal of the continuous-time linear equalizer (210) that has received feedback.

And the low-level amplifier (240) can receive the low-level band output signal of the first amplifier (220).

Fig. 4b is an example of a circuit diagram for amplifiers (220, 230, 240) of an analog equalizer (200).

Referring to FIG. 4b, the amplifiers (220, 230, 240) of the analog equalizer (200) can be identically configured with one resistor (R _D ) and two MOSFETs (N ₁ , N ₂ ). Here, two resistors R _D connected in series can be connected between the series-connected MOSFETs (N ₁ , N ₂ ).

Here, the resistance R _D value of the low-level amplifier (240) can be configured to be 10 times larger than the resistance R _D values of the first and second amplifiers (220, 230).

The transfer function of the amplifier (220, 230, 240) circuit of the analog equalizer (200) is as shown in mathematical expression 3.

Here, g _m is the transconductance (gm) of the MOSFETs (N ₁ , N ₂ ), and C _L is the load capacitor (C _L ) of the amplifiers (220, 230, 240). Therefore, the amplifiers (220, 230, 240) can maintain the same gain (g _m R _D ) up to one pole frequency in the denominator.

And the gain controller (Gc, 250) can receive the output signal (D _OUT ) of the low-level amplifier (240) and feed back the output signal (RF1, RF2) of the continuous-time linear equalizer (210). In addition, the gain controller (250) can determine the damping factor of the analog equalizer (200) and control the frequency bandwidth of the analog equalizer (200).

Fig. 4c is an example of a circuit diagram for a gain controller (Gc, 250).

Referring to FIG. 4c, the gain controller (250) may include a MOSFET (251) which is an amplifier of a complementary inverter structure and a switch (252) connected to both ends of the MOSFET (251, W _p , W _n ). In addition, the gain controller (250) may be configured as a plurality of circuit units by using two MOSFETs (251) of an inverter structure and a switch (252) connected to both ends of the MOSFET (251) as one unit circuit. The gain controller (250) may increase the control gain value Gc as the number of circuit units, that is, the number of switches (252), increases.

That is, the gain controller (250) can operate the switch (252) according to the binary digital bit (N _EQ ) output by the MOSFET (251 W _p , W _n ) and control the output (G _OUT ) of the gain controller (250).

For example, when the digital bit (N _EQ ) increases, the output (G _OUT ) of the gain controller (250) may increase. And the output (G _OUT ) of the gain controller (250) may reduce the output voltage (RF1, RF2) of the continuous-time linear equalizer (210) by a voltage corresponding to the increase in the digital bit ( _{N EQ} ).

And the output voltage (RF1, RF2) reduced by the gain controller (250) can be transmitted again to the second amplifier (230) through the first amplifier (220), and the data signal (IN _P , IN _N ), which is the output signal of the second amplifier (230), can be transmitted to the clock data recovery unit (300).

Here, parameter values based on the transfer function of the above-described continuous-time linear equalizer (210) circuit and the transfer function of the amplifier (220, 230, 240) circuit can be calculated. Then, the calculated parameter values can be substituted into mathematical expression 1 of the analog equalizer (200). Then, the output signal (G _OUT ) of the gain controller (250) can be changed by the operation result for mathematical expression 1, and the position of the pole can be changed by the output signal (G _OUT ).

That is, the analog equalizer (200) has a feedback characteristic, and the gain controller (250) that adjusts the gain can control the position of the pole of the second-order complex system.

The analog equalizer (200) according to the present invention is a second or higher order system, and the gain controller (250) can affect two second order complex equations. For example, when the output value (G _OUT ) of the gain controller (250) increases, the damping factor of one of the two second order complex equations can have a value of 0.9 or higher, and the damping constant of the other can approach 0. Here, the closer the damping constant is to 1, the more stable the high-order system of the analog equalizer (200) becomes, and the closer the damping constant is to 0, the more unstable the high-order system of the analog equalizer (200) becomes. The closer the damping constant is to 0, the more unstable the high-order system becomes, but a peaking gain occurs in the frequency response of the analog equalizer (200).

That is, the analog equalizer (200) according to the present invention can determine the attenuation constant of the analog equalizer (200) according to the output of the gain controller (250) and control the frequency bandwidth of the analog equalizer (200) based on the peak value gain.

In other words, the analog equalizer (200) can control the output of the gain controller (250) and change the attenuation constant of the second-order complex equation using the output value of the gain controller (250). If the attenuation constant is close to 0, a peak value gain may occur in the frequency response of the analog equalizer (200). The generated peak value gain can lower the DC gain of the analog equalizer (200) below the frequency response of the continuous-time linear equalizer (210). That is, the high-order system of the analog equalizer (200) is unstable, but the performance of the analog equalizer (200) can be improved.

For example, the analog equalizer (200) according to the present invention can compensate for a loss of 15 dB or more of the differential analog signal including ISI in a wireless optical communication receiver.

As described above, the clock data recovery device (10) of the wireless optical communication receiver, which is an embodiment of the present invention, can compensate for ISI occurring during a signal conversion process.

Referring back to FIG. 1, the clock data recovery unit (300) can sample the data signals (IN _P , IN _N ), recover the clock and data of the data signals, and output recovered data signals (RD1, RD2). Here, the clock data recovery unit (300) can recover the clock and data based on the position of the rising edge of the clock signal corresponding to the phase of the data signal.

Figure 5 is a circuit diagram of a clock data recovery unit (300) according to one embodiment of the present invention.

Referring to FIG. 5, the clock data recovery unit (300) may include a sampler (310), a plurality of integrators (320), a voltage-current converter (VI Converter, 330), a voltage controlled oscillator (340), a buffer (Buffer, 350), and a sample and hold (S/H) circuit (360).

Since the clock data recovery unit (300) operates only when the data signal (IN _P , IN _N ) changes from 0 to 1 or from 1 to 0, an Odd mode circuit and an Even mode circuit can be configured to confirm and compare the changes in the two cases described above.

Here, the sampler (310), multiple integrators (320) and sample hold circuit (360) of the clock data recovery unit (300) may be configured in Odd mode and Even mode, and each mode may include one sampler, one integrator and one sample fold circuit.

The sampler (310) can sample the data signals (IN _P , IN _N ) in response to the clock signal (CK) and output restored data signals (RD1, RD2) in which the clock and data are restored. Here, RD1 is a first restored data signal which is an output signal of the sampler (310) in Even mode, and RD2 is a second restored data signal which is an output signal of the sampler (310) in Odd mode.

And the sampler (310) may include a plurality of comparators (311) and a plurality of SR latches (312).

A plurality of comparators (311) can receive data signals (IN _P , IN _N ) and a clock signal (CK), which are output signals of an analog equalizer (200).

Here, the clock signal (CK) input to each of the plurality of comparators (311) may be a clock signal received from the buffer (350) in the same manner as the integrator (320).

Here, the clock signals (CK) input to each of the Even mode comparator (311) and the Odd mode comparator (311) may have opposite phases. And the clock signal (CK) may have half the frequency of the data signal (IN _P , IN _N ).

And the SR latch (312) can convert the output signal of the comparator (311) from an RZ (Return to Zero) signal to an NRZ (Non Return to Zero) signal.

The Even mode SR latch (312) can receive an output signal of the Even mode comparator (311) and output a first restoration data signal (RD1). And the Odd mode SR latch (312) can receive an output signal of the Odd mode comparator (311) and output a second restoration data signal (RD2).

Here, the first and second restored data signals (RD1, RD2) may be sampling signals having optimal clock phases for which data and clock are compensated.

Fig. 6 is an example of a circuit diagram for an integrator (320) of a clock data recovery unit (300).

Referring to FIG. 6, a plurality of integrators (320) may be composed of four MOSFETs and two capacitors (C _L ). Data signals (IN _P , IN _N ) may be input to two of the four MOSFETs, respectively, and a clock signal (CK) may be input to the remaining two MOSFETs.

For example, if the clock signal (CK) remains at 1, the output signal (OUT _P , OUT _N ), which is the output voltage across the integrator (320), can be 0 regardless of the data signal (IN _P , _IN N).

On the other hand, when the clock signal (CK) changes from 1 to 0, a difference in the output signals (OUT _P , OUT _N ) may also occur due to the difference in the voltage data signals (IN _P , IN _N ). That is, a difference occurs in the input current (I _INTEG ) input to each MOSFET due to the voltage difference across the integrator (320), and this may cause a voltage difference across the two capacitors (C _L ). Therefore, when the clock signal (CK) changes from 1 to 0, a difference may occur in the output signals (OUT _P , OUT _N ) across the integrator (320) depending on the difference in the data signals (IN _P , IN _N ).

Here, a difference between the output voltages of the two ends of the plurality of integrators (420) may occur depending on the position of the rising edge of the clock signal (CK) corresponding to the phase of the data signal (IN _P , _IN N).

The rising edge position of the clock signal (CK) can be estimated through the difference between the output voltages (OUT _P , OUT _N ) at both ends of the multiple integrators (420), and the clock data recovery unit (300) can correct the data signals (IN _P , IN _N ).

FIGS. 7A to 7C are examples of output voltages (OUT _P , OUT _N ) across multiple integrators (320) according to the rising edge position (center, left, right) of the clock signal (CK) based on the phase of the digital signal (IN _P , IN _N ).

Referring to FIG. 7a, the plurality of integrators (320) can control the output voltage based on the phase of the clock signal (CK ₀ , CK ₁₈₀ ) and the phase of the data signal (IN _P , IN _N ). Here, the clock signal (CK ₀ , CK ₁₈₀ ) can have a frequency that is half that of the data signal (IN _P , IN _N ). That is, the circuit of the plurality of integrators (320) can be configured based on two modes in which the data signal (IN _P , IN _N ) changes from 0 to 1 or from 1 to 0. In addition, in order to compare the data signals (IN _P , IN _N ) for the two modes at the phase of the same clock signal (CK ₀ , CK ₁₈₀ ), it may be desirable for the clock signals (CK ₀ , CK ₁₈₀ ) to have a frequency that is half that of the data signals (IN _P , IN _N ).

When the clock signal (CK) changes from 1 to 0 or from 0 to 1, the rising edge of the clock signal (CK) can be positioned at the phase center of the data signals (IN _P , IN _N ). As illustrated in FIG. 7a, since the phase margin is large when the rising edge of the clock signal (CK) is positioned at the phase center of the data signals (IN _P , IN _N ), it is desirable to restore the clock and data so that the rising edge of the clock signal (CK) is positioned at the center.

In other words, when the rising edge of the clock signal (CK) is located at the phase center of the data signals (IN _P , IN _N ), the output signals (OUT _P , OUT _N ) at both ends of the integrator (320) can have the same size, which can increase the phase margin.

On the other hand, referring to FIGS. 7b and 7c, the rising edge of the clock signal (CK) may be shifted to the left or right based on the phase of the data signals (IN _P , IN _N ). That is, when the clock signal (CK) changes from 1 to 0 or from 0 to 1, if the rising edge of the clock signal (CK) is shifted to the left or right based on the phase of the data signals (IN _P , IN _N ), the output signals (OUT _P , OUT _N ) at both ends of the integrator (320) may have different sizes.

As shown in Fig. 7b, the rising edge of the clock signal (CK) may be positioned to the left of the center of the phase of the data signal (IN _P , IN _N ). And when the clock signal (CK) changes from 0 to 1, the output signal OUT _P of the integrator (320) is the output signal OUT can be greater than _N.

On the other hand, as shown in Fig. 7c, the rising edge of the clock signal (CK) may be positioned to the right of the center of the phase of the input signals (IN _P , IN _N ). And when the clock signal (CK) changes from 0 to 1, the output signal OUT _P of the integrator (320) is the output signal OUT may be less than _N.

As described above, the plurality of integrators (320) of the clock data recovery unit (300) according to the present invention generate output signals (OUT _P , OUT _N ) linearly according to the phase of the clock signal (CK), and thus can generate lower clock jitter compared to a conventional clock and data recovery circuit (CDR) that outputs only digital signals 1 and 0.

Here, the difference between the output signals (OUT _P , OUT _N ) may increase as the rising edge of the clock signal (CK) moves away from the center based on the phase of the data signals (IN _P , IN _N ). Therefore, the clock data recovery unit (300) may be designed to restore the clock and data only when the rising edge of the clock signal (CK) moves away from the center position based on the difference between the output signals (OUT _P , OUT _N ) at both ends of the integrator (420).

Referring again to FIG. 5, the voltage-to-current converter (330) can convert the voltage corresponding to the difference between the output voltages across the multiple integrators (320) into current.

For example, the voltage-current converter (330) may not perform a conversion operation when the output voltages (OUT _P , OUT _N ) across multiple integrators (420), i.e., the Odd mode integrator (320), are the same and the output voltages (OUT _P , OUT _N ) across the Even mode integrator (320) are the same.

On the other hand, when the output voltages (OUT _P , OUT _N ) at both ends of the Odd mode integrator (320) are different or when the output voltages (OUT _P , OUT _N ) at both ends of the Even mode integrator (320) are different, the voltage-current converter (330) can generate an enable (EN) signal to perform a conversion operation. Here, the EN signal can be generated corresponding to each of the Even mode and the Odd mode.

And the voltage-current converter (330) can convert a current corresponding to the difference value of the output voltage, and can apply an input voltage (V _LPF ) corresponding to the converted current to the voltage controlled oscillator (340).

In other words, if the output voltages (OUT _P , OUT _N ) across each integrator (320) are different, the EN signal can be generated as 1, and the EN signal can be applied to the voltage-to-current converter (330). Depending on the difference in the output voltages (OUT _P , OUT _N ) across the integrator (320) input to the voltage-to-current converter (330), a difference may also occur in the current flowing across the two ends. Then, an increase or decrease in the input voltage (V _LPF ) can be determined according to the difference in the current flowing across the integrator (320).

That is, it is possible to determine whether to increase or decrease the input voltage (V _LPF ) of the voltage controlled oscillator (340) based on the current converted by the voltage-current converter (330).

For example, when the output voltage OUT _P is greater than the output voltage OUT _N , the current applied to one end of the voltage-current converter (330) into which the output voltage OUT _P is input may be greater than the current applied to the other end of the voltage-current converter (330) into which the output voltage OUT _N is input. The input voltage (V _LPF ) applied to the voltage-controlled oscillator (340) may increase or decrease based on the difference value of the currents applied to both ends of the voltage-current converter (330).

Therefore, the input voltage (V _LPF ) applied to the voltage controlled oscillator (340) can be controlled according to the output voltages of the plurality of integrators (320).

A voltage controlled oscillator (340) can control the frequency of an output signal according to an input voltage (V _LPF ) corresponding to the converted current, and generate a clock signal (CK ₀ , CK ₁₈₀ ) based on the frequency.

For example, the output signal OUT _P of multiple integrators (320) is the output signal If the current is smaller than OUT _N , the input voltage (V _LPF ) of the voltage-controlled oscillator (340) may decrease if the current has a negative value. On the other hand, the output signal OUT _P of the plurality of integrators (320) is the output signal When it is greater than OUT _N , the current has a positive value and the input voltage (V _LPF ) may increase. Here, when the input voltage (V _LPF ) decreases, the output signal frequency of the voltage controlled oscillator (340) may decrease, and when the input voltage (V _LPF ) increases, the output signal frequency of the voltage controlled oscillator (340) may increase.

Therefore, the voltage controlled oscillator (340) can determine the size of the input voltage (V _LPF ) and the frequency of the output signal of the voltage controlled oscillator (340) based on the difference between the output voltages at both ends of the plurality of integrators (320).

And the buffer (350) can transmit clock signals (CK ₀ , CK ₁₈₀ ) to multiple integrators (320). And the multiple comparators (311) can receive the same clock signals (CK ₀ , CK ₁₈₀ ) as the multiple integrators (320) and transmit them to the SR latch (312).

Therefore, the sampler (310) can output the restored data signals (RD1, RD2) by the clock signals (CK ₀ , CK ₁₈₀ ). Here, the restored data signals (RD1, RD2) can be digital signals sampled with ISI compensated.

And the sample and hold circuit (360, S/H) is positioned between the plurality of integrators (320) and the voltage-current converter (330) and can store the output voltages of each of the plurality of integrators (320). For example, if a switch (not shown) is configured between the plurality of integrators (320) and the sample and hold circuit (360, S/H), when the connection between the plurality of integrators (320) and the sample and hold circuit (360, S/H) is disconnected, the output voltages of the plurality of integrators (320) can be stored in the sample and hold circuit (360, S/H).

And, based on the phase of the data signal (IN _P , IN _N ), if the rising edge of the clock signal (CK ₀ , CK ₁₈₀ ) transmitted from the buffer (350) is located at the center of the phase of the data signal (IN _P , IN _N ), the clock data recovery unit (300) can convert the data signal (IN _P , IN _N ) and output the recovery data signal (RD1, RD2).

That is, the sampler (310) can output restored data signals (RD1, RD2) by restoring the clock and data so that the rising edge of the clock signal ( _CK ) is positioned at the phase center of the data signals (IN _P , IN N).

Figure 8 is a circuit diagram of a clock data recovery unit (300) according to another embodiment of the present invention.

Referring to FIG. 8, the clock data recovery unit (300) may include a sampler (310), a plurality of integrators (320), a voltage-current converter (330), a voltage controlled oscillator (340), a buffer (350), and a plurality of switches (370).

Here, the sampler (310), multiple integrators (320), voltage-current converter (330), voltage controlled oscillator (340), and buffer (350) are the same as those described in FIGS. 5, 6, and 7a to 7c described above.

A plurality of SR latches (312) and a plurality of switches (370) can be connected between a plurality of comparators (311) and a voltage-current converter (330).

Here, the sampler (310), multiple integrators (320) and multiple switches (370) of the clock data recovery unit (300) can be configured in Odd mode and Even mode, and each mode can include one sampler, one integrator and two switches.

And a plurality of SR latches (312) can control the on/off operation of a plurality of switches (370) based on the NRZ signal, which is an output voltage. Here, the SR latches (312) can convert the output signal of the comparator (311) from an RZ signal to an NRZ signal.

And the signals input to the plurality of comparators (311) may be a clock signal (CK ₀ ) transmitted from a buffer (350) and a data signal (IN _P , IN _N ) input from an analog equalizer (200). Here, the clock signal (CK ₀ , CK ₁₈₀ ) transmitted from the buffer (350) may pass through an integrator (320) and be directly transmitted to the comparator (311).

FIG. 9a is an example of a circuit diagram of a clock data recovery unit (300) according to another embodiment of the present invention.

Referring to FIG. 9a, the Odd mode SR latch (312) can control the on/off operation for two switches (370) connected to the Even mode comparator (311). On the other hand, the Even mode SR latch (312) can control the on/off operation for two switches (370) connected to the Odd mode comparator (311).

For example, if the output voltage of the Odd mode SR latch (312) and the output voltage of the Even mode comparator (311) are the same, the Odd mode SR latch (312) can turn off the two switches (370) in the Even mode. On the other hand, if the output voltage of the Odd mode SR latch (312) and the output voltage of the Even mode comparator (311) are different, that is, if the clock signal (CK) of the Odd mode SR latch (312) changes from 0 to 1 or from 1 to 0, the two switches (370) in the Even mode can be turned on.

On the other hand, if the output voltage of the Even mode SR latch (312) and the output voltage of the Odd mode comparator (311) are the same, the Even mode SR latch (312) can turn off the two switches (370) in the Odd mode. On the other hand, if the output voltage of the Even mode SR latch (312) and the output voltage of the Odd mode comparator (311) are different, that is, if the clock signal (CK) changes from 0 to 1 or from 1 to 0, the two switches (370) in the Even mode can be turned on.

Therefore, the operation of the voltage-current converter (330) can be controlled by turning on the switch (370) only when the output voltage of the comparator (311) and the output voltage of the SR latch (312) are different, that is, only when the clock signal (CK) changes from 0 to 1 or from 1 to 0.

Here, two Odd mode switches can control the generation of enable signals EN _C and EN _D of the voltage-to-current converter (330), and two Even mode switches can control the generation of enable signals EN _A and EN _B of the voltage-to-current converter (330). For example, the enable signal EN _A can be generated when the clock signal (CK) of the Odd mode comparator (311) changes from 1 to 0, and EN _B can be generated when the clock signal (CK) of the Odd mode comparator (311) changes from 0 to 1. On the other hand, the enable signal EN _C can be generated when the clock signal (CK) of the Even mode comparator (311) changes from 1 to 0, and EN _d can be generated when the clock signal (CK) of the Even mode comparator (311) changes from 0 to 1.

Therefore, when the output signal of the Even mode SR latch (312) that receives the output signal of the Even mode comparator (311) and the output signal of the Odd mode SR latch (312) that receives the output signal of the Odd mode comparator (311) are different, the enable signal (EN _A , EN _B , It can be seen that EN _C , EN _D ) were created.

Figure 9b is a graph of an enable (EN) signal according to the output voltage of the SR latch (312) of the clock data recovery unit (300).

Referring to Fig. 9b, when the output voltages of the SR latch (312) in Even mode and Odd mode are different, the voltage-current converter (330) outputs an enable signal (EN _A , EN _B , EN _C , EN _D ) can be generated from 0 to 1. For example, when the output voltage of the Odd mode SR latch (312) and the output voltage of the Even mode SR latch (312) are the same, the voltage-current converter (330) can generate the enable signal (EN _A , EN _B , EN _C , EN _D ) can be 0. On the other hand, when the output voltage of the Odd mode SR latch (312) and the output voltage of the Even mode SR latch (312) are different, the enable signal (EN _A , EN _B , EN _C , EN _D ) can be generated as 1.

Specifically, if the output voltage of the Odd mode SR latch (312) is 1 and the output voltage of the Even mode SR latch (312) is 0, the EN _C and EN _D signals can be generated as 1. On the other hand, if the output voltage of the Even mode SR latch (312) is 1 and the output voltage of the Odd mode SR latch (312) is 0, the EN _A and EN _B signals can be generated as 1.

In other words, the voltage-current converter (330) may not operate even when the output voltage of the Odd mode comparator (311) and the output voltage of the Even mode comparator (311) are the same. On the other hand, when the output voltage of the Odd mode comparator (311) and the output voltage of the Even mode comparator (311) are different, the voltage-current converter (330) may not operate when the enable signal (EN _A , EN _B , It is possible to generate EN _C , EN _D ) and perform conversion operations.

And when the output voltages (OUT _P , OUT _N ) at both ends of the Odd mode or Even mode integrator (320) are the same, the enable signal (EN _A , EN _B , Even if EN _C , EN _D ) are generated, the output voltages (OUT _P , OUT _N ) at both ends of the integrator (320) can be the same. Therefore, the voltage-current converter (330) can maintain a constant voltage (V _LPF ) because no increase or decrease in current occurs.

On the other hand, when the output voltages (OUT _P , OUT _N ) at both ends of the Odd mode integrator (320) are different or when the output voltages (OUT _P , OUT _N ) at both ends of the Even mode integrator (320) are different, the enable signal (EN _A , EN _B , When EN _C , EN _D ) are generated, the current in the voltage-current converter (330) can be increased or decreased by the difference between the output voltages (OUT _P , OUT _N ) at both ends of the integrator (320). Accordingly, the input voltage (V _LPF ) of the voltage controlled oscillator (VCO, 340) can be increased or decreased in response to the increase or decrease in the current.

As described above, the clock data recovery unit (300) is designed to operate the voltage-current converter (330) only when the data signals (IN _P , IN _N ) require correction, thereby enabling efficient clock and data recovery. In addition, the clock data recovery unit (300) generates a clock at an optimal sampling signal position, thereby increasing the voltage margin and having a low bit error rate.

Figure 10 shows output voltage experimental data for a wireless optical communication receiver depending on the presence or absence of a clock data recovery unit (300) according to an embodiment of the present invention.

Referring to FIG. 10, the output eye diagram of a wireless optical communication receiver (prior art) excluding the clock data recovery unit (400) and the output eye diagram of the clock data recovery device (10) of the wireless optical communication receiver according to the embodiment of the present invention can be compared.

As illustrated in FIG. 10, it can be seen that a sampling clock phase restored to the center of input data (IN _P , IN _N ) of a clock data recovery device (10) of a wireless optical communication receiver according to an embodiment of the present invention is generated.

The clock data recovery unit (300) according to the present invention has high efficiency in terms of structure because it requires only two additional integrators, unlike the conventional oversampling CDR or baud rate CDR. Specifically, the oversampling CDR must add a clock phase and requires two comparators, and the baud rate CDR must add a reference voltage and requires two comparators. On the other hand, the clock data recovery unit (400) according to the present invention does not require additional hardware other than two integrators, so the structure can be simplified.

That is, the clock data recovery device (10) of the wireless optical communication receiver, which is an embodiment of the present invention, can compensate for ISI occurring in a wavelength division multiplexing environment.

In other words, even if the phase of the initial sampling clock deviates from the center of the data signal, the phase of the sampling clock can be generated at the center of the data signal by the output signal of the clock data recovery unit (400).

Therefore, the clock data recovery device (10) of the wireless optical communication receiver generates a clock at an optimal sampling signal position, thereby increasing the voltage margin and having a low bit error rate.

FIG. 11 is a flowchart of a method for operating a clock data recovery device of a wireless optical communication receiver according to one embodiment of the present invention.

Referring to FIG. 11, the operating method of the clock data recovery device (10) of the wireless optical communication receiver may include steps S1100 to S1400.

At step S1100, the amplifier (100) can convert the input current into voltage and convert a single analog signal into a differential analog signal. Here, the amplifier (100) is as described in FIG. 1 and FIG. 2 described above.

At step S1200, the analog equalizer (200) can remove the ISI of the differential analog signal and generate a data signal. Here, the analog equalizer (200) is as described in FIG. 1, FIG. 3, and FIG. 4 described above.

At step S1300, the clock data recovery unit (300) samples the data signal and operates the clock data recovery unit (300) according to the position of the rising edge of the clock signal corresponding to the phase of the sampled data signal.

At step S1300, the clock data recovery unit (300) can output a recovery data signal that has recovered the clock and data of the data signal. Here, the clock data recovery unit (300) is as described in FIG. 1, FIG. 5 to FIG. 8, FIG. 9a, and FIG. 9b described above.

Figure 12 is a flowchart of an operation method of an analog equalizer (200) according to one embodiment of the present invention.

Referring to FIG. 12, the operating method of the analog equalizer (200) may include steps S1210 to S1270.

At step S1210, a continuous-time linear equalizer (210, CTLE) can receive the differential analog signal, which is the output signal of the amplifier (100), and remove ISI.

At step S1220, a continuous-time linear equalizer (210, CTLE) can input the differential analog signal with the ISI removed to the first amplifier (220).

At step S1230, the output signal of the first amplifier (220) can be input to the second amplifier (230) connected in series with the first amplifier (220).

At step S1240, the low-level band output signal of the first amplifier (220) can be input to the low-level amplifier (240).

At step S1250, the gain controller (250) can feed back the output signal of the continuous-time linear equalizer (210, CTLE) according to the output signal of the low-level amplifier (240).

At step S1260, the first amplifier (220) can receive the output signal of the fed-back continuous-time linear equalizer (210, CTLE) and transmit it to the second amplifier (230).

At step S1270, the second amplifier (230) can output a data signal which is a differential analog signal with ISI removed.

Figure 13 is a flowchart of an operation method of a clock data recovery unit (300) according to one embodiment of the present invention.

Referring to FIG. 13, the operation method of the clock data recovery unit (300) may include steps S1310 to S1380.

At step S1310, the sampler (310) can sample the data signal in response to the clock signal.

At step S1320, a difference between the output voltages across the multiple integrators (320) may occur depending on the position of the rising edge of the clock signal corresponding to the phase of the data signal.

At step S1330, a voltage-current converter (330, VI Converter) can convert the voltage for the difference between the output voltages across multiple integrators (320) into current.

At step S1340, a voltage controlled oscillator (340, VCO) can control the frequency of an output signal according to an input voltage corresponding to the converted current.

At step S1350, a voltage controlled oscillator (340, VCO) can generate the clock signal based on the frequency.

At step S1360, the buffer (350) can input the clock signal to multiple integrators (320).

At step S1360, multiple integrators (320) can input clock signals to the sampler (310).

At step S1380, the sampler (310) can output the restored data signal in which the clock and data are restored based on the input clock signal.

The operating method of a clock data recovery device (10) of a wireless optical communication receiver, which is an embodiment of the present invention, can compensate for ISI occurring in a wavelength division multiplexing environment.

In other words, even if the phase of the initial sampling clock deviates from the center of the data, the phase of the sampling clock can be generated at the center of the data by the output signal of the clock data recovery unit (400).

Therefore, the operating method of the clock data recovery device (10) of the wireless optical communication receiver generates a clock at an optimal sampling signal position, thereby increasing the voltage margin and having a low bit error rate.

The above-described contents are specific embodiments for carrying out the present invention. In addition to the above-described embodiments, the present invention will also include embodiments that can be simply designed or easily changed. In addition, the present invention will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims described below as well as the equivalents of the claims of this invention.

10: Clock data recovery device for wireless optical communication receiver
100 : Amplifier
110: Transimpedance amplifier 120: Single-differential amplifier
200 : Analog Equalizer
210: Continuous time linear equalizer 220: First amplifier
230: Second amplifier 240: Low level amplifier
250 : Gain Controller
251 : MOSFET 252 : Switch
300 : Clock data recovery unit
310 : Sampler
311: Multiple comparators 312: Multiple SR latches
320: Multiple Integrators 330: Voltage-Current Converters
340 : Voltage Controlled Oscillator 350 : Buffer
360: Sample hold circuit 370: Multiple switches
20 : Photodetector

Claims (15)

An amplifier section that converts input current into voltage and converts a single analog signal (RF) into differential analog signals (RF1, RF2);
An analog equalizer that removes ISI (Inter Symbol Interference) of the differential analog signal to generate data signals (IN _P , IN _N ); and
A clock data restoration unit for sampling the above data signal, restoring the clock and data of the above data signal, and outputting a restored data signal (RD1, RD2);
The above analog equalizer,
A continuous time linear equalizer (CTLE) that receives the differential analog signal (RF1, RF2), which is an output signal of the above amplifier, and removes the ISI;
A first amplifier into which the differential analog signal from which the ISI has been removed is input;
A second amplifier connected in series with the first amplifier, receiving an output signal of the first amplifier and outputting the data signal (IN _P , IN _N ) based on an output signal of the continuous-time linear equalizer that has been fed back;
A low-level amplifier into which the low-level band output signal of the first amplifier is input; and
It includes a gain controller (Gc) that receives the output signal of the low-level amplifier and feeds back the output signal of the continuous-time linear equalizer;
The above gain controller,
Determine the damping factor of the above analog equalizer and control the frequency bandwidth of the above analog equalizer,
The above clock data restoration unit,
A clock data recovery device for a wireless optical communication receiver, which recovers clock and data based on the position of the rising edge of a clock signal corresponding to the phase of the above data signal.
In the first paragraph,
The above amplifier part,
A trans-impedence amplifier that converts the input current, which is the output current of the photodetector, into voltage; and
A clock data recovery device for a wireless optical communication receiver, comprising a single-to-differential (S2D) amplifier that converts the single analog signal, which is an output signal of the transimpedance, into the differential analog signal (RF1, RF2).
delete In the first paragraph,
The above gain controller,
A complementary-connected inverter-structured amplifier, comprising a MOSFET and a switch connected to both ends of the MOSFET,
A clock data recovery device for a wireless optical communication receiver, which controls the operation of the switch according to the binary digital bit output by the above MOSFET and reduces the output voltage of the continuous-time linear equalizer by an amount increased in response to an increase in the digital bit.
In the first paragraph,
The above clock data restoration unit,
A sampler for sampling the data signal in response to the clock signal and outputting the restored data signal in which the clock and data are restored;
A plurality of integrators, each of which generates a difference between output voltages at both ends according to the position of the rising edge of the clock signal corresponding to the phase of the data signal;
A voltage-to-current converter (VI Converter) that converts the voltage difference between the output voltages of the plurality of integrators into current;
A voltage controlled oscillator (VCO) that controls the frequency of an output signal according to an input voltage corresponding to the converted current and generates the clock signal based on the frequency; and
A clock data recovery device for a wireless optical communication receiver, comprising a buffer for transmitting the clock signal to the plurality of integrators.
In paragraph 5,
The above clock data restoration unit,
A clock data recovery device for a wireless optical communication receiver, further comprising a sample and hold circuit for storing the output voltage of each of the plurality of integrators.
In paragraph 5,
The above sampler,
A plurality of comparators receiving the above data signal and the above clock signal; and
A plurality of SR latches that receive output signals of the plurality of comparators and output the restoration data signals;
A clock data recovery device for a wireless optical communication receiver, wherein the clock signals input to each of the plurality of comparators have opposite phases, and the clock signals have a frequency of half that of the data signal.
In paragraph 5,
The above multiple integrators are,
When the rising edge of the clock signal is located at the center based on the phase of the data signal, the output voltages at both ends of the plurality of integrators are the same,
A clock data recovery device for a wireless optical communication receiver, wherein a difference occurs in the output voltages of the multiple integrators when the rising edge of the clock signal is shifted from the center based on the phase of the data signal.
In Article 8,
The above voltage-current converter,
If the output voltages at both ends of the input multiple integrators are the same, the conversion operation does not occur.
A clock data recovery device for a wireless optical communication receiver, which generates an enable signal to perform a conversion operation when the output voltages of the input plurality of integrators are different, and transmits the converted current to the voltage controlled oscillator.
In Article 9,
If the rising edge of the clock signal transmitted from the buffer is located at the center based on the phase of the data signal,
A clock data recovery device of a wireless optical communication receiver, wherein the sampler converts the data signal and outputs the recovery data signal.
In Article 7,
The above clock data restoration unit,
Further comprising a plurality of switches connecting between the sampler and the voltage-current converter;
If the output voltages of the above plurality of comparators and the output voltages of the above plurality of SR latches are the same, the above plurality of switches are turned off,
A clock data recovery device for a wireless optical communication receiver, which turns on the plurality of switches and generates an enable signal when the output voltages of the plurality of comparators and the output voltages of the plurality of SR latches are different, thereby controlling the operation of the voltage-current converter.
In Article 11,
A clock data recovery device for a wireless optical communication receiver, wherein an input voltage of the voltage controlled oscillator is generated based on the enable signal.
In the method of operating a clock data recovery device of a wireless optical communication receiver,
A step in which the amplifier converts the input current into voltage and converts a single analog signal into a differential analog signal;
A step of an analog equalizer removing ISI (Inter Symbol Interference) of the differential analog signal to generate a data signal; and
A step of a clock data recovery unit sampling the data signal, recovering the clock and data of the data signal, and outputting a recovered data signal; including:
The step of generating the data signal by removing the ISI of the differential analog signal by the above analog equalizer is:
A step of receiving the differential analog signal, which is the output signal of the amplifier, and removing the ISI through a continuous time linear equalizer (CTLE);
A step in which the differential analog signal with the ISI removed is input to the first amplifier;
A step of inputting an output signal of the first amplifier to a second amplifier connected in series with the first amplifier;
A step in which a low-level band output signal of the first amplifier is input to a low-level amplifier;
A step of a gain controller (Gc) receiving an output signal of the low-level amplifier and feeding back an output signal of the continuous-time linear equalizer; and
A step of outputting the data signal based on the output signal of the continuous-time linear equalizer fed back by the second amplifier;
The above gain controller,
Determine the damping factor of the above analog equalizer and control the frequency bandwidth of the above analog equalizer,
The above clock data restoration unit,
A method for operating a clock data recovery device of a wireless optical communication receiver, comprising: a step of restoring a clock and data based on the position of a rising edge of a clock signal corresponding to the phase of the data signal;
delete In Article 13,
The step of the clock data restoration unit restoring the clock and data of the data signal and outputting the restored data signal is:
A step of the sampler sampling the data signal in response to the clock signal;
A step in which a difference is generated between the output voltages of a plurality of integrators depending on the position of the rising edge of the clock signal corresponding to the phase of the data signal;
A step of converting a voltage-to-current converter (VI Converter) into a current the difference between the output voltages of the plurality of integrators;
A step of controlling the frequency of an output signal according to an input voltage corresponding to the converted current by a voltage controlled oscillator (VCO) and generating the clock signal based on the frequency;
a step of the buffer inputting the clock signal to the plurality of integrators; and
A method for operating a clock data recovery device of a wireless optical communication receiver, comprising: a step of the sampler outputting the recovered data signal in which the clock and data are recovered based on the clock signals received from the plurality of integrators.

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