KR102660491B1 - Electroluminescent Display Device - Google Patents

Abstract

An electroluminescent display device according to an embodiment of the present invention has odd-numbered row sub-pixels and even-numbered row sub-pixels designed to be mirror symmetrical to adjacent light emitting units, and pixel redundancy between the light emitting units. ) By designing the structure, the yield can be improved in ultra-high resolution models. This pixel redundancy structure can be commonly used in odd-numbered row sub-pixels and even-numbered row sub-pixels, so the aperture ratio can be improved.

Description

Electroluminescent display device

The present invention relates to an electroluminescent display device, and more specifically, to an electroluminescent display device that can repair pixel defects while implementing a high aperture ratio in a large screen and ultra-high resolution model.

Currently, as we enter the full-fledged information age, the field of display devices that visually display electrical information signals is developing rapidly, and research is continuing to develop performance such as thinner, lighter, and lower power consumption for various display devices.

Representative display devices include Liquid Crystal Display device (LCD), Field Emission Display device (FED), Electro-Wetting Display device (EWD), and Organic Light Emitting Display device (Organic Lighting Display). Light Emitting Display Device (OLED), etc.

Among these, the electroluminescent display device, which is a display device including an organic light emitting display device, is a self-luminous display device and, unlike the liquid crystal display device, does not require a separate light source and can be manufactured in a lightweight and thin form. In addition, electroluminescent display devices are not only advantageous in terms of power consumption due to low voltage operation, but also have excellent color reproduction, response speed, viewing angle, and contrast ratio (CR), so they are expected to be used in various fields. It is becoming.

An electroluminescent display device is constructed by disposing a light-emitting layer using an organic material between two electrodes called an anode and a cathode. Then, when holes from the anode are injected into the light-emitting layer and electrons from the cathode are injected into the light-emitting layer, the injected electrons and holes recombine with each other to form excitons in the light-emitting layer and emit light. do.

This light-emitting layer contains a host material and a dopant material, and interaction between the two materials occurs. The host generates excitons from electrons and holes and transfers energy to the dopant. The dopant is a dye-like organic substance added in small amounts and serves to receive energy from the host and convert it into light.

In order for display devices to become larger and achieve ultra-high resolution, it is necessary to secure a high aperture ratio.

Meanwhile, when a sub-pixel becomes defective, such as a bright spot or a dark spot, due to foreign matter, static electricity, or other causes, a pixel redundancy structure is needed to operate the sub-pixel normally. The existing pixel redundancy structure has a form in which source nodes of vertically adjacent sub-pixels overlap. In this case, when a defect such as a bright spot or dark spot occurs in any sub-pixel, the source node of the corresponding sub-pixel is cut and disconnected, and the source node of the upper sub-pixel of the defective sub-pixel is welded ( By connecting through welding, defective sub-pixels can be normalized.

This repair structure is difficult to apply to 8K UHD (Ultra High Definition) class ultra-high resolution models because the aperture ratio is reduced.

The inventors of the present invention focused on the fact that a pixel redundancy structure is needed to improve yield in ultra-high resolution models, and that the aperture ratio loss can be minimized if the pixel redundancy structure can be shared for two neighboring sub-pixels. , by designing the odd-numbered row sub-pixels and the even-numbered row sub-pixels in mirror symmetry, a pixel redundancy structure can be commonly used by the odd-numbered row sub-pixels and the even-numbered row sub-pixels. invented.

Accordingly, the problem to be solved by the present invention is to provide an electroluminescent display device that can repair pixel defects while implementing a high aperture ratio in a large screen and ultra-high resolution model.

Meanwhile, the gate redundancy pattern to repair short circuit defects between the horizontal wiring of the gate line and the vertical wiring of the data line/power line is currently becoming a problem.

This is because only the interlayer insulation layer is interposed between the horizontal and vertical wiring points, and electrostatic defects may occur due to the short separation distance. In order to improve yield, the structure for repair is designed within the pixel, that is, the sub-pixel. It had to be. Accordingly, a gate redundancy pattern was previously applied to the location where horizontal and vertical wiring intersect. However, as the gate redundancy pattern was formed to occupy a certain area above and below the gate line, it became a factor in reducing the aperture ratio within the pixel, and the addition of the gate redundancy pattern within the pixel made pixel design difficult in ultra-high resolution models.

The inventors of the present invention focused on the fact that the intersection of horizontal and vertical wires is vulnerable to short circuit defects because only the interlayer insulation layer is interposed between them, and that such short circuit defects are affected by the separation distance between wires, By arranging the power line and gate line on a different layer from the existing one, a structure was invented that prevents short circuit defects by interposing a buffer layer in addition to the interlayer insulation layer between vertical and horizontal wiring.

Another problem to be solved by the present invention is to provide an electroluminescent display device that can achieve a high aperture ratio by preventing short circuit defects that occur between vertical and horizontal wiring without a gate redundancy pattern.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to solve the above-described problem, an electroluminescent display device according to an embodiment of the present invention includes data lines and gate lines that cross each other on a substrate to partition a plurality of sub-pixels in a matrix form, and circuit parts of the sub-pixels. It includes a thin film transistor disposed in and a light-emitting element disposed in the light-emitting portion of the sub-pixel, wherein the odd-numbered row sub-pixel is mirror-symmetrical with the even-numbered row sub-pixel, and the odd-numbered row sub-pixel is mirror-symmetrical with the even-numbered row sub-pixel. The light emitting part of the pixel and the light emitting part of the even-numbered row sub-pixel may be adjacent to each other.

In order to solve the above-described problem, an electroluminescent display device according to another embodiment of the present invention includes data lines, gate lines, and sub-pixels that cross each other on a substrate to partition a plurality of sub-pixels in a matrix form. It includes a thin film transistor disposed in a circuit portion and a light-emitting element disposed in a light-emitting portion of a sub-pixel, wherein the odd-numbered row sub-pixel is mirror-symmetrical with the even-numbered row sub-pixel, and is connected to the light-emitting portion of the odd-numbered row sub-pixel. The light emitting units of the even-numbered row sub-pixels are adjacent to each other, and one pixel redundancy structure is disposed between the adjacent light-emitting units, so that it can be commonly used by the odd-numbered row sub-pixels and the even-numbered row sub-pixels for repair. .

Specific details of other embodiments are included in the detailed description and drawings.

The present invention can improve yield by applying a pixel redundancy structure in an ultra-high resolution model, and this pixel redundancy structure can be commonly used in odd-numbered row sub-pixels and even-numbered row sub-pixels, thereby improving the aperture ratio. .

The present invention can prevent short circuit defects that occur between the vertical wiring and the horizontal wiring by arranging the vertical wiring of the data line/power line and the horizontal wiring of the gate line on a different layer from the existing wiring. Accordingly, the gate redundancy pattern within the pixel can be deleted, making pixel design easier in ultra-high resolution models and securing additional aperture ratio.

The effects according to the present invention are not limited to the contents exemplified above, and further various effects are included in the present specification.

1 is a block diagram schematically showing an electroluminescence display device according to an embodiment of the present invention.
Figure 2 is a circuit diagram of a pixel included in an electroluminescence display device according to an embodiment of the present invention.
Figure 3 is a plan view schematically showing an electroluminescence display device according to an embodiment of the present invention.
FIGS. 4A and 4B are diagrams schematically showing the cross-sectional structure of the electroluminescent display device according to an embodiment of the present invention shown in FIG. 3.
FIG. 5 is a plan view schematically illustrating a repair process in the electroluminescent display device according to an embodiment of the present invention shown in FIG. 3.
Figure 6 is a plan view schematically showing an electroluminescence display device according to another embodiment of the present invention.
FIGS. 7A and 7B are diagrams schematically showing the cross-sectional structure of the electroluminescent display device according to another embodiment of the present invention shown in FIG. 6.
FIG. 8 is a diagram schematically showing a cross section taken along line II' of the electroluminescent display device according to another embodiment of the present invention shown in FIG. 6.
FIG. 9 is another diagram schematically showing a cross section taken along line II' of the electroluminescent display device according to another embodiment of the present invention shown in FIG. 6.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless 'only' is used. In cases where a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting components, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

The fact that an element or layer is referred to as being on another element or layer includes all cases where another layer or other element is interposed directly on or in the middle of another element.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the components shown.

Each feature of the various embodiments of the present invention can be partially or fully combined or combined with each other, and as can be fully understood by those skilled in the art, various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other. It may be possible to conduct them together due to a related relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram schematically showing an electroluminescence display device according to an embodiment of the present invention.

Referring to FIG. 1, an electroluminescent display device 100 according to an embodiment of the present invention includes a display panel 110, a data driving integrated circuit (IC) 130, a gate driving integrated circuit 140, It may be configured to include an image processing unit 170 and a timing controller 180.

The display panel 110 may include a plurality of sub-pixels 160. The plurality of sub-pixels 160 may be arranged in a row direction and a column direction in a matrix form. For example, as shown in FIG. 1, the plurality of sub-pixels 160 may be arranged in m rows and n columns. Hereinafter, for convenience of explanation, a group of sub-pixels 160 arranged in the row direction among the plurality of sub-pixels 160 is defined as a row sub-pixel, and a group of sub-pixels 160 arranged in the column direction is defined as a row sub-pixel. Column is defined as a sub-pixel.

Each of the plurality of sub-pixels 160 may implement light of a specific color. For example, the plurality of sub-pixels 160 may be composed of a red sub-pixel that implements red, a green sub-pixel that implements green, and a blue sub-pixel that implements blue. In this case, a group of red sub-pixels, green sub-pixels, and blue sub-pixels may be referred to as one pixel.

The plurality of sub-pixels 160 of the display panel 110 may be connected to gate lines GL1 to GLm and data lines DL1 to DLn, respectively. For example, 1 row sub-pixel may be connected to the first gate line GL1, and 1 column sub-pixel may be connected to the first data line DL1. Additionally, the 2nd to m row sub-pixels may be respectively connected to the second to mth gate lines (GL2 to GLm). Additionally, the 2nd to nth column sub-pixels may be connected to the second to nth data lines DL2 to DLn, respectively. The plurality of sub-pixels 160 may be configured to operate based on the gate voltage transmitted from the gate lines GL1 to GLm and the data voltage transmitted from the data lines DL1 to DLn.

The image processing unit 170 may output a data enable signal (DE) in addition to a data signal (image data) (DATA) supplied from the outside. In addition to the data enable signal DE, the image processing unit 170 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

The timing controller 180 may receive various timing signals including a vertical synchronization signal, a horizontal synchronization signal, a data enable signal (DE), and a clock signal along with the data signal (DATA) from the image processing unit 170. The timing controller 180 receives a data signal (DATA), that is, input image data, from the image processing unit 170, converts it to a data signal format that can be processed by the data driving integrated circuit 130, and generates a data signal (DATA). That is, in order to control the data driving integrated circuit 130 and the gate driving integrated circuit 140 in addition to outputting the output image data, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal (DE), and a clock signal are used. By receiving a timing signal, various control signals (DCS, GCS) can be generated and output to the data driving integrated circuit 130 and the gate driving integrated circuit 140.

For example, the timing controller 180 uses a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal to control the gate driving integrated circuit 140. Various gate control signals (GCS) including (Gate Output Enable; GOE) can be output.

Here, the gate start pulse may control the operation start timing of one or more gate circuits constituting the gate driving integrated circuit 140. The gate shift clock is a clock signal commonly input to one or more gate circuits, and can control the shift timing of a scan signal (gate pulse). The gate output enable signal specifies timing information of one or more gate circuits.

In addition, the timing controller 180 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (Source) to control the data driving integrated circuit 130. Various data control signals (DCS) including Output Enable (SOE) can be output.

Here, the source start pulse may control the data sampling start timing of one or more data circuits constituting the data driving integrated circuit 130. The source sampling clock is a clock signal that controls the sampling timing of data in each data circuit. The source output enable signal may control the output timing of the data driving integrated circuit 130.

The gate driving integrated circuit 140 sequentially supplies scan signals of the on voltage or off voltage to the gate lines GL1 to GLm under the control of the timing controller 180, thereby driving the gate line GL1. to GLm) can be driven sequentially.

Depending on the driving method, the gate driving integrated circuit 140 may be located on only one side of the display panel 110, or in some cases, may be located on both sides.

The gate driving integrated circuit 140 is connected to the bonding pad of the display panel 110 using Tape Automated Bonding (TAB) or Chip On Glass (COG), or is connected to the bonding pad of the display panel 110 using a Gate In Panel (GIP) method. It may be implemented as a type and placed directly on the display panel 110, or, depending on the case, may be integrated and placed on the display panel 110.

The gate driving integrated circuit 140 may include a shift register, level shifter, etc.

When a specific gate line is opened, the data driving integrated circuit 130 converts the output image data DATA received from the timing controller 180 into an analog data voltage and supplies it to the data lines DL1 to DLn, thereby generating data. Lines DL1 to DLn can be driven.

The data driving integrated circuit 130 may be connected to a bonding pad of the display panel 110 using a tape automated bonding method or a chip-on-glass method, or may be placed directly on the display panel 110, and in some cases, may be connected to the display panel 110. It may also be integrated and placed at (110).

The data driving integrated circuit 130 may be implemented using a chip on film (COF) method. In this case, one end of the data driving integrated circuit 130 may be bonded to at least one source printed circuit board, and the other end may be bonded to the display panel 110.

The data driving integrated circuit 130 may include a logic unit including various circuits such as a level shifter and a latch unit, a digital analog converter (DAC), and an output buffer.

The detailed structure of the pixel 160 is explained in FIGS. 2 and 3.

Figure 2 is a circuit diagram of a pixel included in an electroluminescence display device according to an embodiment of the present invention. Below, for convenience of explanation, the structure and operation of the electroluminescent display device according to an embodiment of the present invention when it is a 2T (Transistor) 1C (Capacitor) pixel circuit will be described, but the present invention is not limited thereto. .

Referring to FIG. 2, in the electroluminescent display device 100 according to an embodiment of the present invention, one sub-pixel includes a switching transistor (ST), a driving transistor (DT), and a compensation circuit (not shown). ) and a light emitting element (LE).

The light emitting element LE may operate to emit light according to the driving current formed by the driving transistor DT.

The switching transistor (ST) may perform a switching operation so that the data signal supplied through the data line 116 is stored as a data voltage in the capacitor C in response to the gate signal supplied through the gate line 117.

The driving transistor 113 may operate so that a constant driving current flows between the high-potential power line (VDD) and the low-potential power line (VSS) in response to the data voltage stored in the capacitor 112.

Here, the compensation circuit is a circuit for compensating the threshold voltage of the driving transistor (DT), and may be configured to include one or more thin film transistors and a capacitor. The composition of the compensation circuit can vary greatly depending on the compensation method.

As such, in the electroluminescent display device 100 according to an embodiment of the present invention, one sub-pixel includes a switching transistor (ST), a driving transistor (DT), a capacitor (C), and a light emitting element (LE). It is composed of a 2T1C structure, but if a compensation circuit is added, it can be configured in various ways, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

Figure 3 is a plan view schematically showing an electroluminescence display device according to an embodiment of the present invention. 4A and 4B are diagrams schematically showing the cross-sectional structure of the electroluminescent display device according to an embodiment of the present invention shown in FIG. 3.

At this time, FIG. 3 shows the planar structure of four 2x2 sub-pixels (P11, P12, P21, and P22) in the electroluminescence display device 100 according to an embodiment of the present invention as an example. For convenience of explanation, FIG. 3 shows an example of a 2T1C structure including a switching transistor (ST), a driving transistor (DT), a capacitor (C), and a light emitting element (LE) for one of the sub-pixels (P21). However, if a compensation circuit is added as described above, it can be configured in various ways, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

And, FIG. 4A shows the electroluminescence display device 100 according to an embodiment of the present invention shown in FIG. 3, a circuit section (CA) including a driving transistor (DT) and a capacitor, and a light emitting element (LE). A part of the light emitting part (EA) and the intersection part (IA) of the gate lines (117m-1, 117m) and the data lines (116n-1, 116n) is shown as an example. FIG. 4B shows, as an example, a portion of the circuit portion (CA) including the switching transistor (ST) in the electroluminescent display device 100 according to an embodiment of the present invention shown in FIG. 3.

3 and 4A and 4B, the electroluminescent display device 100 according to an embodiment of the present invention includes a gate line (or scan line) 117m-1, 117m on a substrate 110, The data lines 116n-1 and 116n and the power line (or power voltage line) 119 may intersect to define the pixel area AA. In addition, sensing control lines, reference lines, etc. may be further arranged.

The data lines 116n-1 and 116n and the power line 119 may be disposed on the substrate 110 in a first direction. The gate lines (117m-1, 117m) are arranged in a second direction crossing the first direction and form the pixel area (AA) of one sub-pixel together with the data lines (116n-1, 116n) and the power line 119. can be divided. For convenience, the pixel area (AA) can be divided into a light emitting part (EA) where the light emitting element (LE) emits light, and a circuit part (CA) consisting of a plurality of driving circuits for supplying a driving current to the light emitting element (LE).

In Figure 3, the m-1th gate line (117m-1), the m-th gate line (117m), the n-1th data line (116n-1), and the n-th data line (116n) are shown together with the power line 119. The case of dividing four 2x2 sub-pixels (P11, P12, P21, and P22) is shown as an example, but the present invention is not limited to this.

Among them, the odd-numbered row sub-pixels (P11, P12) have the light emitting portion (EA) disposed below the circuit portion (CA), and the even-numbered row sub-pixels (P21, P22) have the light emitting portion (EA) disposed below the circuit portion (CA). ) The case placed above is given as an example. Accordingly, the m-1th gate line (117m-1) of the odd-numbered row sub-pixels (P11, P12) is disposed on the upper side of the sub-pixels (P11, P12), while the even-numbered row sub-pixels (P21, P22) may have an m-th gate line (117m) disposed below the sub-pixels (P21, P22).

Figure 3 shows an example where the n-1th data line 116n-1 and the nth data line 116n are arranged adjacent to each other, but the present invention is not limited to this.

The power line 119 may be arranged in one or more pixel areas (AA), but the present invention is not limited thereto.

A reference line may be disposed in the first direction along with the data lines 116n-1 and 116n and the power line 119 on the same layer as the data lines 116n-1 and 116n and the power line 119.

The plurality of pixel areas (AA) may be composed of a red sub-pixel area, a green sub-pixel area, a blue sub-pixel area, and a white sub-pixel area to form a unit pixel. In Figure 3, only the pixel area (AA) of four arbitrary 2x2 sub-pixels is shown as an example, but the present invention is not limited thereto. Each of the pixel areas AA of these red, green, blue and white sub-pixels includes a light emitting element LE and a plurality of pixel driving circuits that independently drive the light emitting elements LE. The pixel driving circuit may include a switching transistor (ST), a driving transistor (DT), a capacitor (C), and a sensing transistor (not shown).

The switching transistor (ST) turns on when a scan pulse is supplied to the gate line (117m-1, 117m) and drives the data signal supplied to the data line (116n-1, 116n) to the capacitor (C). It can be supplied to the first gate electrode 121 of the transistor DT. The switching transistor ST has a second gate electrode 121' connected to the gate lines 117m-1 and 117m, a data line 116n-1, A second source electrode 122' connected to 116n), a second drain electrode 123' connected to the first gate electrode 121 through a sixth contact hole, and a second active layer 124'. It can be configured.

Next, the driving transistor (DT) controls the current supplied from the power line 119 according to the driving voltage charged in the capacitor (C) and supplies a current proportional to the driving voltage to the light emitting element (LE), thereby making the light emitting element ( LE) emits light. The driving transistor DT has a first gate electrode 121 connected to the second drain electrode 123' of the switching transistor ST through the sixth contact hole, and a first source electrode connected to the power line 119 ( 122), and may include a first drain electrode 123 and a first active layer 124 connected to the light emitting element (LE) through the fifth contact hole.

At this time, the power line 119 may be connected to the first source electrode 122 of a neighboring sub-pixel through a bridge wire (not shown). The bridge wiring may extend to neighboring sub-pixels in a direction parallel to the second direction. The bridge wire extending to the neighboring sub-pixel may be connected to the first source electrode 122 of the neighboring sub-pixel through the tenth contact hole. However, the present invention is not limited to this.

One side of the bridge wiring may be connected to the power line 119 above it through the 11th contact hole.

Among them, the thin film transistor shown in FIG. 4A is a driving transistor (DT), and is an example of a thin film transistor with a top gate structure in which the first gate electrode 121 is disposed on the first active layer 124, especially a coplanar structure. holding it In addition, the thin film transistor shown in Figure 4b is a switching transistor (ST), and has a top gate structure in which the second gate electrode 121' is disposed on the second active layer 124', especially a thin film with a coplanar structure. A transistor is used as an example. However, the present invention is not limited to this, and a thin film transistor with a bottom gate structure in which the gate electrode is disposed below the active layer can also be applied.

The first gate electrode 121 of the driving transistor DT may overlap the first active layer 124 with a gate insulating layer 115b of substantially the same shape as that of the first gate electrode 121 interposed therebetween. The second gate electrode 121' of the switching transistor (ST) has a gate insulating layer 115b of substantially the same shape as the second gate electrode 121', and overlaps the second active layer 124'. You can.

Specifically, the first active layer 124 and the second active layer 124' may be disposed on the substrate 110.

At this time, a light blocking layer 125 may be disposed below the first active layer 124, and a buffer layer 115a may be disposed between the first active layer 124 and the light blocking layer 125.

The light blocking layer 125 may serve to block the first active layer 124 from being influenced by light from external or surrounding light emitting devices, and may be disposed on the bottom layer of the substrate 110.

The buffer layer 115a may be disposed on the substrate 110 to cover the light blocking layer 125 .

Each of the first active layer 124 and the second active layer 124' is formed to overlap the first gate electrode 121 and the second gate electrode 121' on the gate insulating layer 115b, A channel may be formed between the source electrode 122 and the first drain electrode 123 and between the second source electrode 122' and the second drain electrode 123'.

The first active layer 124 and the second active layer 124' may be formed using an oxide semiconductor containing at least one metal selected from Zn, Cd, Ga, In, Sn, Hf, and Zr. It may be made of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or organic semiconductor.

Figure 4a shows an example where the gate insulating layer 115b is formed limited to the lower part of the first gate electrode 121, but the present invention is not limited to this. In addition, Figure 4b shows an example where the gate insulating layer 115b is formed limited to the lower part of the second gate electrode 121', but the present invention is not limited to this. The gate insulating layer 115b may be formed on the entire surface of the substrate 110 on which the first active layer 124 and the second active layer 124' are formed. In this case, the gate insulating layer 115b has a first source electrode ( 122) and the first drain electrode 123 may be formed with contact holes for connecting each of the source and drain regions of the first active layer 124. Additionally, the gate insulating layer 115b has contact holes for connecting the second source electrode 122' and the second drain electrode 123' to each of the source and drain regions of the second active layer 124'. can be formed.

The gate insulating layer 115b may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multiple layer of silicon nitride (SiNx) or silicon oxide (SiOx).

Gate lines 117m-1 and 117m may be disposed in a second direction on the same layer as the first gate electrode 121 and the second gate electrode 121'.

Like the first gate electrode 121, a limited gate insulating layer 115b may be formed below the gate lines 117m-1 and 117m, but the present invention is not limited thereto.

The first gate electrode 121, the second gate electrode 121', and the gate lines 117m-1, 117m are made of various conductive materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), and gold ( It may be composed of any one or an alloy of two or more of Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or multiple layers thereof.

An interlayer insulating layer 115c may be disposed on the first gate electrode 121, the second gate electrode 121', and the gate lines 117m-1 and 117m.

The interlayer insulating layer 115c may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or a multiple layer of silicon nitride (SiNx) or silicon oxide (SiOx). The interlayer insulating layer 115c may be formed over the entire surface of the substrate 110, as shown in FIGS. 4A and 4B, or may be formed only in the pixel area AA, but the present invention is not limited thereto.

A first source electrode 122, a first drain electrode 123, and a second source electrode 122' are formed on the interlayer insulating layer 115c on the first active layer 124 and the second active layer 124', respectively. and a second drain electrode 123' may be disposed. The first source electrode 122 and the second source electrode 122' each connect the first active layer 124 and the second active layer through the first and third contact holes penetrating the interlayer insulating layer 115c. Each may be connected to the source region of (124'), and the first drain electrode 123 and the second drain electrode 123' each have a second contact hole and a fourth contact hole penetrating the interlayer insulating layer 115c. It can be connected to the drain regions of the first active layer 124 and the second active layer 124', respectively.

The second drain electrode 123' of the switching transistor (ST) may extend in one direction and be electrically connected to the first gate electrode 121 of the driving transistor (DT) through the sixth contact hole.

A data line ( 116n-1, 116n) may be arranged (see FIG. 4).

In one embodiment of the present invention, the repair pattern 118 is formed on the same layer of the first source electrode 122 and the second source electrode 122' and the first drain electrode 123 and the second drain electrode 123'. can be placed. However, the present invention is not limited to this. The repair pattern 118 may be disposed on the same layer as the first gate electrode 121, the second gate electrode, and the gate lines 117m-1 and 117m.

The repair pattern 118 may be disposed at the boundary between the odd-numbered row sub-pixels (P11 and P12) and the even-numbered row sub-pixels (P21 and P22). The repair pattern 118 according to an embodiment of the present invention is commonly used by the odd-numbered row sub-pixels (P11, P12) and the even-numbered row sub-pixels (P21, P22) for repair.

Figure 3 shows an example where the repair pattern 118 is disposed adjacent to the power line 119, but the present invention is not limited to this and may be disposed adjacent to the data lines 116n-1 and 116n. It may be possible. Additionally, the repair pattern 118 may be disposed at a certain position regardless of the power line 119 and the data lines 116n-1 and 116n.

As described above, in this specification, the thin film transistor is described as having a coplanar structure, but the thin film transistor may be implemented in other structures such as a staggered structure.

Next, a protective layer 115d and a planarization layer 115e may be disposed on the thin film transistor. The protective layer 115d protects the thin film transistor, the gate driver and other wiring arranged outside the pixel area (AA), and the planarization layer 115e smoothes the level difference on the substrate 110 to flatten the upper part of the substrate 110. It can be formed to do so.

A color filter layer (CF) may be disposed on the protective layer (115d) of the light emitting unit (EA). However, the present invention is not limited to this.

The protective layer 115d may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or a multiple layer of silicon nitride (SiNx) or silicon oxide (SiOx). The protective layer 115d may be formed over the entire surface of the substrate 110, as shown in FIGS. 4A and 4B, or may be formed only in the pixel area AA, but the present invention is not limited thereto.

The planarization layer 115e may be made of an organic insulating material.

The planarization layer 115e is made of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, and photoresist. It can be formed as any one, but is not limited to this.

The first drain electrode 123 may be connected to the anodes 126a and 126b of the light emitting element LE through the fifth contact hole penetrating the protective layer 115d and the planarization layer 115e.

At this time, for convenience, the anode of the odd-numbered row sub-pixels (P11, P12) is referred to as the odd-numbered row anode (126a), and the anode of the even-numbered row sub-pixels (P21, P22) is referred to as the even-numbered row anode (126b). Please refer to it.

In one embodiment of the present invention, when the odd-numbered row anode 126a and the even-numbered row anode 126b are disposed adjacent to each other, and the repair pattern 118 is overlapped and disposed below the odd-numbered row anode 126a, a defective sub-pixel occurs. It is characterized in that defective sub-pixels can be repaired through the repair pattern 118.

That is, when a sub-pixel becomes defective, such as a bright spot or a dark spot, due to foreign matter, static electricity, or other causes, a pixel redundancy structure is needed to operate the sub-pixel normally. The existing pixel redundancy structure has a form in which source nodes of vertically adjacent sub-pixels overlap. In this case, when a defect such as a bright spot or dark spot occurs in any sub-pixel, the source node of the corresponding sub-pixel is cut and disconnected, and the source node of the upper sub-pixel of the defective sub-pixel is welded ( By connecting through welding, defective sub-pixels can be normalized.

However, this repair structure was difficult to apply in 8K UHD (Ultra High Definition) class ultra-high resolution models because the aperture ratio was reduced.

Commonly, a resolution of 3840x2160 (about 8.8 million pixels), which is four times that of FHD, is called 4K UHD, and a resolution of 7680x4320 (about 33 million pixels), which is four times that of FHD, is called 8K UHD. To make it more convenient, 4K UHD is also called UHD and 8K UHD is called FUHD. Of course, this is only a 16:9 ratio, and there are also resolutions such as 4096x2196 with a 17:9 ratio, 4096x1716 with a 2.35:1 ratio, and 4096x3072 with a 4:3 ratio.

Accordingly, one embodiment of the present invention is that in ultra-high resolution models, a pixel redundancy structure is needed to improve yield, and that if a pixel redundancy structure can be shared for two neighboring sub-pixels, aperture ratio loss can be minimized. Taking this into account, the odd-numbered row sub-pixels (P11, P12) and the even-numbered row sub-pixels (P21, P22) are designed to be mirror symmetrical, thereby creating a pixel redundancy structure between the odd-numbered row sub-pixels (P11, P12). ) and the even-numbered row sub-pixels (P21, P22).

That is, the odd-numbered row sub-pixels (P11, P12) and the even-numbered row sub-pixels (P21, P22) are designed to be mirror symmetrical to adjoin the light emitting units (LE), and a pixel redundancy structure is created between the light emitting units (LE). By adding,design, the yield can be improved in ultra-high-resolution,models. This pixel redundancy structure can be commonly used in the odd-numbered row sub-pixels (P11, P12) and the even-numbered row sub-pixels (P21, P22), thereby improving the aperture ratio.

In the pixel redundancy structure according to an embodiment of the present invention, the odd row sub-pixels P11 and P12 and the even row sub-pixels P11 and P12 are adjacent to the odd row anode 126a and a portion of the even row anode 126b. The protrusions 126a' and 126b' protrude from each other toward the boundaries of the pixels P21 and P22, and the protrusions 126a' are disposed below the protrusions 126a' and 126b' through a contact hole 150. , 126b') may be composed of a repair pattern 118 connected to any one of the protrusions 126b'.

The protrusions 126a' and 126b' may be formed of a protrusion 126a' of the odd-numbered row anode 126a and a protrusion 126b' of the even-numbered row anode 126b. Figure 3 shows an example where the protrusion 126b' of the even-numbered row anode 126b is connected to the repair pattern 118, but the present invention is not limited thereto. The protrusion 126a' of the odd-numbered row anode 126a may be connected to the repair pattern 118.

Next, referring to FIG. 4A, the light emitting element LE may be disposed on the planarization layer 115e. For example, as an organic light emitting device, the light emitting device (LE) includes odd or even row anodes 126a and 126b formed on the planarization layer 115e and connected to the first drain electrode 123 of the driving transistor DT. It may be configured to include an organic light emitting layer 127 disposed on odd or even row anodes 126a and 126b, and a cathode 128 disposed on the organic light emitting layer 127.

At this time, the odd or even row anodes 126a and 126b are disposed on the planarization layer 115e and can be electrically connected to the first drain electrode 123 through the fifth contact hole formed in the planarization layer 115e. there is. The odd or even row anodes 126a and 126b may be made of a conductive material with a high work function in order to supply holes to the organic light emitting layer 127. Odd or even row anodes 126a, 126b are, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO). ) and the like may be made of a transparent conductive material.

In FIG. 4A , as an example, odd or even row anodes 126a and 126b are shown connected to the first drain electrode 123 of the driving transistor DT, but the present invention is not limited thereto. The present invention may be configured so that the odd or even row anodes 126a and 126b are connected to the first source electrode 122 of the driving transistor depending on the type of thin film transistor, the design method of the driving circuit, etc.

In addition, as described above, in FIG. 3, the case where the protrusion 126b' of the even-numbered row anode 126b is connected to the repair pattern 118 through the contact hole 150 is shown as an example, but the present invention does not apply to this. It is not limited. The protrusion 126a' of the odd row anode 126a may be connected to the repair pattern 118 through the contact hole 150.

The organic emission layer 127 is an organic layer for emitting light of a specific color and may include any one of a red organic emission layer, a green organic emission layer, a blue organic emission layer, and a white organic emission layer. Additionally, the organic light-emitting layer 127 may further include various organic layers such as a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer. In FIG. 4A, the organic light emitting layer 127 is shown as patterned for each sub-pixel, but the present invention is not limited thereto, and the organic light emitting layer 127 may be a common layer commonly formed in a plurality of sub-pixels.

The cathode 128 may be disposed on the organic light emitting layer 127. The cathode 128 may supply electrons to the organic light emitting layer 127. The cathode 128 is made of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and tin. It may be made of a tin oxide (TO)-based transparent conductive oxide or a ytterbium (Yb) alloy. Alternatively, the cathode 128 may be made of a conductive material.

Next, referring to FIGS. 4A and 4B , a bank 115f may be disposed on the odd or even row anodes 126a and 126b and the planarization layer 115e. The bank 115f may cover a portion of the odd or even row anodes 126a and 126b of the organic light emitting device.

The bank 115f may be arranged to distinguish adjacent sub-pixels in the pixel area AA.

The bank 115f may be made of an organic insulating material. For example, the bank 115f may be made of polyimide, acryl, or benzocyclobutene (BCB)-based resin, but the present invention is not limited thereto.

The bank 115f may be arranged to surround the light emitting unit EA on the planarization layer 115e.

An open hole H is formed in the bank 115f, and the pixel redundancy structure according to an embodiment of the present invention can be exposed through the open hole H. The pixel redundancy structure exposed through the open hole (H) allows repair through laser welding if a defect occurs in any sub-pixel.

FIG. 5 is a plan view schematically illustrating a repair process in the electroluminescent display device according to an embodiment of the present invention shown in FIG. 3.

Referring to FIG. 5, if a defect occurs in any sub-pixel, for example, the sub-pixel (P21) corresponding to the m-th gate line (117m) and the n-1-th data line (116n-1), the corresponding sub-pixel -A repair process can be performed to operate the pixel (P21) normally.

At this time, defects may include defects such as bright spots or dark spots caused by foreign substances, static electricity, or other causes. A bright point is a point that always appears white regardless of whether the corresponding sub-pixel is driven, and a dark point means a point that always appears black regardless of whether the corresponding sub-pixel is driven.

In this way, when defects such as bright spots or dark spots occur in any sub-pixel (P21), the space between the anode 126b and the drain electrode 123 of the defective sub-pixel (P21) is cut (C in FIG. 5). Disconnect. And, the anode of the sub-pixel (P11) corresponding to the upper sub-pixel of the defective sub-pixel (P21), that is, the m-1th gate line (117m-1) and the n-1th data line (116n-1). The defective sub-pixel P21 can be normalized by connecting 126a to the lower repair pattern 118 through welding (W in FIG. 5). In this case, the defective sub-pixel (P21) can be driven by applying a driving current that is the same as the driving current of the sub-pixel (P11) above it.

As described above, the present invention can improve yield by applying a pixel redundancy structure in an ultra-high resolution model, and this pixel redundancy structure includes odd row sub-pixels (P11, P12) and even row sub-pixels (P21). , P22) can be used in common, so the aperture ratio can be improved.

An encapsulation portion (not shown) may be formed on the upper part of the organic light emitting device configured in this way to protect the organic light emitting device, which is vulnerable to moisture, from being exposed to moisture. For example, the encapsulation part may have a structure in which inorganic layers and organic layers are alternately stacked. However, the present invention is not limited to this.

Meanwhile, in the case of the electroluminescent display device 100 according to an embodiment of the present invention described above, an interlayer interconnection is formed between the horizontal wiring of the gate lines (117m-1, 117m) and the vertical wiring of the data lines (116n-1, 116n). Since only the insulating layer 115c is interposed, there is a possibility that electrostatic defects may occur due to the short separation distance. Accordingly, the electroluminescence display device according to another embodiment of the present invention can prevent the above-mentioned electrostatic defect by improving the arrangement of horizontal and vertical wiring, which will be described in detail with reference to the drawings.

Figure 6 is a plan view schematically showing an electroluminescence display device according to another embodiment of the present invention. 7A and 7B to 9 are diagrams schematically showing the cross-sectional structure of the electroluminescent display device according to another embodiment of the present invention shown in FIG. 6.

At this time, FIG. 6 shows the planar structure of four 2x2 sub-pixels (P11, P12, P21, and P22) in the electroluminescence display device 200 according to another embodiment of the present invention as an example. For convenience of explanation, FIG. 6 shows an example of a 2T1C structure including a switching transistor (ST), a driving transistor (DT), a capacitor (C), and a light emitting element (LE) for one of the sub-pixels (P21). However, if a compensation circuit is added as described above, it can be configured in various ways, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

In addition, FIG. 7A shows the electroluminescence display device 200 according to another embodiment of the present invention shown in FIG. 6, for example, a circuit portion (CA) including a driving transistor (DT) and a capacitor, and a light emitting element ( It shows a part of the light emitting area (EA) including LE) and the intersection area (IA) of the gate lines (217m-1, 217m) and data lines (216n-1, 216n). FIG. 7B shows, as an example, a portion of the circuit portion (CA) including the switching transistor (ST) in the electroluminescent display device 200 according to another embodiment of the present invention shown in FIG. 6. FIG. 8 is a diagram schematically showing a cross section taken along line II' of the electroluminescent display device 200 according to another embodiment of the present invention shown in FIG. 6. And, FIG. 9 is another diagram schematically showing a cross section taken along line II' of the electroluminescent display device 200 according to another embodiment of the present invention shown in FIG. 6.

Referring to FIGS. 6 and 7A and 7B, the electroluminescent display device 200 according to another embodiment of the present invention includes gate lines (or scan lines) 217m-1 and 217m on the substrate 210. , the data lines 216n-1 and 216n and the power line (or power voltage line) 219 may intersect to define the pixel area AA. In addition, sensing control lines, reference lines, etc. may be further arranged.

The data lines 216n-1 and 216n and the power line 219 may be disposed on the substrate 210 in a first direction. The gate lines (217m-1, 217m) are arranged in a second direction crossing the first direction, and together with the data lines (216n-1, 216n) and the power line 219, are formed in the pixel area (AA) of one sub-pixel. can be divided. For convenience, the pixel area (AA) can be divided into a light emitting part (EA) where the light emitting element (LE) emits light, and a circuit part (CA) consisting of a plurality of driving circuits for supplying a driving current to the light emitting element (LE).

In Figure 6, the m-1th gate line (217m-1), the m-th gate line (217m), the n-1th data line (216n-1), and the n-th data line (216n) are shown together with the power line 219. The case of dividing four 2x2 sub-pixels (P11, P12, P21, and P22) is shown as an example, but the present invention is not limited to this.

Among them, the odd-numbered row sub-pixels (P11, P12) have the light emitting portion (EA) disposed below the circuit portion (CA), and the even-numbered row sub-pixels (P21, P22) have the light emitting portion (EA) disposed below the circuit portion (CA). ) The case placed above is given as an example. Accordingly, the m-1th gate line (217m-1) of the odd-numbered row sub-pixels (P11, P12) is disposed on the upper side of the sub-pixels (P11, P12), while the even-numbered row sub-pixels (P21, P22) may have an m-th gate line (217m) disposed below the sub-pixels (P21, P22).

Figure 6 shows an example where the n-1th data line 216n-1 and the nth data line 216n are arranged adjacent to each other, but the present invention is not limited to this.

The power line 219 may be arranged in one or more pixel areas (AA), but the present invention is not limited thereto.

A reference line may be disposed in the first direction along with the data lines 216n-1 and 216n and the power line 219 on the same layer as the data lines 216n-1 and 216n and the power line 219.

The plurality of pixel areas (AA) may be composed of a red sub-pixel area, a green sub-pixel area, a blue sub-pixel area, and a white sub-pixel area to form a unit pixel. In Figure 6, only the pixel area (AA) of four arbitrary 2x2 sub-pixels is shown as an example, but the present invention is not limited thereto. Each of the pixel areas AA of these red, green, blue and white sub-pixels includes a light emitting element LE and a plurality of pixel driving circuits that independently drive the light emitting elements LE. The pixel driving circuit may include a switching transistor (ST), a driving transistor (DT), a capacitor (C), and a sensing transistor (not shown).

The switching transistor (ST) turns on when a scan pulse is supplied to the gate line (217m-1, 217m) and drives the data signal supplied to the data line (216n-1, 216n) to the capacitor (C). It can be supplied to the first gate electrode 221 of the transistor DT. The switching transistor (ST) includes a second gate electrode (221') connected to the gate lines (217m-1, 217m), a second source electrode (222') connected to the data lines (216n-1, 216n), and a sixth contact. It may be configured to include a second drain electrode 223' and a second active layer 224' connected to the first gate electrode 221 through a hole.

Next, the driving transistor (DT) controls the current supplied from the power line 219 according to the driving voltage charged in the capacitor (C) and supplies a current proportional to the driving voltage to the light emitting element (LE), thereby making the light emitting element ( LE) emits light. The driving transistor DT has a first gate electrode 221 connected to the second drain electrode 223' of the switching transistor ST through the sixth contact hole, and a first source electrode connected to the power line 219 ( 222), and may include a first drain electrode 223 and a first active layer 224 connected to the light emitting element (LE) through the fifth contact hole.

At this time, the power line 219 may be connected to the first source electrode 222 of the neighboring sub-pixel through a bridge wire (not shown). The bridge wiring may extend to neighboring sub-pixels in a direction parallel to the second direction. The bridge wire extending to the neighboring sub-pixel may be connected to the first source electrode 222 of the neighboring sub-pixel through the tenth contact hole. However, the present invention is not limited to this.

One side of the bridge wiring can be connected to the power line 219 at the top of it through the 11th contact hole.

Among them, the thin film transistor shown in FIG. 7A is a driving transistor (DT), and is an example of a thin film transistor with a top gate structure in which the first gate electrode 221 is disposed on the first active layer 224, especially a coplanar structure. holding it In addition, the thin film transistor shown in Figure 7b is a switching transistor (ST), and has a top gate structure in which the second gate electrode 221' is disposed on the second active layer 224', especially a thin film with a coplanar structure. A transistor is used as an example. However, the present invention is not limited to this, and a thin film transistor with a bottom gate structure in which the gate electrode is disposed below the active layer can also be applied.

The first gate electrode 221 of the driving transistor DT may overlap the first active layer 224 with a gate insulating layer 215b having substantially the same shape as that of the first gate electrode 221. The second gate electrode 221' of the switching transistor (ST) has a gate insulating layer 215b of substantially the same shape as the second gate electrode 221', and overlaps the second active layer 224'. You can.

Specifically, the first active layer 224 and the second active layer 224' may be disposed on the substrate 210.

At this time, a light blocking layer 225 may be disposed below the first active layer 224, and a buffer layer 215a may be disposed between the first active layer 224 and the light blocking layer 225.

The light blocking layer 225 may serve to block the first active layer 224 from being influenced by light from external or surrounding light emitting devices, and may be disposed on the bottom layer of the substrate 210.

The data lines 216n-1 and 216n and the power line 219 according to the present invention may be arranged in the first direction on the same layer as the light blocking layer 225. That is, the data lines 216n-1 and 216n and the power line 219 of the present invention are disposed on the lowest layer of the substrate 210 along with the light blocking layer 225.

This is by placing the vertical wiring of the data lines (216n-1, 216n) and the power line 219 on a different layer from the existing one, so that the vertical wiring of the data lines (216n-1, 216n) and the power line 219 and the gate line ( Short-circuit defects are prevented by interposing at least two layers of insulation, for example, a buffer layer 215a and an interlayer insulation layer 215c, instead of just one layer of the interlayer insulation layer 215c, between horizontal wirings of 217m-1 and 217m. It is for this purpose.

The buffer layer 215a may be disposed on the substrate 210 to cover the light blocking layer 225, the power line 219, and the data lines 216n-1 and 216n.

Each of the first active layer 224 and the second active layer 224' is formed to overlap the first gate electrode 221 and the second gate electrode 221' on the gate insulating layer 215b, A channel may be formed between the source electrode 222 and the first drain electrode 223 and between the second source electrode 222' and the second drain electrode 223'.

The first active layer 224 and the second active layer 224' may be formed using an oxide semiconductor containing at least one metal selected from Zn, Cd, Ga, In, Sn, Hf, and Zr. It may be made of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or organic semiconductor.

Figure 7a shows an example where the gate insulating layer 215b is formed limited to the lower part of the first gate electrode 221, but the present invention is not limited to this. In addition, Figure 7b shows an example where the gate insulating layer 215b is formed limited to the lower part of the second gate electrode 221', but the present invention is not limited to this. The gate insulating layer 215b may be formed on the entire surface of the substrate 210 on which the first active layer 224 and the second active layer 224' are formed. In this case, the gate insulating layer 215b has a first source electrode ( Contact holes may be formed to connect each of the first drain electrode 222) and the first drain electrode 223 to the source region and drain region of the first active layer 224, respectively. Additionally, the gate insulating layer 215b has contact holes for connecting the second source electrode 222' and the second drain electrode 223' to the source and drain regions of the second active layer 224', respectively. can be formed.

The gate insulating layer 215b may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multiple layer of silicon nitride (SiNx) or silicon oxide (SiOx).

The first gate electrode 221 and the second gate electrode 221' are made of various conductive materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel ( It may be composed of any one of Ni), neodymium (Nd), and copper (Cu), an alloy of two or more, or multiple layers thereof.

An interlayer insulating layer 215c may be disposed on the first gate electrode 221 and the second gate electrode 221'.

The interlayer insulating layer 215c may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or a multiple layer of silicon nitride (SiNx) or silicon oxide (SiOx). The interlayer insulating layer 215c may be formed over the entire surface of the substrate 210, as shown in FIGS. 7A and 7B, or may be formed only in the pixel area AA, but the present invention is not limited thereto.

A first source electrode 222, a first drain electrode 223, and a second source electrode 222' are formed on the interlayer insulating layer 215c on the first active layer 224 and the second active layer 224', respectively. and a second drain electrode 223' may be disposed. The first source electrode 222 and the second source electrode 222' each connect the first active layer 224 and the second active layer through the first contact hole and the third contact hole penetrating the interlayer insulating layer 215c. Each may be connected to the source region of (224'), and the first drain electrode 223 and the second drain electrode 223' each have a second contact hole and a fourth contact hole penetrating the interlayer insulating layer 215c. It can be connected to the drain regions of the first active layer 224 and the second active layer 224', respectively.

The second drain electrode 223' of the switching transistor (ST) may extend in one direction and be electrically connected to the first gate electrode 221 of the driving transistor (DT) through the sixth contact hole.

A gate line ( 217m-1, 217m) can be deployed (see Figure 7).

Unlike the above-described embodiment of the present invention, the electroluminescent display device 200 according to another embodiment of the present invention has vertical wiring of the data lines 216n-1 and 216n and the power line 219 on the substrate ( 210), and the horizontal wiring of the gate line (217m-1, 217m) is arranged in the second direction crossing the first direction to partition the pixel area AA together with the vertical wiring.

As such, the electroluminescent display device 200 according to another embodiment of the present invention arranges the vertical wiring of the data lines 216n-1 and 216n and the power line 219 on the same layer as the light blocking layer 225 of the lowest layer. By arranging the horizontal wiring of the gate line (217m-1, 217m) on the same layer as the first source electrode 222/first drain electrode 223, the existing interlayer insulating layer 215c is formed between the vertical wiring and the horizontal wiring. ) It is characterized in that at least two insulating layers, an interlayer insulating layer 215c and a buffer layer 215a, are interposed instead of one layer. Accordingly, short circuit defects that occur at the intersection of vertical and horizontal wiring can be prevented.

In another embodiment of the present invention, the intersection point of the horizontal and vertical wires is vulnerable to short circuit defects because only the interlayer insulating layer 215c is interposed between them, and such short circuit defects are affected by the separation distance between wires. Inspired by this, the data lines (216n-1, 216n), power lines (219), and gate lines (217m-1, 217m) are placed on a different layer from before, thereby creating an interlayer insulation layer (215c) between the horizontal and vertical wirings. ) and the two-layer insulating layer of the buffer layer 215a are interposed to prevent short circuit defects.

Accordingly, the gate redundancy pattern within the sub-pixel can be deleted, making pixel design easier in high-resolution models, improving yield, and securing additional aperture ratio.

In addition, in another embodiment of the present invention, a repair pattern is formed on the same layer of the first source electrode 222 and the second source electrode 222' and the first drain electrode 223 and the second drain electrode 223'. It is characterized by the arrangement of (218). However, the present invention is not limited to this. The repair pattern 218 may be disposed on the same layer as the first gate electrode 221, the second gate electrode 221', and the gate lines 217m-1 and 217m.

The repair pattern 218 may be disposed at the boundary between the odd-numbered row sub-pixels (P11 and P12) and the even-numbered row sub-pixels (P21 and P22). The repair pattern 218 according to another embodiment of the present invention is characterized in that it is commonly used in the odd-numbered row sub-pixels (P11, P12) and the even-numbered row sub-pixels (P21, P22) for repair. .

Figure 6 shows an example where the repair pattern 218 is disposed adjacent to the power line 219, but the present invention is not limited to this and may be disposed adjacent to the data lines 216n-1 and 216n. It may be possible. Additionally, the repair pattern 218 may be disposed at a certain position regardless of the power line 219 and the data lines 216n-1 and 216n.

As described above, in this specification, the thin film transistor is described as having a coplanar structure, but the thin film transistor may be implemented in other structures such as a staggered structure.

Next, a protective layer 215d and a planarization layer 215e may be disposed on the thin film transistor. The protective layer 215d protects the thin film transistor, the gate driver and other wirings arranged outside the pixel area (AA), and the planarization layer 215e smoothes the level difference on the substrate 210 to flatten the upper part of the substrate 210. It can be formed to do so.

A color filter layer CF may be disposed on the protective layer 215d of the light emitting unit EA. However, the present invention is not limited to this.

The protective layer 215d may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx), or a multiple layer of silicon nitride (SiNx) or silicon oxide (SiOx). The protective layer 215d may be formed over the entire surface of the substrate 210, as shown in FIGS. 7A and 7B, or may be formed only in the pixel area AA, but the present invention is not limited thereto.

The planarization layer 215e may be made of an organic insulating material.

The planarization layer 215e is made of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, and photoresist. It can be formed as any one, but is not limited to this.

The planarization layer 215e according to another embodiment of the present invention may be arranged to cover the color filter layer (CF) as shown in FIG. 8, or may be disposed to cover the color filter layer (CF) as shown in FIG. 9. It can be arranged so that part of it is exposed.

When the planarization layer 215e is arranged to cover the color filter layer CF as shown in FIG. 8, the margin L1 of the welding point and the area of the open hole H are reduced, while in FIG. 9 When the planarization layer 215e is disposed to expose a portion of the color filter layer CF as shown, the margin L2 of the welding point and the area of the open hole H may be increased. For example, the area of the open hole H may be increased so that the planarization layer 215e exposes a portion of the color filter layer CF.

The first drain electrode 223 may be connected to the anodes 226a and 226b of the light emitting element LE through a fifth contact hole penetrating the protective layer 215d and the planarization layer 215e.

At this time, as described above, for convenience, the anode of the odd-numbered row sub-pixels (P11, P12) is referred to as the odd-numbered row anode 226a, and the anode of the even-numbered row sub-pixels (P21, P22) is referred to as the even-numbered row anode. It shall be referred to as (226b).

Referring to FIGS. 6, 8, and 9, in another embodiment of the present invention, the odd-numbered row anode 226a and the even-numbered row anode 226b are disposed adjacent to each other, and a repair pattern 218 is formed below the odd-numbered row anode 226a. ) is overlapped and disposed, and when a defective sub-pixel occurs, the defective sub-pixel can be repaired through the repair pattern 218.

As described above, another embodiment of the present invention is that in ultra-high resolution models, a pixel redundancy structure is required to improve yield, and if a pixel redundancy structure can be shared for two neighboring sub-pixels, aperture ratio loss can be avoided. Considering that this can be minimized, the odd-numbered row sub-pixels (P11, P12) and the even-numbered row sub-pixels (P21, P22) are designed to be mirror symmetrical, thereby creating a pixel redundancy structure in the odd-numbered row sub-pixels. It is characterized in that it can be commonly used in (P11, P12) and even-numbered row sub-pixels (P21, P22).

That is, the odd-numbered row sub-pixels (P11, P12) and the even-numbered row sub-pixels (P21, P22) are designed to be mirror symmetrical to adjoin the light emitting units (LE), and a pixel redundancy structure is created between the light emitting units (LE). By adding,design, the yield can be improved in ultra-high-resolution,models. This pixel redundancy structure can be commonly used in the odd-numbered row sub-pixels (P11, P12) and the even-numbered row sub-pixels (P21, P22), thereby improving the aperture ratio.

In the pixel redundancy structure according to another embodiment of the present invention, the odd row anode 226a and a portion of the even row anode 226b are adjacent to the odd row sub-pixels P11 and P12 and the even row sub-pixels. -Protrusions 226a' and 226b' that protrude from each other toward the boundaries of the pixels (P21 and P22) and protrusions (226a) disposed below the protrusions (226a' and 226b') through a contact hole 250. ', 226b') may be composed of a repair pattern 218 connected to any one of the protrusions 226b'.

The protrusions 226a' and 226b' may be formed of a protrusion 226a' of the odd-numbered row anode 226a and a protrusion 226b' of the even-numbered row anode 226b. Referring to FIGS. 6, 8, and 9, the case where the protrusion 226b' of the even-numbered row anode 226b is connected (or connected) to the repair pattern 218 is shown as an example, but the present invention It is not limited to this. The protrusion 126a' of the odd-numbered row anode 226a may be connected to the repair pattern 218.

Next, referring to FIGS. 7A and 7B to 9 , the light emitting element LE may be disposed on the planarization layer 215e. For example, as an organic light emitting device, the light emitting device (LE) includes odd or even row anodes 226a and 226b formed on the planarization layer 215e and connected to the first drain electrode 223 of the driving transistor DT. It may be configured to include an organic light-emitting layer 227 disposed on odd or even row anodes 226a and 226b, and a cathode 228 disposed on the organic light-emitting layer 227.

At this time, the odd or even row anodes 226a and 226b are disposed on the planarization layer 215e and can be electrically connected to the first drain electrode 223 through the fifth contact hole formed in the planarization layer 215e. there is. The odd or even row anodes 226a and 226b may be made of a conductive material with a high work function in order to supply holes to the organic light emitting layer 227. The odd or even row anodes 226a and 226b are, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO). ) and the like may be made of a transparent conductive material.

In FIG. 7A , as an example, odd or even row anodes 226a and 226b are shown connected to the first drain electrode 223 of the driving transistor DT, but the present invention is not limited thereto. The present invention may be configured so that the odd or even row anodes 226a and 226b are connected to the first source electrode 222 of the driving transistor depending on the type of thin film transistor, the design method of the driving circuit, etc.

In addition, as described above in FIGS. 6, 8, and 9, the case where the protrusion 126b' of the even-numbered row anode 126b is connected to the repair pattern 118 through the contact hole 150 is shown as an example. , the present invention is not limited thereto. The protrusion 226a' of the odd row anode 226a may be connected to the repair pattern 218 through the contact hole 250.

The organic emission layer 227 is an organic layer for emitting light of a specific color and may include any one of a red organic emission layer, a green organic emission layer, a blue organic emission layer, and a white organic emission layer. Additionally, the organic light-emitting layer 227 may further include various organic layers such as a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer. In FIG. 7A, the organic light emitting layer 227 is shown as patterned for each sub-pixel, but the present invention is not limited thereto, and the organic light emitting layer 227 may be a common layer commonly formed in a plurality of sub-pixels.

The cathode 228 may be disposed on the organic light emitting layer 227. The cathode 228 may supply electrons to the organic light emitting layer 227. The cathode 228 is made of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and tin. It may be made of a tin oxide (TO)-based transparent conductive oxide or a ytterbium (Yb) alloy. Alternatively, the cathode 228 may be made of a conductive material.

Next, referring to FIGS. 7A and 7B , a bank 215f may be disposed on the odd or even row anodes 226a and 226b and the planarization layer 215e. The bank 215f may cover a portion of the odd or even row anodes 226a and 226b of the organic light emitting device.

The bank 215f may be arranged to separate adjacent sub-pixels P11, P12, P21, and P22 in the pixel area AA.

The bank 215f may be made of an organic insulating material. For example, the bank 215f may be made of polyimide, acryl, or benzocyclobutene (BCB)-based resin, but the present invention is not limited thereto.

The bank 215f may be arranged to surround the light emitting unit EA on the planarization layer 215e.

An open hole H is formed in the bank 215f, and a pixel redundancy structure according to another embodiment of the present invention may be exposed through the open hole H. The pixel redundancy structure exposed through the open hole (H) allows repair through laser welding if a defect occurs in any sub-pixel.

That is, if a defect occurs in any sub-pixel, for example, the sub-pixel (P21) corresponding to the m-th gate line (217m) and the n-1-th data line (216n-1), the corresponding sub-pixel (P21) ) can proceed with the repair process to operate normally.

If a defect such as a bright spot or a dark spot occurs in any sub-pixel (P21), the gap between the anode 226b and the drain electrode 223 of the defective sub-pixel P21 is cut to disconnect it. And, the anode of the sub-pixel (P11) corresponding to the upper sub-pixel of the defective sub-pixel (P21), that is, the m-1th gate line (217m-1) and the n-1th data line (216n-1). The defective sub-pixel P21 can be normalized by connecting 226a to the lower repair pattern 218 through welding. In this case, the defective sub-pixel (P21) can be driven by applying a driving current that is the same as the driving current of the sub-pixel (P11) above it.

As described above, the present invention can improve yield by applying a pixel redundancy structure in an ultra-high resolution model, and this pixel redundancy structure includes odd row sub-pixels (P11, P12) and even row sub-pixels (P21). , P22) can be used in common, so the aperture ratio can be improved.

An encapsulation portion (not shown) may be formed on the upper part of the organic light emitting device configured in this way to protect the organic light emitting device, which is vulnerable to moisture, from being exposed to moisture. For example, the encapsulation part may have a structure in which inorganic layers and organic layers are alternately stacked. However, the present invention is not limited to this.

Exemplary embodiments of the present invention may be described as follows.

An electroluminescent display device according to an embodiment of the present invention includes data lines and gate lines that cross each other on a substrate to partition a plurality of sub-pixels in a matrix form, thin film transistors and sub-pixels disposed in the circuit part of the sub-pixels. It includes a light emitting element disposed in the light emitting part of, and the odd row sub-pixel is mirror symmetrical with the even row sub-pixel, so that the light emitting part of the odd row sub-pixel and the even row sub-pixel are mirror symmetrical. -The light emitting parts of the pixels may be adjacent to each other.

According to another feature of the present invention, the light emitting device includes an anode, and the anode of the odd-numbered row sub-pixel and the anode of the even-numbered row sub-pixel may be disposed adjacent to each other.

According to another feature of the present invention, the light emitting portion of the odd-numbered row sub-pixels may be disposed below the circuit portion, and the light emitting portion of the even-numbered row sub-pixels may be disposed above the circuit portion.

According to another feature of the present invention, the odd-numbered row sub-pixel may have its gate line disposed above the sub-pixel, while the even-numbered row sub-pixel may have its gate line disposed below the sub-pixel. there is.

According to another feature of the present invention, the electroluminescent display device may further include a repair pattern disposed on the same layer as the source/drain electrodes of the thin film transistor.

According to another feature of the present invention, the repair pattern may be disposed at the boundary between the odd-numbered row sub-pixels and the even-numbered row sub-pixels.

According to another feature of the present invention, the anode of the odd-numbered row sub-pixel and the anode of the even-numbered row sub-pixel have a portion thereof directed toward the border of the adjacent odd-numbered row sub-pixel and the even-numbered row sub-pixel. Each may further include protruding protrusions.

According to another feature of the present invention, repair patterns may be overlapped and disposed on the lower portions of the protrusions.

According to another feature of the present invention, the repair pattern may be connected to any one of the protrusions through a predetermined contact hole.

According to another feature of the present invention, the repair pattern can be connected to another one of the protrusions through laser welding.

According to another feature of the present invention, the data line is disposed in a first direction on the substrate, and the gate line is disposed in a second direction intersecting the first direction with at least two layers of insulating layers on top of the data line. You can.

According to another feature of the present invention, the electroluminescent display device further includes a light blocking layer disposed below the thin film transistor, and the data line may be disposed on the same layer as the light blocking layer.

In addition, an electroluminescent display device according to another embodiment of the present invention includes data lines and gate lines that cross each other on a substrate to partition a plurality of sub-pixels in a matrix form, a thin film transistor disposed in the circuit section of the sub-pixels, and It includes a light-emitting element disposed in a light-emitting portion of a sub-pixel, and the odd-numbered row sub-pixel is mirror-symmetrical with the even-numbered row sub-pixel, so that the light-emitting portion of the odd-numbered row sub-pixel and the even-numbered row sub-pixel are mirror-symmetrical. The light emitting units are adjacent to each other, and one pixel redundancy structure is disposed between the adjacent light emitting units, so that it can be commonly used in the odd-numbered row sub-pixels and the even-numbered row sub-pixels for repair.

According to another feature of the present invention, the light emitting device includes an anode, and the pixel redundancy structure is such that the anode of the odd-numbered row sub-pixel and a part of the even-numbered row sub-pixel are adjacent to the odd-numbered row sub-pixel and the even-numbered row sub-pixel. It may be configured to include protrusions that protrude from each other toward the boundary of the row sub-pixel, and a repair pattern disposed below the protrusions.

According to another feature of the present invention, the electroluminescent display device may further include a protective layer disposed on the source/drain electrode of the thin film transistor, a color filter layer disposed on the protective layer of the light emitting portion, and a planarization layer disposed on the color filter layer. You can.

According to another feature of the present invention, the repair pattern may be disposed on the same layer as the source/drain electrodes of the thin film transistor.

According to another feature of the present invention, the electroluminescent display device has a contact hole that penetrates the protective layer and exposes a portion of the surface of the repair pattern, and a contact hole that penetrates the flattening layer and the color filter layer to expose a portion of the surface of the protective layer on the repair pattern. It further includes an open hole, and the protrusions can be disposed on the protective layer on the upper part of the repair pattern through the open hole.

According to another feature of the present invention, the repair pattern may be connected to any one of the protrusions through a contact hole.

According to another feature of the present invention, the repair pattern may be connected to another one of the protrusions through laser welding.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100,200: Electroluminescence display device
115a: buffer layer
115b: Gate insulation layer
115c: Interlayer insulation layer
115d: protective layer
115e: Planarization layer
115f: bank
116n-1,116n,216n-1,216n: data line
117m-1,117m,217m-1,217m: Gateline
119,219: Power line
125,225: Light blocking layer
126a, 126b, 216a, 216b: Anode
126a', 126b', 216a', 216b': protrusions
127,227: Organic light emitting layer
128,228: cathode
150,250: Repair pattern
H: open hole

Claims (19)

Data lines, power lines, and gate lines that cross each other on the substrate to partition a plurality of sub-pixels in a matrix form;
a thin film transistor disposed in a circuit part of the sub-pixel; and
It is disposed in a light emitting part of the sub-pixel and includes a light emitting element including an anode,
The odd-numbered row sub-pixel and the even-numbered row sub-pixel are symmetrical in arrangement of the circuit part and the light emitting part, so that the light emitting part of the odd-numbered row sub-pixel and the light emitting part of the even-numbered row sub-pixel are aligned with each other. adjacent,
The odd-numbered data line and the even-numbered data line are arranged adjacent to each other, and the odd-numbered column sub-pixel and the even-numbered column sub-pixel are positioned between the odd-numbered data line and the even-numbered data line arranged adjacently. is symmetrical left and right, the thin film transistor of the odd-numbered column sub-pixel is connected to the odd-numbered data line, and the thin film transistor of the even-numbered column sub-pixel is connected to the even-numbered data line,
Both sides of the anode of the odd-numbered row sub-pixel and the anode of the even-numbered row sub-pixel respectively have protrusions that protrude toward the boundary of the adjacent odd-numbered row sub-pixel and the even-numbered row sub-pixel. Have,
The anode of the odd row sub-pixel and the anode of the even row sub-pixel including the protrusions are vertically symmetrical across a boundary between the odd row sub-pixel and the even row sub-pixel, Electroluminescent display device. According to paragraph 1,
An electroluminescence display device wherein the anode of the odd-numbered row sub-pixel and the anode of the even-numbered row sub-pixel are disposed adjacent to each other. According to paragraph 2,
The odd-numbered row sub-pixel has the light emitting portion disposed below the circuit portion, and the even-numbered row sub-pixel has the light emitting portion disposed above the circuit portion. According to paragraph 3,
The odd-numbered row sub-pixel has the gate line disposed above the sub-pixel, while the even-numbered row sub-pixel has the gate line disposed below the sub-pixel. According to paragraph 2,
An electroluminescent display device further comprising a repair pattern disposed on the same layer as the source/drain electrodes of the thin film transistor. According to clause 5,
The repair pattern is disposed at a boundary between the odd-numbered row sub-pixel and the even-numbered row sub-pixel. According to clause 5,
The protrusions on both sides of the anode of the odd-numbered row sub-pixel and the protrusions on both sides of the anode of the even-numbered row sub-pixel face each other. In clause 7,
An electroluminescent display device in which the repair pattern is overlapped and disposed on a lower portion of one of the protrusions on both sides. According to clause 8,
The repair pattern is connected to a protrusion on one side of the anode of the odd-numbered row sub-pixel or the protrusion on one side of the anode of the even-numbered row sub-pixel through a predetermined contact hole. According to clause 9,
The repair pattern is connected to a protrusion on one side of the other of the protrusions on one side of the anode of the odd-numbered row sub-pixel or the anode of the even-numbered row sub-pixel through laser welding. According to any one of claims 1 to 10,
The data line is disposed in a first direction on the substrate,
The gate line is disposed in a second direction crossing the first direction with at least two insulating layers on top of the data line. According to clause 11,
It further includes a light blocking layer disposed below the thin film transistor,
The data line is disposed on the same layer as the light blocking layer. Data lines, power lines, and gate lines that cross each other on the substrate to partition a plurality of sub-pixels in a matrix form;
a thin film transistor disposed in the circuit part of the sub-pixel; and
It is disposed in a light emitting part of the sub-pixel and includes a light emitting element including an anode,
The odd-numbered row sub-pixel is symmetrical to the even-numbered row sub-pixel in that the arrangement of the circuit portion and the light emitting portion is symmetrical, so that the light emitting portion of the odd-numbered row sub-pixel and the light emitting portion of the even-numbered row sub-pixel are adjacent to each other,
One pixel redundancy structure is disposed between the adjacent light emitting units and is commonly used by the odd-numbered row sub-pixel and the even-numbered row sub-pixel for repair,
The odd-numbered data line and the even-numbered data line are arranged adjacent to each other, and the odd-numbered column sub-pixel and the even-numbered column sub-pixel are symmetrical with the odd-numbered data line and the even-numbered data line arranged adjacent to each other. The thin film transistor of the odd-numbered column sub-pixel is connected to the odd-numbered data line, and the thin film transistor of the even-numbered column sub-pixel is connected to the even-numbered data line,
Both sides of the anode of the odd-numbered row sub-pixel and the anode of the even-numbered row sub-pixel respectively have protrusions that protrude toward the boundary of the adjacent odd-numbered row sub-pixel and the even-numbered row sub-pixel. Have,
The anode of the odd row sub-pixel and the anode of the even row sub-pixel including the protrusions are vertically symmetrical across a boundary between the odd row sub-pixel and the even row sub-pixel, Electroluminescent display device. According to clause 13,
The pixel redundancy structure includes protrusions on one side of the protrusions on both sides, and a repair pattern disposed under the protrusions on the one side. According to clause 14,
a protective layer disposed on top of the source/drain electrodes of the thin film transistor;
a color filter layer disposed on the protective layer of the light emitting unit; and
An electroluminescent display device further comprising a planarization layer disposed on the color filter layer. According to clause 15,
The repair pattern is disposed on the same layer as the source/drain electrode of the thin film transistor. According to any one of claims 15 and 16,
a contact hole penetrating the protective layer to expose a portion of the surface of the repair pattern; and
It further includes an open hole penetrating the planarization layer and the color filter layer to expose a portion of the surface of the protective layer on the repair pattern,
The protrusions on one side are disposed on the protective layer on the repair pattern through the open hole. According to clause 17,
The repair pattern is connected to a protrusion on one side of the anode of the odd-numbered row sub-pixel or the protrusion on one side of the anode of the even-numbered row sub-pixel through the contact hole. According to clause 18,
The repair pattern is connected to a protrusion on one side of the other of the protrusions on one side of the anode of the odd-numbered row sub-pixel or the anode of the even-numbered row sub-pixel through laser welding.

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