KR102512779B1 - Electroluminescent display device - Google Patents

Abstract

The electroluminescence display device according to an embodiment of the present invention arranges vertical wires of data lines/power lines and horizontal wires of gate lines on a different layer from those of the existing layers, thereby preventing short-circuit defects occurring at intersections of vertical wires and horizontal wires. It can be prevented.
In addition, in the electroluminescent display device according to an embodiment of the present invention, a trench is formed in advance by removing an insulating layer between adjacent data lines, and then a gate line is patterned, thereby automatically repairing a short circuit defect between data lines ( repair) can be done. Accordingly, even if the interval between the data lines is reduced in the high-resolution model, a defect in which the data lines are short-circuited can be prevented.

Description

Electroluminescent display device {ELECTROLUMINESCENT DISPLAY DEVICE}

The present invention relates to an electroluminescence display device, and more particularly, to an electroluminescence display device capable of preventing a short circuit defect between data lines while realizing a high aperture ratio at a large screen and high resolution.

As we enter the information age in earnest, the field of display devices that visually display electrical information signals is rapidly developing, and research is continuing to develop performance such as thinning, lightening, and low power consumption for various display devices.

Representative display devices include a liquid crystal display device (LCD), a field emission display device (FED), an electro-wetting display device (EWD), and an organic light emitting display device (Organic). Light Emitting Display Device (OLED) and the like.

Among them, the electroluminescent display, which is a display device including an organic light emitting display, is a self-emissive display device and, unlike a liquid crystal display, does not require a separate light source and can be manufactured in a lightweight and thin shape. In addition, the electroluminescent display is not only advantageous in terms of power consumption due to low voltage driving, but also has excellent color representation, response speed, viewing angle, and contrast ratio (CR), so it is expected to be used in various fields. It is becoming.

An electroluminescent display device is configured by disposing a light emitting layer using an organic material between two electrodes called an anode and a cathode. Then, when holes from the anode are injected into the light emitting layer and electrons from the cathode are injected into the light emitting layer, the injected electrons and holes recombine with each other to form excitons in the light emitting layer and emit light. do.

The light emitting layer includes a host material and a dopant material, and interaction between the two materials occurs. The host serves to generate excitons from electrons and holes and transfers energy to the dopant, and the dopant is a dye organic material added in a small amount and serves to receive energy from the host and convert it into light.

In order to realize large display devices and high resolution, it is necessary to secure a high aperture ratio, and the gate redundancy pattern to repair short-circuit defects between the horizontal wiring of the gate line and the vertical wiring of the data line/power line is currently a problem. is becoming

This is because only the interlayer insulating layer is interposed between the intersection of the horizontal wiring and the vertical wiring, and a short separation distance can cause electrostatic failure. In order to improve yield, a repair structure must be designed in the pixel. . Accordingly, in the past, a gate redundancy pattern was applied to a position where horizontal wiring and vertical wiring intersect. However, as the gate redundancy pattern is formed to occupy a predetermined area above and below the gate line, it becomes a factor in reducing the aperture ratio in the pixel, and it is difficult to design pixels in a high-resolution model due to the addition of the gate redundancy pattern in the pixel.

The inventors of the present invention focused on the fact that the intersection point of the horizontal wiring and the vertical wiring is vulnerable to short-circuit defects because only the interlayer insulating layer is interposed therebetween, and such short-circuit defects are affected by the separation distance between the data lines and the data lines. A structure capable of preventing short-circuit defects was invented by arranging the power line and the gate line on a different layer from the conventional one so that a gate insulating layer is interposed between the vertical wiring and the horizontal wiring in addition to the interlayer insulating layer.

Accordingly, an object to be solved by the present invention is to provide an electroluminescent display device capable of realizing a high aperture ratio by preventing short-circuit defects occurring between vertical and horizontal wires without a gate redundancy pattern.

On the other hand, in order to realize a high aperture ratio in a large screen and high resolution, it is necessary to reduce the wiring CD (Critical Dimension) and space, and accordingly, the distance between adjacent data lines is gradually reduced, resulting in an increase in short-circuit defects between adjacent data lines. .

The inventors of the present invention believe that short-circuit defects between adjacent data lines occur as the distance between data lines decreases, and according to the wiring structure described above, even if a short-circuit defect between data lines occurs, it can be repaired during gate line patterning. Focusing on the fact that it can be possible, a structure capable of preventing a short circuit defect between adjacent data lines has been invented.

Accordingly, another problem to be solved by the present invention is to provide an electroluminescent display capable of preventing a short circuit defect between data lines while realizing a high aperture ratio in a large screen and high resolution.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, an electroluminescent display device according to an embodiment of the present invention is a data line and a gate line crossing each other on a substrate to partition a pixel area, a thin film transistor and a pixel disposed in a circuit part of the pixel area. A light emitting device may be disposed in the light emitting portion of the region, data lines may be disposed adjacent to each other in adjacent pixel regions, and an insulating layer between adjacent data lines may be removed to form a trench.

Other embodiment specifics are included in the detailed description and drawings.

According to the present invention, by arranging the vertical wiring of the data line/power line and the horizontal wiring of the gate line on a different layer, it is possible to prevent a short circuit defect occurring between the vertical wiring and the horizontal wiring. Accordingly, the gate redundancy pattern within the pixel can be deleted, providing an effect of facilitating pixel design in a high-resolution model and securing an additional aperture ratio.

Also, according to the present invention, a short circuit defect between data lines can be automatically repaired by forming a trench in advance by removing an insulating layer between adjacent data lines and then patterning the gate line. Accordingly, even if the distance between adjacent data lines is reduced in the high-resolution model, an effect of preventing a short-circuit defect of the data lines without adding a process is provided.

Effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a schematic block diagram of an electroluminescent display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram of a pixel included in an electroluminescent display device according to an exemplary embodiment of the present invention.
3 is a plan view schematically illustrating an electroluminescent display device according to an exemplary embodiment of the present invention.
4 and 5 are diagrams schematically illustrating a cross-sectional structure of an electroluminescent display device according to an exemplary embodiment of the present invention shown in FIG. 3 .
6A to 6F are cross-sectional views sequentially illustrating manufacturing processes of the electroluminescent display device according to the exemplary embodiment shown in FIG. 5 .
7 is a plan view schematically illustrating an electroluminescent display device according to another exemplary embodiment of the present invention.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

When an element or layer is referred to as being on another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or another element is interposed therebetween.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, and as those skilled in the art can fully understand, various interlocking and driving operations are possible, and each embodiment can be implemented independently of each other. It may be possible to implement together in an association relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of an electroluminescent display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , an electroluminescent display device 100 according to an embodiment of the present invention includes a display panel 110, a data driving integrated circuit (IC) 130, a gate driving integrated circuit 150, It may include an image processing unit 170 and a timing controller 180.

The display panel 110 may include a plurality of sub-pixels 160 . The plurality of sub-pixels 160 may be arranged in a matrix form by being arranged in a row direction and a column direction. For example, as shown in FIG. 1 , the plurality of sub-pixels 160 may be arranged in m rows and n columns. Hereinafter, for convenience of description, a group of sub-pixels 160 arranged in a row direction among a plurality of sub-pixels 160 is defined as a row sub-pixel, and a group of sub-pixels 160 arranged in a column direction is defined as Defined as a column sub-pixel.

Each of the plurality of sub-pixels 160 may implement light of a specific color. For example, the plurality of sub-pixels 160 may include a red sub-pixel implementing red, a green sub-pixel implementing green, and a blue sub-pixel implementing blue. In this case, a group of red sub-pixels, green sub-pixels, and blue sub-pixels may be referred to as one pixel.

The plurality of sub-pixels 160 of the display panel 110 may be connected to gate lines GL1 to GLm and data lines DL1 to DLn, respectively. For example, a 1-row sub-pixel may be connected to the first gate line GL1 and a 1-column sub-pixel may be connected to the first data line DL1 . Also, the 2 to m row sub-pixels may be connected to the second to m th gate lines GL2 to GLm, respectively. Also, the 2 to n column sub-pixels may be connected to the second to n th data lines DL2 to DLn, respectively. The plurality of sub-pixels 160 may be configured to operate based on gate voltages transmitted from the gate lines GL1 to GLm and data voltages transmitted from the data lines DL1 to DLn.

The image processor 170 may output the data enable signal DE along with the data signal (image data) DATA supplied from the outside. The image processing unit 170 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE.

The timing controller 180 may receive various timing signals including a vertical sync signal, a horizontal sync signal, a data enable signal DE, and a clock signal from the image processing unit 170 together with the data signal DATA. The timing controller 180 receives the data signal DATA, that is, the input image data, from the image processing unit 170, converts it into a data signal format that can be processed by the data driving integrated circuit 130, and converts it into a data signal DATA, That is, in addition to outputting the output image data, in order to control the data driving integrated circuit 130 and the gate driving integrated circuit 150, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal DE, a clock signal, etc. A timing signal may be received, and various control signals DCS and GCS may be generated and output to the data driving integrated circuit 130 and the gate driving integrated circuit 150 .

For example, the timing controller 180 may use a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal to control the gate driving integrated circuit 150. Various gate control signals (GCS) including (Gate Output Enable; GOE) and the like may be output.

Here, the gate start pulse may control operation start timing of one or more gate circuits constituting the gate driving integrated circuit 150 . The gate shift clock is a clock signal commonly input to one or more gate circuits and can control shift timing of scan signals (gate pulses). The gate output enable signal specifies timing information of one or more gate circuits.

In addition, the timing controller 180, in order to control the data driving integrated circuit 130, a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (Source Various data control signals (DCS) including Output Enable (SOE) and the like may be output.

Here, the source start pulse may control data sampling start timing of one or more data circuits constituting the data driving integrated circuit 130 . The source sampling clock is a clock signal that controls sampling timing of data in each data circuit. The source output enable signal may control output timing of the data driving integrated circuit 130 .

The gate driving integrated circuit 150 sequentially supplies scan signals of an on voltage or an off voltage to the gate lines GL1 to GLm under the control of the timing controller 180 to generate the gate lines GL1 to GLm) can be sequentially driven.

The gate driving integrated circuit 150 may be located on only one side of the display panel 110 or, in some cases, on both sides, depending on the driving method.

The gate driving integrated circuit 150 is connected to the bonding pad of the display panel 110 using a tape automated bonding (TAB) method or a chip on glass (COG) method, or a gate in panel (GIP) method. It may be implemented as a type and directly disposed on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases.

The gate driving integrated circuit 150 may include a shift register, a level shifter, and the like.

When a specific gate line is opened, the data driving integrated circuit 130 converts the output image data DATA received from the timing controller 180 into an analog data voltage and supplies it to the data lines DL1 to DLn, thereby providing data Lines DL1 to DLn can be driven.

The data driving integrated circuit 130 may be connected to bonding pads of the display panel 110 by a tape automated bonding method or a chip on glass method, or may be directly disposed on the display panel 110. In some cases, the display panel (110) may be integrated and arranged.

The data driving integrated circuit 130 may be implemented in a chip on film (COF) method. In this case, one end of the data driving integrated circuit 130 may be bonded to at least one source printed circuit board, and the other end may be bonded to the display panel 110 .

The data driving integrated circuit 130 may include a logic unit including various circuits such as a level shifter and a latch unit, a digital analog converter (DAC), and an output buffer.

The detailed structure of the pixel 160 will be described with reference to FIGS. 2 and 3 .

2 is a circuit diagram of a pixel included in an electroluminescent display device according to an exemplary embodiment of the present invention. Hereinafter, for convenience of description, the structure and operation of the case where the electroluminescent display device according to an embodiment of the present invention is a 2T (transistor) 1C (capacitor) pixel circuit will be described, but the present invention is not limited thereto. .

Referring to FIG. 2 , in the electroluminescent display device 100 according to an exemplary embodiment of the present invention, one pixel includes a switching transistor (ST), a driving transistor (DT), a compensation circuit (not shown), and It may be configured to include a light emitting element (LE).

The light emitting element LE may operate to emit light according to a driving current formed by the driving transistor DT.

The switching transistor ST may perform a switching operation so that the data signal supplied through the data line 116 is stored in the capacitor C as a data voltage in response to the gate signal supplied through the gate line 117 .

The driving transistor 113 may operate to allow a constant driving current to flow between the high potential power line VDD and the low potential power line VSS in response to the data voltage stored in the capacitor 112 .

Here, the compensation circuit is a circuit for compensating for the threshold voltage of the driving transistor DT, and may include one or more thin film transistors and capacitors. The composition of the compensation circuit can be very diverse according to the compensation method.

As described above, in the electroluminescent display device 100 according to an embodiment of the present invention, one pixel includes a switching transistor ST, a driving transistor DT, a capacitor C, and a light emitting element LE. However, when a compensation circuit is added, it can be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

3 is a plan view schematically illustrating an electroluminescent display device according to an exemplary embodiment of the present invention.

4 and 5 are diagrams schematically showing a cross-sectional structure of the electroluminescent display device according to an exemplary embodiment of the present invention shown in FIG. 3 .

In this case, FIG. 3 schematically shows a planar structure of one pixel in the electroluminescent display device 100 according to an embodiment of the present invention. For convenience of description, FIG. 3 shows a case of a 2T1C structure including a switching transistor (ST), a driving transistor (DT), a capacitor (C), and a light emitting element (LE) for one pixel as an example. As described above, when a compensation circuit is added, it may be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and the like.

Further, FIG. 4 shows a circuit unit CA including a driving transistor DT and a capacitor and a light emitting element LE in the electroluminescent display device 100 according to an embodiment of the present invention shown in FIG. 3 . A part of the light emitting part EA and the crossing part IA of the gate line 117 and the data line 116 is shown as an example. In addition, FIG. 5 shows a cross section taken along the line II' of the electroluminescent display device 100 according to an embodiment of the present invention shown in FIG. 3 as an example, and the driving transistor DT A circuit portion CA including a capacitor, a light emitting portion EA including a light emitting element LE, and a portion of a data line area DA adjacent to two pixels are shown. In particular, FIG. 5 illustrates a case where a short circuit occurs between data lines 116 adjacent to two pixels as an example.

3 to 5 , the electroluminescent display device 100 according to an embodiment of the present invention includes a gate line (or scan line) 117, a data line 116, and a power line on a substrate 110. (or power supply voltage line) 119 may intersect to divide the pixel area AA. In addition, a sensing control line, a reference line, and the like may be further disposed.

The data line 116 and the power line 119 may be disposed on the substrate 110 in a first direction. The gate line 117 may be disposed in a second direction crossing the first direction to partition the pixel area AA together with the data line 116 and the power line 119 . For convenience, one pixel area AA can be divided into a light emitting unit EA through which the light emitting element LE emits light, and a circuit unit CA including a plurality of driving circuits for supplying driving current to the light emitting element LE.

The power line 119 may be arranged in one or more pixel areas AA, but the present invention is not limited thereto.

The data lines 116 may be arranged to be adjacent to each other with respect to neighboring pixels, but the present invention is not limited thereto.

In addition, a reference line may be disposed in the first direction on the same layer as the data line 116 and the power line 119 together with the data line 116 and the power line 119 .

In this case, the insulating layer between the adjacent data lines 116, for example, the buffer layer 115a and/or the interlayer insulating layer 115c may be removed to form the trench 140.

Trench 140 may be disposed along data line 116 .

The trench 140 may be vertically separated with the gate line 117 as the center.

A plurality of trenches 140 may be formed in upper and lower portions.

The trench 140 may be integrally provided along the data line 116 .

During patterning of the data line 116 , a remaining film 116 ′ remains between the adjacent data lines 116 and may be connected to any one of the adjacent data lines 116 .

The plurality of pixel areas AA may include a red sub-pixel area, a green sub-pixel area, a blue sub-pixel area, and a white sub-pixel area to form a unit pixel. Although only one arbitrary sub-pixel area AA is shown as an example in FIG. 3 , the present invention is not limited thereto. Each of these red, green, blue and white sub-pixel areas AA includes a light emitting element LE and a plurality of pixel driving circuits independently driving the light emitting element LE. The pixel driving circuit may include a switching transistor ST, a driving transistor DT, a capacitor C, and a sensing transistor (not shown).

The switching transistor ST is turned on when a scan pulse is supplied to the gate line 117 and transmits the data signal supplied to the data line 116 to the capacitor C and the first gate of the driving transistor DT. It can be supplied to the electrode 121. At this time, although not shown, the switching transistor ST includes a second gate electrode connected to the gate line 117 through the sixth contact hole, a second source electrode connected to the data line 116 through the seventh contact hole, and a second gate electrode connected to the data line 116 through the seventh contact hole. It may include a second drain electrode connected to the first gate electrode 121 through 8 contact holes and a second active layer.

Next, the driving transistor DT controls the current supplied from the power supply line 119 according to the driving voltage charged in the capacitor C, and supplies a current proportional to the driving voltage to the light emitting element LE, so that the light emitting element ( LE) to emit light. The driving transistor DT includes a first gate electrode 121 connected to the second drain electrode through the eighth contact hole, a first source electrode 122 connected to the power line 119 through the ninth contact hole, It may include a first drain electrode 123 and a first active layer 124 connected to the light emitting element LE through 5 contact holes.

The power line 119 may be connected to the first source electrode 122 of a neighboring pixel through a bridge wiring (not shown). The bridge wiring may extend to neighboring pixels in a direction parallel to the second direction. A bridge wire extending to a neighboring pixel may be connected to the first source electrode 122 of a neighboring pixel through a tenth contact hole. However, the present invention is not limited thereto.

One side of the bridge wiring may be connected to the lower power line 119 through an 11th contact hole.

Among them, the thin film transistor shown in FIGS. 4 and 5 is a driving transistor (DT), and has a top gate structure in which the first gate electrode 121 is disposed on the first active layer 124, particularly a thin film having a coplanar structure. Take a transistor as an example. However, the present invention is not limited thereto, and a thin film transistor having a bottom gate structure in which a gate electrode is disposed under an active layer may also be applied. In addition, the switching transistor ST may also have a top gate structure, a coplana structure, or a bottom gate structure.

The first gate electrode 121 of the driving transistor DT may overlap the first active layer 124 with a gate insulating layer 115b having substantially the same shape as the first gate electrode 121 interposed therebetween. The second gate electrode of the switching transistor ST may overlap the second active layer with a gate insulating layer 115b having substantially the same shape as the second gate electrode interposed therebetween.

Specifically, the first active layer 124 and the second active layer may be disposed on the substrate 110 .

In this case, a light blocking layer 125 may be disposed below the first active layer 124 , and a buffer layer 115a may be disposed between the first active layer 124 and the light blocking layer 125 .

The light blocking layer 125 may serve to block the first active layer 124 from being affected by external or surrounding light from light emitting devices, and may be disposed on the lowermost layer of the substrate 110 .

The data line 116 and the power line 119 of the present invention may be disposed in the first direction on the same layer as the light blocking layer 125 . That is, the data line 116 and the power supply line 119 of the present invention are disposed on the lowermost layer of the substrate 110 together with the light blocking layer 125.

This is achieved by arranging the vertical wiring of the data line 116 and the power supply line 119 on a layer different from that of the conventional one, so that there is a gap between the vertical wiring of the data line 116 and the power supply line 119 and the horizontal wiring of the gate line 117. This is to prevent a short circuit defect by interposing at least two insulating layers, for example, a buffer layer 115a and an interlayer insulating layer 115c, instead of a single interlayer insulating layer 115c (see FIG. 4 ).

The buffer layer 115a may be disposed on the substrate 110 to cover the light blocking layer 125 , the data line 116 , and the power line 119 .

Each of the first active layer 124 and the second active layer is formed to overlap the first gate electrode 121 and the second gate electrode on the gate insulating layer 115b, so that the first source electrode 122 and the first A channel may be formed between the drain electrode 123 and between the second source electrode and the second drain electrode.

The first active layer 124 and the second active layer may be formed using an oxide semiconductor including at least one metal selected from among Zn, Cd, Ga, In, Sn, Hf, and Zr, and may be formed using amorphous silicon. (amorphous silicon; a-Si), polycrystalline silicon; poly-Si, or organic semiconductors.

4 and 5 illustrate the case where the gate insulating layer 115b is limitedly formed under the first gate electrode 121 as an example, but the present invention is not limited thereto. The gate insulating layer 115b may be formed on the entire surface of the substrate 110 on which the first active layer 124 is formed. In this case, the first source electrode 122 and the first drain electrode 123 are formed on the gate insulating layer 115b. ) may be formed with contact holes for connecting each of the source and drain regions of the first active layer 124 .

The gate insulating layer 115b may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

The first gate electrode 121 and the second gate electrode are made of various conductive materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium. (Nd), and copper (Cu), or two or more alloys, or may be composed of multiple layers thereof.

An interlayer insulating layer 115c may be disposed on the first gate electrode 121 and the second gate electrode.

The interlayer insulating layer 115c may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). As shown in FIGS. 4 and 5 , the interlayer insulating layer 115c may be formed over the entire surface of the substrate 110 or only in the pixel area AA, but the present invention is not limited thereto.

A first source electrode 122, a first drain electrode 123, a second source electrode, and a second drain electrode are disposed on the interlayer insulating layer 115c above the first active layer 124 and the second active layer, respectively. can Each of the first source electrode 122 and the second source electrode is connected to the source regions of the first active layer 124 and the second active layer through a first contact hole and a third contact hole penetrating the interlayer insulating layer 115c. Each of the first drain electrode 123 and the second drain electrode may be connected to the first active layer 124 and the second drain electrode through a second contact hole and a fourth contact hole penetrating the interlayer insulating layer 115c. Each may be connected to the drain region of the active layer.

The second drain electrode of the switching transistor ST may extend in one direction and be electrically connected to the first gate electrode 121 of the driving transistor DT through a sixth contact hole.

In the case of an embodiment of the present invention, the gate line 117 may be disposed in the second direction on the same layer of the first source electrode 122, the second source electrode, and the first drain electrode 123 and the second drain electrode. (See Fig. 4).

As described above, in the electroluminescent display device 100 according to an embodiment of the present invention, vertical wires of the data line 116 and the power line 119 are disposed on the substrate 110 in the first direction, and the gate line ( 117) is arranged in a second direction crossing the first direction to divide the pixel area AA together with the vertical wires.

In the electroluminescent display device 100 according to an embodiment of the present invention, vertical wires of the data line 116 and the power supply line 119 are disposed on the same layer as the lowermost light blocking layer 125, and the gate line 117 By arranging the horizontal wiring on the same layer as the first source electrode 122/first drain electrode 123, there is at least an interlayer insulating layer 115c between the vertical wiring and the horizontal wiring instead of one existing interlayer insulating layer 115c. ) and the two insulating layers of the buffer layer 115a are interposed. Accordingly, it is possible to prevent a short-circuit defect occurring at the intersection of the vertical wiring and the horizontal wiring.

That is, conventionally, a gate redundancy pattern must be formed to repair a short-circuit defect between a horizontal wiring of a gate line and a vertical wiring of a data line/power line. Since only an interlayer insulating layer is interposed therebetween, electrostatic defects may occur due to a short separation distance, and a structure for repair should be designed in the pixel to improve yield. Accordingly, in the past, a gate redundancy pattern was applied to a position where horizontal wiring and vertical wiring intersect. However, as the gate redundancy pattern is formed to occupy a predetermined area above and below the gate line, it becomes a factor in reducing the aperture ratio in the pixel, and it is difficult to design pixels in a high-resolution model due to the addition of the gate redundancy pattern in the pixel.

Accordingly, in one embodiment of the present invention, the intersection point of the horizontal wiring and the vertical wiring is vulnerable to short circuit defects because only the interlayer insulating layer 115c is interposed therebetween, and such short circuit defects are affected by the separation distance between the wires. , by arranging the data line 116, the power supply line 119, and the gate line 117 on a layer different from the existing ones, at least two layers of the interlayer insulating layer 115c and the buffer layer 115a are formed between the horizontal wiring and the vertical wiring. It is characterized in that the insulating layer of the layer is configured to be interposed to prevent a short circuit defect.

As a result, it is possible to delete the gate redundancy pattern within the pixel, thereby providing an effect of facilitating pixel design in a high-resolution model, improving yield, and securing an additional aperture ratio.

In this specification, the thin film transistor has been described as having a coplanar structure, but the thin film transistor may be implemented in another structure such as a staggered structure.

Next, a protective layer 115d and a planarization layer 115e may be disposed on the thin film transistor. The protection layer 115d protects the gate driver and other wires disposed in addition to the thin film transistor and pixel area AA, and the planarization layer 115e flattens the top of the substrate 110 by smoothing the step difference on the substrate 110. can be formed to

The protective layer 115d may fill the inside of the trench 140 .

The planarization layer 115e may also fill the inside of the trench 140 .

At this time, even if the residual film 116' is connected to any one of the adjacent data lines 116, the trench 140 is adjacent to the passivation layer 115d and/or the planarization layer 115e. It may be separated from the other data line 116 of the data lines 116 that do.

A color filter layer may be disposed on the protective layer 115d of the light emitting unit EA.

The protective layer 115d may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). As shown in FIGS. 4 and 5 , the protective layer 115d may be formed over the entire surface of the substrate 110 or only in the pixel area AA, but the present invention is not limited thereto.

The planarization layer 115e may be made of an organic insulating material.

The planarization layer 115e may include acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, and photoresist. It may be formed in any one, but is not limited thereto.

The first drain electrode 123 may be connected to the anode 126 of the light emitting element LE through a fifth contact hole penetrating the passivation layer 115d and the planarization layer 115e.

Referring to FIGS. 4 and 5 , a light emitting element LE may be disposed on the planarization layer 115e. For example, as an organic light emitting element, the light emitting element LE is formed on the planarization layer 115e and is disposed on the anode 126 connected to the first drain electrode 123 of the driving transistor DT and the organic light emitting element 126. It may include a cathode 128 formed on the light emitting layer 127 and the organic light emitting layer 127 .

The anode 126 may be disposed on the planarization layer 115e and electrically connected to the first drain electrode 123 through a fifth contact hole formed in the planarization layer 115e. The anode 126 may be made of a conductive material having a high work function in order to supply holes to the organic light emitting layer 127 . The anode 126 is made of a transparent conductive material such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). can

3 to 5 show that the anode 126 is electrically connected to the first drain electrode 123 of the driving transistor DT as an example, but the present invention is not limited thereto, and the type and driving of the thin film transistor The anode 126 may be electrically connected to the first source electrode 122 of the driving transistor according to a circuit design method or the like.

The organic light emitting layer 127 is an organic layer for emitting light of a specific color, and may include any one of a red organic light emitting layer, a green organic light emitting layer, a blue organic light emitting layer, and a white organic light emitting layer. In addition, the organic emission layer 127 may further include various organic layers such as a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer. 3 to 5 illustrate that the organic light emitting layer 127 is patterned for each pixel, the present invention is not limited thereto, and the organic light emitting layer 127 may be a common layer commonly formed in a plurality of pixels.

A cathode 128 may be disposed on the organic light emitting layer 127 . The cathode 128 may supply electrons to the organic light emitting layer 127 . The cathode 128 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and tin. It may be made of a transparent conductive oxide based on oxide (Tin Oxide; TO) or a ytterbium (Yb) alloy. Alternatively, the cathode 128 may be made of a conductive material.

Next, referring to FIGS. 4 and 5 , a bank 115f may be disposed on the anode 126 and the planarization layer 115e. The bank 115f may cover a portion of the anode 126 of the organic light emitting device. The bank 115f may be arranged to distinguish adjacent pixels in the pixel area AA.

The bank 115f may be made of an organic insulating material. For example, the bank 115f may be made of polyimide, acryl, or benzocyclobutene (BCB)-based resin, but the present invention is not limited thereto.

The bank 115f may be disposed on the planarization layer 115e to surround the light emitting unit EA.

An encapsulation portion (not shown) may be formed above the organic light emitting device configured as described above to protect the organic light emitting device, which is vulnerable to moisture, from being exposed to moisture. For example, the encapsulation unit may have a structure in which an inorganic layer and an organic layer are alternately stacked. However, the present invention is not limited thereto.

Meanwhile, in the electroluminescent display device 100 according to an embodiment of the present invention, an insulating layer between adjacent data lines 116, for example, a buffer layer 115a and an interlayer insulating layer 115c are removed in advance to form a trench. ) 140 and then patterning the gate line 117 to automatically repair a short-circuit defect between adjacent data lines 116.

That is, in order to realize a high aperture ratio in a large screen and high resolution, it is necessary to reduce the wiring CD (Critical Dimension) and space, and accordingly, the distance between adjacent data lines gradually decreases, resulting in an increase in short-circuit defects between adjacent data lines. . For example, in the case of an 8K UHD (Ultra High Definition) model, the wiring space (or spacing) needs to be reduced to 6.0㎛ or less to secure the desired aperture ratio. defects may occur.

Commonly, a resolution of 3840x2160 (about 8.8 million pixels), which is four times that of FHD, is called 4K UHD, and a resolution of 7680x4320 (about 33 million pixels), which is four times higher than that, is called 8K UHD. 4K UHD is sometimes referred to as UHD, and 8K UHD as FUHD to make it more convenient. Of course, this is always a 16:9 ratio, and resolutions such as 4096x2196 with a 17:9 ratio, 4096x1716 with a 2.35:1 ratio, and 4096x3072 with a 4:3 ratio exist.

Accordingly, in one embodiment of the present invention, short-circuit defects between adjacent data lines 116 occur as the distance between the data lines 116 decreases, and according to the wiring structure described above, the adjacent data lines 116 Even if a short circuit between adjacent data lines 116 occurs with a remaining film 116' left between them, it can be automatically repaired during patterning of the gate line 117, so that the adjacent data lines 116 Disclosed is a structure and method capable of preventing inter-short circuit failure.

That is, the insulating layer between the adjacent data lines 116, for example, the buffer layer 115a and the interlayer insulating layer 115c are previously removed along the data line 116 to form a trench 140, and then By patterning the gate line 117, even if adjacent data lines 116 are short-circuited by the remaining film 116', part of the short-circuited portion during patterning of the gate line 117, that is, part of the remaining film 116' is removed together. Short-circuit defects between adjacent data lines 116 may be automatically repaired. At this time, even if the remaining film 116' is connected to any one of the adjacent data lines 116, the trench 140 and the passivation layer 115d and/or the planarization layer filled in the trench 140 ( 115e) may be separated from the other data line 116 of the adjacent data lines 116 .

Accordingly, the present invention provides an effect of preventing a defect in which the data lines 116 are short-circuited without adding a process even when the interval between adjacent data lines 116 is reduced in a high-resolution model.

3 shows an example in which the trench 140 according to an embodiment of the present invention is divided into two upper and lower parts centered on the gate line 117, but the present invention is not limited thereto. The trenches 140 according to an embodiment of the present invention may be formed in plurality even in the top and bottom, or may be integrally formed along the data line 116 .

Hereinafter, a method of manufacturing an electroluminescent display device according to an embodiment of the present invention will be described in detail with reference to the drawings.

6A to 6F are cross-sectional views sequentially illustrating manufacturing processes of the electroluminescent display device according to the exemplary embodiment shown in FIG. 5 .

Referring to FIG. 6A , vertical wiring of a data line 116 and a power line (not shown) and a light blocking layer 125 may be formed on a substrate 110 .

In this case, the light-blocking layer 125 may serve to block the first active layer from being affected by external or surrounding light from light emitting devices, and may be disposed on the lowermost layer of the substrate 110 . A portion of the light blocking layer 125 may form a first storage electrode for forming a first capacitor.

The power line may be disposed in each of one or more pixel areas, but the present invention is not limited thereto.

The data lines 116 may be formed to be adjacent to each other in adjacent pixel areas, but the present invention is not limited thereto.

Along with the data line 116 and the power line, a reference line may be formed in the first direction on the same layer as the data line 116 and the power line.

As such, the data line 116 and the power supply line according to the present invention are disposed on the lowermost layer of the substrate 110 together with the light blocking layer 125.

The data line 116, the power line, and the light blocking layer may be formed by stacking and forming a first metal layer on the substrate 110 and then selectively patterning the first metal layer through a mask process using a mask.

At this time, as a high aperture ratio is implemented in a large screen and high resolution, the wiring CD (Critical Dimension) is reduced and the distance between adjacent data lines 116 is reduced. As a result, when the data lines 116 are patterned, a residual film 116' may remain between adjacent data lines 116 .

The mask process refers to a series of processes in which a photoresist film is formed on a substrate, exposed and developed using a mask to form a predetermined photoresist film pattern, and then an etching process is performed using the photoresist film pattern as an etching mask.

The first metal layer may include various conductive materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper ( Cu), or two or more alloys, or a multilayer thereof.

Also, referring to FIG. 6B , a buffer layer 115a may be formed on the substrate 110 on which the data line 116, the power supply line, and the light blocking layer 125 are formed.

After that, the first active layer 124 and the second active layer may be formed on the substrate 110 .

A second storage electrode made of a semiconductor material constituting the first active layer 124 and the second active layer may be formed on the same layer as the first active layer 124 and the second active layer. A second storage electrode is disposed on the first storage electrode with the buffer layer 115a interposed therebetween to form a first capacitor.

The first active layer 124 and the second active layer may be formed using an oxide semiconductor including at least one metal selected from among Zn, Cd, Ga, In, Sn, Hf, and Zr, and may be formed using amorphous silicon. (amorphous silicon; a-Si), polycrystalline silicon; poly-Si, or organic semiconductors.

After the first active layer 124 and the second active layer are formed on the substrate 110 as described above, referring to FIG. 6C , a predetermined insulating layer may be formed on the entire surface of the substrate 110 .

The insulating layer may be composed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

Then, a second metal layer may be formed on the entire surface of the substrate 110 on which the insulating layer is formed.

The second metal layer may include various conductive materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). ), or may be composed of two or more alloys, or multilayers thereof.

Thereafter, the insulating layer and the second metal layer may be patterned through a mask process to form the first gate electrode 121 made of the second metal layer on the first active layer 124 . In addition, a second gate electrode made of a second metal layer may be formed on the second active layer.

At the same time, a gate insulating layer 115b made of an insulating layer may be formed under the first gate electrode 121 and the second gate electrode.

Next, referring to FIG. 6D , an interlayer insulating layer 115c may be formed on the entire surface of the substrate 110 .

The interlayer insulating layer 115c may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

Thereafter, the interlayer insulating layer 115c and the buffer layer 115a are selectively patterned through a mask process so that the first contact hole 140a and the second contact hole 140a exposing the source region and the drain region of the first active layer 124, respectively. A sixth contact hole and a seventh contact hole exposing the hole 140b and the source and drain regions of the second active layer, respectively, are formed. In addition, the trench 140 may be formed by removing the insulating layer between the adjacent data lines 116 through the above-described mask process, for example, the buffer layer 115a and/or the interlayer insulating layer 115c.

In this case, if the residual film 116' remains between the adjacent data lines 116, it may be exposed to the outside through the trench 140. However, adjacent data lines 116 may still be electrically connected to each other by the residual film 116'.

Trench 140 may be formed along data line 116 .

The trench 140 may be vertically separated and formed centering on the gate line.

A plurality of trenches 140 may be formed in upper and lower portions.

The trench 140 may be integrally formed along the data line 116 .

Next, a third metal layer may be formed on the entire surface of the substrate 110 .

The third metal layer may include various conductive materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). ), or may be composed of two or more alloys, or multilayers thereof.

Thereafter, the third metal layer is patterned through a mask process to form the first source electrode 122, the first drain electrode 123, and the second metal layer respectively formed of the third metal layer on the first active layer 124 and the second active layer. A source electrode and a second drain electrode may be formed. At this time, each of the first source electrode 122 and the second source electrode is the source of the first active layer 124 and the second active layer through the first contact hole and the sixth contact hole penetrating the interlayer insulating layer 115c. region, and each of the first drain electrode 123 and the second drain electrode connects to the first active layer 124 and the second active layer through a second contact hole and a seventh contact hole penetrating the interlayer insulating layer 115c. It can be connected to the drain region of the layer.

A gate line may be formed on the same layer as the first source electrode 122 and the first drain electrode 123 and the second source electrode and the second drain electrode.

When forming the gate line, the first source electrode 122 and the first drain electrode 123, and the second source electrode and the second drain electrode, a portion of the remaining film 116' exposed by the trench 140 is removed together. Accordingly, adjacent data lines 116 may be electrically separated from each other.

In addition, in the electroluminescent display device according to an embodiment of the present invention, vertical wiring is disposed on the same layer as the lowermost light blocking layer 125, and horizontal wiring of the gate line 117 is separated from the first source electrode 122. By disposing the first drain electrode 123 and the second source electrode on the same layer as the second drain electrode, a buffer layer 115a other than the existing interlayer insulating layer 115c may be further interposed between the vertical wiring and the horizontal wiring. there is. Therefore, the separation distance between the vertical and horizontal wires increases. In particular, since the buffer layer 115a has nothing to do with the capacitance of the capacitor, increasing the thickness of the buffer layer 115a results in a short-circuit defect occurring at the intersection of the vertical and horizontal wires. can prevent

As a result, it is possible to delete the gate redundancy pattern within the pixel, thereby providing an effect of facilitating pixel design in a high-resolution model, improving yield, and securing an additional aperture ratio.

Next, referring to FIG. 6F , a protective layer 115d may be formed on the substrate 110 .

The protective layer 115d may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). As shown in FIG. 6F , the protective layer 115d may be formed over the entire surface of the substrate 110 or only in the pixel area, but the present invention is not limited thereto.

Thereafter, the protective layer 115d may be selectively patterned through a mask process to form a fifth contact hole exposing a portion of the first drain electrode 123 .

In this case, a color filter layer may be formed on the protective layer 115d of the light emitting unit.

After that, a planarization layer 115e may be formed on the substrate 110 .

The passivation layer 115d and/or the planarization layer 115e may fill the trench 140 .

The planarization layer 115e may be made of an organic insulating material.

The planarization layer 115e may include acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, and photoresist. It may be formed in any one, but is not limited thereto.

Next, a light emitting device may be formed on the substrate 110 . For example, as an organic light emitting device, the light emitting device includes an anode 126 formed on the planarization layer 115e and electrically connected to the first drain electrode 123 of the driving transistor, an organic light emitting layer 127 disposed on the anode 126, and It may include a cathode 128 formed on the organic light emitting layer 127 .

That is, an anode 126 connected to the first drain electrode 123 may be formed on the planarization layer 115e.

The anode 126 may be made of a conductive material having a high work function in order to supply holes to the organic light emitting layer 127 . The anode 126 is made of a transparent conductive material such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). can

The first drain electrode 123 may be connected to the anode 126 of the light emitting device through the second contact hole.

The organic light emitting layer 127 is an organic layer for emitting light of a specific color, and may include any one of a red organic light emitting layer, a green organic light emitting layer, a blue organic light emitting layer, and a white organic light emitting layer. In addition, the organic emission layer 127 may further include various organic layers such as a hole transport layer, a hole injection layer, an electron injection layer, and an electron transport layer. In FIG. 8I, the organic emission layer 127 is formed in common with a plurality of pixels as an example, but the present invention is not limited thereto.

A cathode 128 may be formed on the organic light emitting layer 127 . The cathode 128 may supply electrons to the organic light emitting layer 127 . The cathode 128 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and tin. It may be made of a transparent conductive oxide based on oxide (Tin Oxide; TO) or a ytterbium (Yb) alloy. Alternatively, the cathode 128 may be made of a conductive material.

An encapsulation portion (not shown) may be formed above the organic light emitting device configured as described above to protect the organic light emitting device, which is vulnerable to moisture, from being exposed to moisture. For example, the encapsulation unit may have a structure in which an inorganic layer and an organic layer are alternately stacked. However, the present invention is not limited thereto.

Meanwhile, as described above, the trench of the present invention may be integrally formed along the data line, and in this case, a short circuit defect between adjacent data lines can be more effectively prevented. It is explained in detail through an example.

7 is a plan view schematically illustrating an electroluminescent display device according to another exemplary embodiment of the present invention.

At this time, the electroluminescence display device 200 according to another embodiment of the present invention shown in FIG. 7 is substantially identical to the electroluminescence display device according to the above-described embodiment of the present invention except for the configuration of the trench 240. has the same composition as

7 schematically shows a planar structure of one pixel in the electroluminescent display device 200 according to another embodiment of the present invention. For convenience of explanation, FIG. 7 shows a case in which one pixel is configured with a 2T1C structure including a switching transistor ST, a driving transistor DT, a capacitor C, and a light emitting element LE as an example. As described above, when a compensation circuit is added, it may be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and the like.

Referring to FIG. 7 , an electroluminescent display device 200 according to another embodiment of the present invention includes a gate line (or scan line) 217, a data line 216 and a power line (or power voltage) on a substrate. Lines 219 may intersect to divide the pixel area AA. In addition, a sensing control line, a reference line, and the like may be further disposed.

The data line 216 and the power line 219 may be disposed on the substrate in a first direction. The gate line 217 may be disposed in a second direction crossing the first direction to partition the pixel area AA together with the data line 216 and the power line 219 . For convenience, one pixel area AA can be divided into a light emitting unit EA through which the light emitting element LE emits light, and a circuit unit CA including a plurality of driving circuits for supplying driving current to the light emitting element LE.

The power line 219 may be arranged in one or more pixel areas AA, but the present invention is not limited thereto.

The data lines 216 may be arranged to be adjacent to each other with respect to neighboring pixels, but the present invention is not limited thereto.

In addition, a reference line may be disposed in the first direction on the same layer as the data line 216 and the power line 219 together with the data line 216 and the power line 219 .

In this case, an insulating layer between adjacent data lines 216 , for example, a buffer layer and/or an interlayer insulating layer may be removed to form the trench 240 .

Trench 240 may be disposed along data line 216 .

In particular, the trench 240 according to another embodiment of the present invention is characterized in that it is integrally formed along the data line 216 . However, the present invention is not limited thereto.

While patterning the data lines 216 as in the above-described embodiment of the present invention, a residual film remains between the adjacent data lines 216, and any one data line 216 among the adjacent data lines 216 can be connected to

The plurality of pixel areas AA may include a red sub-pixel area, a green sub-pixel area, a blue sub-pixel area, and a white sub-pixel area to form a unit pixel. Although only one arbitrary sub-pixel area AA is illustrated as an example in FIG. 7 , the present invention is not limited thereto. Each of these red, green, blue and white sub-pixel areas AA includes a light emitting element LE and a plurality of pixel driving circuits independently driving the light emitting element LE. The pixel driving circuit may include a switching transistor ST, a driving transistor DT, a capacitor C, and a sensing transistor (not shown).

The switching transistor ST is turned on when a scan pulse is supplied to the gate line 217 and transmits the data signal supplied to the data line 216 to the capacitor C and the first gate of the driving transistor DT. electrodes can be supplied.

Next, the driving transistor DT controls the current supplied from the power supply line 219 according to the driving voltage charged in the capacitor C, and supplies a current proportional to the driving voltage to the light emitting element LE, so that the light emitting element ( LE) to emit light.

The power line 219 may be connected to the first source electrode 222 of a neighboring pixel through a bridge wire (not shown). The bridge wiring may extend to neighboring pixels in a direction parallel to the second direction.

Although not shown, the first active layer and the second active layer may be disposed on the substrate.

In this case, a light blocking layer may be disposed below the first active layer, and a buffer layer may be disposed between the first active layer and the light blocking layer.

The light-blocking layer may serve to block the first active layer from being affected by external or surrounding light from light emitting devices, and may be disposed on the lowermost layer of the substrate.

The data line 216 and the power line 219 of the present invention may be disposed in the first direction on the same layer as the light blocking layer. That is, the data line 216 and the power supply line 219 of the present invention are characterized in that they are disposed on the lowermost layer of the substrate together with the light blocking layer.

This is achieved by arranging the vertical wiring of the data line 216 and the power supply line 219 on a different layer from the conventional one, so that there is a gap between the vertical wiring of the data line 216 and the power supply line 219 and the horizontal wiring of the gate line 217. This is to prevent a short circuit defect by interposing at least two insulating layers, for example, a buffer layer and an interlayer insulating layer, instead of a single interlayer insulating layer.

A buffer layer may be disposed on the substrate to cover the light blocking layer and the data line 216 and power line 219 .

A gate insulating layer may be limitedly formed below the first gate electrode and the second gate electrode. However, the present invention is not limited thereto.

An interlayer insulating layer may be disposed on the first gate electrode and the second gate electrode.

A first source electrode, a first drain electrode, a second source electrode, and a second drain electrode may be disposed on the interlayer insulating layer above the first active layer and the second active layer, respectively.

The second drain electrode of the switching transistor ST may extend in one direction and be electrically connected to the first gate electrode of the driving transistor DT.

In the case of another embodiment of the present invention, the gate line 217 may be disposed in the second direction on the same layer of the first source electrode, the second source electrode, and the first drain electrode and the second drain electrode.

Next, a protective layer and a planarization layer may be disposed on the thin film transistor. The protective layer may protect gate drivers and other lines disposed in addition to the thin film transistor and the pixel area AA, and the planarization layer may be formed to flatten the top of the substrate by smoothing the step difference on the substrate.

The protective layer may fill the inside of the trench 240 .

A planarization layer may also fill the inside of the trench 240 .

At this time, even if a remaining film is connected to any one of the adjacent data lines 216, the other one of the adjacent data lines 216 is formed by the trench 240 and the passivation layer and/or the planarization layer. can be separated from the data line 216 of

A color filter layer may be disposed on the protective layer of the light emitting unit EA.

A light emitting element LE may be disposed on the planarization layer. For example, as an organic light emitting device, the light emitting device LE may include an anode formed on a planarization layer and connected to the first drain electrode of the driving transistor DT, an organic light emitting layer disposed on the anode, and a cathode formed on the organic light emitting layer. can

A bank may be disposed over the anode and planarization layer. The bank may cover a portion of the anode of the organic light emitting device. The banks may be arranged to distinguish adjacent pixels in the pixel area AA.

The bank may be disposed on the planarization layer to surround the light emitting unit EA.

An encapsulation portion (not shown) may be formed above the organic light emitting device configured as described above to protect the organic light emitting device, which is vulnerable to moisture, from being exposed to moisture. For example, the encapsulation unit may have a structure in which an inorganic layer and an organic layer are alternately stacked. However, the present invention is not limited thereto.

An exemplary embodiment of the present invention may be described as follows.

An electroluminescent display device according to an embodiment of the present invention includes a data line and a gate line crossing each other on a substrate to partition a pixel area, a thin film transistor disposed in a circuit part of the pixel area, and a light emitting element disposed in the light emitting part of the pixel area. Including, the data lines are disposed adjacent to each other in adjacent pixel areas, and an insulating layer between adjacent data lines may be removed to form a trench.

According to another feature of the present invention, the data lines may be disposed on the substrate in a first direction, and the gate lines may be disposed in a second direction crossing the first direction with an insulating layer interposed therebetween.

According to another feature of the present invention, the electroluminescent display device may further include a power line disposed in a direction parallel to the first direction on the same layer as the data line.

According to another feature of the present invention, the electroluminescent display device further includes a light blocking layer disposed below the thin film transistor, and the data line may be disposed on the same layer as the light blocking layer.

According to another feature of the present invention, the insulating layer may include a buffer layer and/or an interlayer insulating layer.

According to another feature of the present invention, a trench may be disposed along the data line.

According to another feature of the present invention, the trenches may be vertically separated with the gate line as the center.

According to another feature of the present invention, a plurality of trenches may be formed in the upper and lower portions.

According to another feature of the present invention, the trench may be integrally provided along the data line.

According to another feature of the present invention, the electroluminescent display device may further include another insulating layer that is disposed on the thin film transistor and fills the inside of the trench.

According to another feature of the present invention, the other insulating layer may include a protective layer and/or a planarization layer.

According to another feature of the present invention, the electroluminescent display device may further include a remaining film connected to any one of the adjacent data lines between adjacent data lines.

According to another feature of the present invention, the remaining film may be separated from another one of the adjacent data lines by an insulating layer different from the trench.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. The protection scope of the present invention should be construed according to the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100,200: electroluminescence display
115a: buffer layer
115b: gate insulating layer
115c: interlayer insulating layer
115d: protective layer
115e: planarization layer
115f: bank
116,216: data line
117,217: gate line
119,219: power line
125: light blocking layer
126 anode
127 organic light emitting layer
128: cathode
140,240: trench

Claims (13)

a data line disposed on a substrate; a thin film transistor disposed above the substrate on which the data line is disposed and including an active layer, a gate electrode, a source electrode, and a drain electrode;
a gate line disposed on the same layer as the source electrode and the drain electrode and crossing the data line to define a pixel area; and
A light emitting element disposed in a light emitting part of the pixel region,
The pair of data lines are disposed adjacent to each other in the adjacent pixel area;
wherein an insulating layer between the pair of adjacent data lines is removed to form a trench. According to claim 1,
The data line is disposed on the substrate in a first direction,
The gate line is disposed on the data line in a second direction crossing the first direction with the insulating layer interposed therebetween. According to claim 2,
The electroluminescent display device further comprises a power line disposed in a direction parallel to the first direction on the same layer as the data line. According to claim 1,
Further comprising a light blocking layer disposed under the thin film transistor,
The data line is disposed on the same layer as the light blocking layer. According to claim 2,
The insulating layer includes a buffer layer and/or an interlayer insulating layer. According to claim 1,
The trench is disposed along the data line. According to claim 6,
The trench is vertically separated with respect to the gate line. According to claim 7,
The electroluminescent display device of claim 1 , wherein a plurality of trenches are formed in the upper and lower portions. According to claim 1,
The trench is integrally provided along the data line. According to claim 1,
and another insulating layer disposed on the thin film transistor and filling an inside of the trench. According to claim 10,
The other insulating layer includes a passivation layer and/or a planarization layer. According to claim 10,
and a remaining film between the pair of adjacent data lines and connected to one of the pair of adjacent data lines. According to claim 12,
wherein the remaining film is separated from another one of the pair of adjacent data lines by the trench and the other insulating layer.

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