KR102498500B1 - Organic Light Display Device - Google Patents

Abstract

The organic light emitting display device of the present invention includes a driving transistor, a capacitor, and first to third controllers that control driving current of the organic light emitting diode. The driving transistor includes a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to the third node. A capacitor is connected between the first node and the sharing node. During the initialization period, the first controller connects the shared node and the high-potential voltage line. The second control unit connects the sharing node and the initialization voltage line during the sensing period following the initialization period. The third controller connects the common node and the high-potential voltage line during the light-emitting period following the sensing period.

Description

Organic light display device {Organic Light Display Device}

The present invention relates to an organic light emitting display device.

A flat panel display (FPD) is widely used in portable computers such as laptop computers and tablets as well as desktop computer monitors and mobile phone terminals due to advantages of miniaturization and light weight. Currently, various types of display devices, such as curved displays, flexible displays, rollable displays, and wearable displays, as well as flat panel displays are being developed. there is. These display devices are liquid crystal displays {Liquid Crystal Display; LCD), Plasma Display Panel (PDP), Field Emission Display; FED), Organic Light Emitting Diode Display (OLED), and Quantum Dot Display (QD).

Among them, the organic light emitting display device has advantages such as a fast response speed, high luminance with high luminous efficiency, and a large viewing angle. In general, an organic light emitting display device uses a transistor turned on by a scan signal to apply a data voltage to a gate electrode of a driving transistor, and charges a storage capacitor with the data voltage supplied to the driving transistor. Then, the organic light emitting diode emits light by outputting the data voltage charged in the storage capacitor using the emission control signal.

In the organic light emitting display device, luminance non-uniformity may occur due to process variation or driving characteristics. As one of the causes of non-uniformity in luminance, internal compensation methods for compensating for electrical characteristics of a driving transistor are known.

However, in the organic light emitting diode display, the magnitude of the driving current applied to the organic light emitting diode may vary depending on the voltage drop of the high potential voltage in addition to the electrical characteristics of the driving transistor. The luminance non-uniformity due to the voltage drop of the high potential voltage appears as a bigger problem as the size of the display panel increases and the resolution increases.

In addition, since a large number of transistors are required for internal compensation, there is a disadvantage in that the size of pixels increases and the manufacturing cost increases.

An object of the present invention is to provide an organic light emitting display device capable of improving a change in luminance emitted by pixels due to a voltage drop of a high potential voltage.

An object of the present invention is to provide an organic light emitting display device suitable for high resolution while reducing manufacturing cost by reducing the size of a pixel.

The organic light emitting display device of the present invention includes a driving transistor, a capacitor, and first to third controllers that control driving current of the organic light emitting diode. The driving transistor includes a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to the third node. A capacitor is connected between the first node and the sharing node. During the initialization period, the first controller connects the shared node and the high-potential voltage line. The second control unit connects the sharing node and the initialization voltage line during the sensing period following the initialization period. The third controller connects the common node and the high-potential voltage line during the light-emitting period following the sensing period.

In the organic light emitting display device according to the present invention, the voltage difference between the gate electrode and the source electrode of the driving transistor during the emission period is not affected by the parameter of the high potential voltage, thereby improving the luminance deviation caused by the high potential voltage deviation. can do.

Also, in the organic light emitting display device according to the present invention, a plurality of pixels disposed on a pixel line share a common node control unit that controls a gate electrode voltage of a driving transistor, so that the size of each pixel can be reduced.

1 is a block diagram showing the configuration of an organic light emitting display device according to the present invention.
2 is a block diagram showing the configuration of a shift register.
3 is a diagram showing a part of a pixel array according to the first embodiment.
FIG. 4 is a diagram illustrating one pixel shown in FIG. 3 .
FIG. 5 is a timing diagram illustrating gate signals for driving the pixel shown in FIG. 4 and voltage changes of main nodes.
6 to 8 are diagrams for explaining pixel driving according to operation timing.
9 is a diagram showing a part of a pixel array according to a second embodiment.

Advantages and features of this specification, and methods of achieving them, will become clear with reference to embodiments described below in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments make the disclosure of this specification complete, and the common knowledge in the technical field to which this specification belongs. It is provided to fully inform the owner of the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, so this specification is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

Each feature of the various embodiments of the present specification can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in an association relationship. may be

Switch elements in the gate driving circuit of the present specification may be implemented as n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors. Although a p-type transistor was exemplified in the following embodiments, the present specification is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in an n-type MOSFET, the direction of the current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. The source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on the applied voltage. The invention is not limited by the sources and drains of the transistors in the following embodiments.

1 is a diagram showing the configuration of a display device according to the present specification.

Referring to FIG. 1 , an organic light emitting display device according to the present specification includes a display panel 100 in which pixels P are arranged in a matrix form, a data driver 120, gate drivers 130 and 140, and a timing controller 110. provide

The display panel 100 includes a pixel array 100A on which pixels P are disposed to display an image, and a non-display portion 100B on which a gate driving circuit 140 is disposed and does not display an image.

The pixel array 100A includes a plurality of pixels P, and displays an image based on a gray level displayed by each pixel P. The pixels P are arranged along the first to nth pixel lines HL1 to HLn. Each pixel P is connected to a data line DL arranged along a column line and connected to a gate line GL arranged along a pixel line HL. That is, pixels disposed on the same pixel line share the same gate line GL and are simultaneously driven. Further, when pixels disposed on the first pixel line HL1 are defined as first pixels P1 and pixels disposed on the n-th pixel line HLn are defined as n-th pixels Pn, the first pixel The n-th pixels Pn from P1 are sequentially driven. Also, a sampling period for writing data into one scan line may be defined as one horizontal period (1H).

The gate line GL may include an emission line and a plurality of scan lines according to a pixel structure.

The timing controller 110 controls driving timings of the data driver 120 and the gate driver 130 and 140 . The timing controller 110 rearranges digital video data (RGB) input from the outside according to the resolution of the display panel 100 and supplies it to the data driver 120 . In addition, the timing controller 110 operates the data driver 120 based on timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the gate driver are generated.

The data driver 120 is for driving the data line unit DL. To this end, the data driver 120 converts the digital video data RGB input from the timing controller 110 into an analog data voltage based on the data control signal DDC and supplies it to the data lines DL.

The gate drivers 130 and 140 include a level shifter 130 and a shift register 140 . The level shifter 130 is formed in the form of an IC on a printed circuit board (not shown) connected to the display panel 100, and the gate driving circuit 140 is a GIP circuit in the non-display area 100B of the display panel 100. can be formed as

The level shifter 130 levels-shifts the clock signals and the start signal VST under the control of the timing controller 110 and supplies them to the shift register 140 . The gate driving circuit 140 is formed by a combination of a plurality of thin film transistors (hereinafter referred to as transistors) in the non-display area 100B of the display panel 100 by the GIP method.

The shift register 140 may include a scan signal generator for outputting a scan signal and an emission signal generator for outputting an emission signal. The scan signal generating unit and the emission signal generating unit may be formed of a shift register including a plurality of stages connected to each other dependently.

2 is a block diagram showing the configuration of a shift register.

Referring to FIG. 2 , the shift register 140 includes an emission signal generator 141 and a scan signal generator 143 .

The emission signal generating unit 141 includes first to nth emission drivers EMD1 to EMDn connected to each other dependently. The first emission driver EMD1 generates the first emission signal EM1 and applies the first emission signal EM1 to the emission line of the first pixel line HL1. The second emission driver EMD2 generates the second emission signal EM2 and applies the second emission signal EM2 to the emission line of the second pixel line HL2. The nth emission driver EMDn generates the nth emission signal EMn and applies the nth emission signal EMn to the emission line of the nth pixel line HLn.

The first emission driver EMD1 operates by receiving the start signal, and the second emission driver EMD2 to the nth emission driver EMD(n) generate an output signal of the previous emission driver, that is, the emission It operates by receiving a signal as a carry signal.

The scan signal generation unit 143 includes first to nth scan drivers SD1 to SDn connected to each other in a dependent manner. The first scan driver SD1 generates a first scan signal SCAN1 and applies the first scan signal SCAN1 to the scan line of the first pixel line HL1. The second scan driver SD2 generates the second scan signal SCAN2 and applies the second scan signal SCAN2 to the scan line of the second pixel line HL2. Similarly, the nth scan driver SDn generates the nth scan signal SCAN(n) and applies the nth scan signal SCAN(n) to the scan lines of the nth pixel line HLn.

The first scan driver (SD1) operates by receiving the start signal, and the second scan driver (SD2) to nth scan driver (SD(n)) convert the output signal of the previous scan driver, that is, the scan signal, into a carry signal. It works by receiving authorization.

3 is a diagram showing a part of a pixel array according to the first embodiment. FIG. 4 is a diagram illustrating one pixel shown in FIG. 3 .

Referring to FIGS. 3 and 4 , first to third pixels P1 , P2 , and P3 disposed on the same pixel line are disposed adjacent to each other. Each of the first to third pixels P1, P2, and P3 includes a shared node controller Psh and a unit pixel Pcom. The shared node controller Psh includes first to third controllers T5, T6, and T7. The unit pixel Pcom includes an organic light emitting diode OLED, a driving transistor DT, first to fourth transistors T1, T2, T3, and T4, and a capacitor Cst.

The driving transistor DT controls the driving current applied to the organic light emitting diode OLED according to its source-gate voltage Vsg. The gate electrode of the driving transistor DT is connected to the first node N1, the source electrode is connected to the second node N2, and the drain electrode is connected to the third node N3. The first transistor T1 connects the first node N1 and the second node N2 in response to the nth scan signal SCAN(n). The second transistor T2 connects the data line DL and the third node N3 in response to the nth scan signal SCAN(n). The third transistor T3 connects the initialization voltage line VL and the first node N1 in response to the (n−1)th scan signal SCAN(n−1). The fourth transistor T4 connects the second node N2 and the input terminal of the high potential driving voltage VDD in response to the nth emission signal EM(n). The capacitor Cst is connected between the first node N1 and the sharing node N4 (hereinafter referred to as a fourth node).

The first control unit T5 (hereinafter referred to as a fifth transistor) connects the fourth node N4 and the high potential voltage line VDDL in response to the (n−1)th scan signal SCAN(n−1). let it The second controller T6 (hereinafter referred to as a sixth transistor) connects the fourth node N4 to the initialization voltage line VL in response to the nth scan signal SCAN(n). The third controller T7 (hereinafter referred to as a seventh transistor) connects the fourth node N4 and the high potential voltage line VDDL in response to the nth emission signal EM(n).

FIG. 5 is a diagram illustrating gate signals applied to the pixels shown in FIG. 4 and voltage changes of main nodes. FIG. 6 is a diagram illustrating an operation of a pixel in an initial period, FIG. 7 is a diagram illustrating an operation of a pixel in a sensing period, and FIG. 8 is a diagram illustrating an operation of a pixel in an emission period.

Referring to FIGS. 4 to 6 , in the initialization period Ti, the (n−1)th scan signal SCAN(n−1) becomes a turn-on voltage.

The third transistor T3 applies the initialization voltage Vini to the first node N1 in response to the (n−1)th scan signal SCAN(n−1). The fifth transistor T5 applies the high potential voltage VDD to the fourth node N4 in response to the (n−1)th scan signal SCAN(n−1).

Referring to FIGS. 4, 5, and 7, in the sensing period Ts, the nth scan signal SCAN(n) becomes a turn-on voltage.

In response to the nth scan signal SCAN(n), the first transistor T1, the second transistor T2, and the sixth transistor are turned on.

The sixth transistor T6 applies the initialization voltage Vini to the fourth node N4 in response to the nth scan signal SCAN(n). The voltage of the fourth node N4 decreases from the high potential voltage VDD to the initialization voltage Vini, so that the voltage change amount of the fourth node N4 becomes “VDD-Vini”.

Due to the coupling phenomenon of the capacitor Cst, the voltage of the first node N1 is changed by the amount of change in the voltage of the fourth node N4. That is, since the voltage of the first node N1 decreases by the voltage of “VDD-Vini” from the initialization voltage Vini, it becomes the voltage of “Vini-(VDD-Vini)”. At the start of the sensing period Ts, the voltage level of the first node N1, “2Vini-VDD,” is set to be a turn-on voltage. As a result, the driving transistor DT is turned on.

The second transistor T2 applies the data voltage Vdata to the third node N3 in response to the nth scan signal SCAN(n). The voltage of the third node N3 becomes the data voltage Vdata.

Since the fourth transistor T4 is turned off, the second node N2 is in a floating state, and the voltage level of the second node N2 gradually rises due to the current passing through the second node N2. . Since the first transistor T1 is turned on in response to the nth scan signal SCAN(n), current flows to the first node N1 via the second node N2. Accordingly, the voltage of the first node N1 gradually rises. The voltage of the first node N1 rises until it reaches "Vdata+Vth", the sum of the data voltage Vdata and the driving transistor threshold voltage Vth.

During the sensing period Ts, the third node N3 connected to the anode electrode of the organic light emitting diode OLED is initialized to the data voltage Vdata.

Referring to FIGS. 4, 5, and 8, in the light emission period Tem, the nth emission signal EM(n) becomes a turn-on voltage.

The seventh transistor T7 applies the high potential voltage VDD to the fourth node N4 in response to the nth emission signal EM(n). During the sensing period Ts, the voltage of the fourth node N4, which was the initialization voltage Vini, rises to the high potential voltage VDD. That is, at the start of the light emitting period Tem, the voltage of the fourth node N4 changes by "VDD-Vini".

Due to the coupling phenomenon, the voltage of the first node N1 is changed by the amount of change in the voltage of the fourth node N4. That is, the voltage of the first node N1 becomes "Vdata+Vth+VDD-Vini".

The fourth transistor T4 connects the high potential voltage line VDDL and the second node N2 in response to the nth emission signal EM(n). As a result, the source voltage of the driving transistor DT becomes the high potential voltage VDD. During the light emission period Tem, the gate-source voltage of the driving transistor DT becomes a turn-on voltage, and a driving current Ioled is generated from the second node N2 via the third node N3.

A relational expression for the driving current Ioled flowing through the organic light emitting diode OLED during the light emitting period Pem is as shown in Equation 1 below.

[Equation 1]

I _OLED =k/2(Vgs-Vth) ² = k/2(Vg-Vs-Vth) ²

= k/2{(Vdata+Vth+VDD-Vini)-VDD-Vth)} ²

=k/2(Vdata-Vini) ²

In Equation 1, k/2 represents a proportionality constant determined by the electron mobility, parasitic capacitance, and channel capacitance of the driving transistor DT. As a result, during the light emitting period Te, the driving current Ioled flowing through the organic light emitting diode OLED is not affected by the high potential voltage VDD as well as the threshold voltage Vth of the driving transistor DT.

A general organic light emitting display device using an internal compensation method improves a threshold voltage deviation of the driving transistor DT, but fails to compensate for a deviation of the high potential voltage VDD. Since the high potential voltage VDD is a constant potential voltage, all pixels P of the pixel array 100A must receive the same voltage.

However, a plurality of pixels are connected to the high potential voltage line VDDL, and each pixel is turned on for most of the period except for the initialization period Ti and the sensing period Ts. Therefore, current flows from the high potential voltage line VDDL to each pixel P, and the voltage of the high potential voltage VDD due to 'IR drop' according to the position of the high potential voltage line VDDL. descent occurs. As a result, the high potential voltage VDD applied to the pixels P is slightly different, and the magnitude of the driving current flowing through the organic light emitting diode OLED is also different. As a result, a problem in that luminance varies due to a deviation of the high potential voltage VDD may occur.

In contrast, the present invention controls the voltage of the gate electrode of the driving transistor DT by using the coupling phenomenon of the capacitor Cst connected to the gate electrode of the driving transistor DT, thereby increasing the driving current during the light emission period Tem. is not affected by the high potential voltage (VDD). As a result, it is possible to prevent the luminance from being varied due to the deviation of the high potential voltage VDD. Since the 'IR drop' phenomenon of the high potential voltage (VDD) is severe in a large-area, high-resolution display panel, the present invention is advantageous in application to a large-area, high-resolution display panel.

9 is a diagram illustrating a pixel array according to a second embodiment.

Referring to FIG. 9 , one pixel array includes a shared node controller Psh and a plurality of unit pixels Pcom. A plurality of unit pixels Pcom share a shared node controller Psh. The shared node controller Psh includes fifth to seventh transistors T7. The unit pixel Pcom includes an organic light emitting diode OLED, a driving transistor DT, first to fourth transistors T4, and a capacitor Cst. Components included in the shared node control unit Psh and the unit pixel Pcom are the same as those of the pixels shown in FIG. 4 and perform the same operation based on the same gate signal, so a detailed description thereof will be omitted.

The fifth to seventh transistors T5, T6, and T7 belonging to the shared node control unit Psh are for controlling the fourth node N4 and switch the fourth node N4 and the constant voltage sources, respectively. That is, since the data voltage Vdata does not intervene in the operation of the fifth to seventh transistors T5, T6, and T7 that control the fourth node N4, the fourth node of the pixels arranged on the same pixel line (N4) is controlled with the same voltage. Therefore, in the second embodiment, one shared node control unit Psh for controlling the fourth node N4 is disposed on the pixel line, and the capacitor Cst of each unit pixel Pcom is connected to the fourth node N4. By connecting to, it is possible to share the shared node control unit (Psh).

In the pixel array according to the second embodiment, a unit pixel Pcom including an organic light emitting diode (OLED) corresponds to one pixel. Therefore, the second embodiment can reduce the number of transistors included in the pixel P compared to the first embodiment.

Since the size of the pixels can be reduced in the second embodiment, it is advantageous for application to a high-resolution display device. Alternatively, when the second embodiment is applied without reducing the pixel size, the luminance can be increased by increasing the light emitting area.

Through the above description, those skilled in the art will know that various changes and modifications are possible without departing from the technical spirit of the present specification. Therefore, the technical scope of the present specification is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100: display panel 110: timing controller
120: data driver 130,140: gate driver
Psh: shared node control unit Pcom: unit pixel

Claims (9)

a driving transistor that controls driving current of the organic light emitting diode and includes a gate electrode, a source electrode, and a drain electrode;
a capacitor connected between the gate electrode and a common node;
a first control unit connecting the sharing node and a high potential voltage line during an initialization period;
a second control unit connecting the sharing node and an initialization voltage line during a sensing period following the initialization period; and
and a third control unit connecting the common node and the high-potential voltage line during an emission period following the sensing period. According to claim 1,
During the sensing period,
a first transistor connecting the gate electrode and the source electrode; and
The organic light emitting display device further includes a second transistor connecting the drain electrode and the data line. According to claim 2,
During the initialization period,
The organic light emitting display device further includes a third transistor connecting the initialization voltage line and the gate electrode. According to claim 3,
The organic light emitting display device further includes a fourth transistor connecting the high potential voltage line and the source electrode during the light emitting period. According to claim 3,
In the pixels arranged on the n (n is a natural number)-th pixel line,
The first control unit and the gate electrode of each of the third transistors receive an (n-1)th scan signal,
The second control unit and the gate electrode of each of the first and second transistors receive an nth scan signal,
wherein the (n−1)th scan signal is applied to the second controller disposed on the (n−1)th pixel line and to gate electrodes of the first and second transistors, respectively. a sharing node controller controlling a voltage of the sharing node; and
Includes a plurality of unit pixels sharing the shared node;
Each of the unit pixels is
a driving transistor for driving an organic light emitting diode by receiving a high potential voltage through a source electrode; and
A capacitor connected to the gate electrode of the driving transistor;
The shared node control unit
controlling a gate voltage of the driving transistor coupled to the capacitor by controlling a voltage of the common node, and applying the high potential voltage to the common node during a sensing period in which data is written to the pixels;
The capacitor of each of the unit pixels located on a pixel line arranged along the scan line direction is connected to the common node, so that the gate voltage of each of the driving transistors of the unit pixels is equally controlled according to the common node voltage. organic light emitting display device. delete According to claim 6,
The shared node control unit
a first control unit connected between the sharing node and a high potential voltage line;
a second control unit connected between the sharing node and an initialization voltage line; and
and a third controller connected to the sharing node and the high potential voltage line. According to claim 8,
The driving transistor includes a gate electrode connected to a first node, a source electrode connected to a second node, and a drain electrode connected to a third node;
Each of the unit pixels is
a first transistor connected between the first node and the second node;
a second transistor connected between the third node and a data line;
a third transistor connected between the initialization voltage line and the first node; and
The organic light emitting display device further includes a fourth transistor connected between the high potential voltage line and the second node.

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