KR102410789B1 - Semiconductor package - Google Patents

Abstract

A semiconductor device package according to the present invention includes a body including a flat lower surface, an upper surface parallel to the lower surface, and first and second openings penetrating the upper and lower surfaces;
a semiconductor device disposed on the body; an adhesive disposed between the body and the semiconductor device; and a molding member disposed to surround the semiconductor device. including,
The semiconductor device may include first and second bonding portions respectively disposed on the first and second openings, and an outer surface of the molding member may be disposed on the same plane as an outer surface of the body.
Through the present invention, it is possible to improve the reliability and light conversion efficiency of the semiconductor device package.
In addition, the process yield of the semiconductor device package can be improved through the present invention.

Description

Semiconductor package {Semiconductor package}

The present invention relates to a semiconductor device package and a method for manufacturing the semiconductor device package.

A semiconductor device containing a compound such as GaN, AlGaN, InGaN, InAlGaN, GaAs, AlGaAs, InGaAs, GaP, AlGaInP, InP, etc. has many advantages such as wide and easily adjustable band gap energy. and various diodes.

In particular, light emitting devices such as light emitting diodes or laser diodes using compound semiconductor materials such as group 3-5 or group 2-6 of semiconductors are red and green due to the development of thin film growth technology and device materials. Various colors such as , blue and ultraviolet light can be realized, and white light with good efficiency can be realized by using fluorescent materials or adjusting the color. It has the advantages of speed, stability, and environmental friendliness.

In addition, when a light receiving device such as a photodetector or a solar cell is manufactured using a semiconductor group 3-5 or group 2-6 compound semiconductor material, a photocurrent is generated by absorbing light in various wavelength ranges through the development of the device material. By doing so, it is possible to absorb light in a range of wavelengths from gamma rays to a radio wavelength range and use light in a range of wavelengths from gamma rays to a radio wavelength range. In addition, since it has advantages of fast response speed, stability, environmental friendliness and easy adjustment of device materials, it can be easily used in power control or ultra-harmonic circuits or communication modules.

Therefore, the semiconductor device can replace a light emitting diode backlight, a fluorescent lamp or an incandescent light bulb that replaces a cold cathode tube (CCFL) constituting a transmission module of an optical communication means and a backlight of a liquid crystal display (LCD) display device. Applications such as white light emitting diode lighting devices, automobile headlights and traffic lights, sensors that detect gas or fire, and medical devices are expanding. In addition, the application of the semiconductor device can be extended to high-frequency application circuits, other power control devices, and communication modules.

In recent years, various developments have been made on the structure of the semiconductor device package to improve the luminous flux and light extraction efficiency of the semiconductor device.

An object of the present invention is to provide a semiconductor device package and a semiconductor device package manufacturing method capable of improving light conversion efficiency and electrical characteristics.

An object of the present invention is to provide a semiconductor device package and a semiconductor device package manufacturing method that improve process efficiency by suggesting a new package structure.

A semiconductor device package according to the present invention includes a body including a flat lower surface, an upper surface parallel to the lower surface, and first and second openings penetrating the upper and lower surfaces; a semiconductor device disposed on the body; an adhesive disposed between the body and the semiconductor device; and a molding member disposed to surround the semiconductor device. The semiconductor device may include first and second bonding portions disposed on the first and second openings, respectively, and the outer surface of the molding member may be disposed on the same plane as the outer surface of the body. have.

In addition, it is disposed between the first opening and the second opening, further comprising a recess arranged concavely in the direction from the upper surface to the lower surface of the body, the adhesive may be disposed in the recess

In addition, a thickness of the recess may be smaller than a thickness of the first opening and the second opening.

In addition, the thickness of the recess may be greater than 0 to 5/6 or less compared to the thickness of the first and second openings.

In addition, the horizontal width of the recess may be 1:0.2 or more and less than 1:1 compared to the horizontal width between the first bonding part and the second bonding part.

In addition, a horizontal distance between the outer end of the recess and the inner surface of the first and second openings may be 50 μm or more to 150 μm or less.

The first opening and the second opening may include a first angle θ1 between inner surfaces and a second angle θ2 between the outer surfaces with respect to lower surfaces of the first and second openings.

In addition, the first angle and the second angle include an angle of 0 degrees or more and 90 degrees or less,

The first angle may be equal to or smaller than the second angle.

In addition, widths of lower surfaces of the first and second openings may be greater than widths of upper surfaces of the first and second openings.

In addition, the horizontal width of the upper portions of the first opening and the second opening may be 70% or more and 95% or less of the horizontal width of the first bonding portion and the second bonding portion.

In addition, a horizontal distance between the lower ends of the outer surfaces of the first opening and the second opening and the outer surface of the body may be 150 μm or more and 200 μm or less.

In addition, a horizontal distance between the side surface of the semiconductor device and the side surface of the molding member may be 50 μm or more and 200 μm or less.

In addition, the molding member may include a wavelength conversion material.

In addition, the molding member may be composed of a plurality of layers.

The molding member includes a first layer including a wavelength conversion material and a second layer disposed on the side of the semiconductor device under the first layer, the second layer being made of a transparent resin, and having a refractive index different from the refractive index of the semiconductor device It may have a refractive index.

In addition, the molding member further includes a third layer disposed surrounding the second layer,

The third layer may be made of a resin including a reflective material.

In addition, it further includes a first contact layer disposed between the first bonding portion and the first opening and a second contact layer disposed between the second electrode and the second opening, wherein the upper portion of the first opening and the second opening is formed. A horizontal width may be greater than a horizontal width of the first bonding unit and the second bonding unit.

In addition, a horizontal width of the first contact layer may be greater than a horizontal width of the first bonding portion and greater than a horizontal width of an upper portion of the first opening.

In addition, a horizontal width of the second contact layer may be greater than a horizontal width of the second bonding portion and greater than a horizontal width of an upper portion of the second opening.

Through the present invention, it is possible to improve the reliability and light conversion efficiency of the semiconductor device package.

Through the present invention, it is possible to improve the process yield of a semiconductor device package.

On the other hand, the effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention belongs from the description below. will be able

1 is a perspective view of a semiconductor device package according to an embodiment.
FIG. 2 shows a cross-section of the semiconductor device package according to the first embodiment taken in the direction A-A' in FIG. 1 .
3 is a view for explaining the first and second angles included in the semiconductor device package according to the first embodiment.
4 is a view for explaining a method of manufacturing a semiconductor device package according to the first embodiment.
FIG. 5 is a cross-sectional view illustrating a semiconductor device package according to the second embodiment taken in the direction A-A' in FIG. 1 .
6 is a view for explaining the first and second angles included in the semiconductor device package according to the second embodiment.
7 is a view for explaining a method of manufacturing a semiconductor device package according to the second embodiment.

The above-described object and technical configuration of the present invention and details regarding the operational effects thereof will be more clearly understood by the following detailed description.

In the description of the present invention, terms such as first, second, etc. used below are merely identification symbols for distinguishing the same or corresponding components, and the same or corresponding components are first, second, etc. terms is not limited by

The singular expression includes the plural expression unless the context clearly dictates otherwise. Terms such as “comprising” or “having” are intended to designate that a feature, number, step, action, component, part, or combination thereof described in the specification exists, and includes one or more other features, number, or step. , operations, components, parts, or combinations thereof may be construed as being added.

As used hereinafter, “comprises” and/or “comprising” refers to the presence or absence of one or more other components, steps, operations and/or elements mentioned addition is not excluded.

Hereinafter, a semiconductor device package according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view of a semiconductor device package according to the present invention, and FIG. 2 is a cross-sectional view of the semiconductor device package according to the first embodiment taken in the direction A-A' of FIG. 1 .

The semiconductor device 20 according to the first embodiment may be a light emitting device.

The semiconductor device 20 according to the embodiment may include a support part, a light emitting structure, and a bonding part.

The support part may be selected from a group including a sapphire substrate (Al ₂ O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge.

The light emitting structure may include a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer.

The light emitting structure may be provided as a compound semiconductor. The light emitting structure may be provided as, for example, a group 2-6 or group 3-5 compound semiconductor. For example, the light emitting structure may include at least two or more elements selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As), and nitrogen (N). .

The light emitting structure may include a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer.

The first and second conductivity-type semiconductor layers may be implemented with at least one of a group 3-5 or group 2-6 compound semiconductor. The first and second conductivity type semiconductor layers are formed of, for example, a semiconductor material having a compositional formula of In _x Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) can be For example, the first and second conductivity-type semiconductor layers may include at least one selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. . The first conductivity-type semiconductor layer may be an n-type semiconductor layer doped with an n-type dopant such as Si, Ge, Sn, Se, or Te. The second conductivity-type semiconductor layer may be a p-type semiconductor layer doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba.

The active layer may be implemented with a compound semiconductor. The active layer may be embodied as, for example, at least one of a group 3-5 or group 2-6 compound semiconductor. When the active layer is implemented as a multi-well structure, the active layer may include a plurality of well layers and a plurality of barrier layers that are alternately disposed, and In _x Al _y Ga _{1 -x- y} N (0≤x≤1 , 0≤y≤1, 0≤x+y≤1). For example, the active layer may be selected from the group consisting of InGaN/GaN, GaN/AlGaN, AlGaN/AlGaN, InGaN/AlGaN, InGaN/InGaN, AlGaAs/GaAs, InGaAs/GaAs, InGaP/GaP, AlInGaP/InGaP, InP/GaAs. It may include at least one.

The bonding unit may include a first bonding unit 22 and a second bonding unit 24 . The first bonding portion 22 and the second bonding portion 24 may be disposed to be spaced apart from each other on the lower surface of the light emitting device. The first bonding part 22 may be disposed on the first electrode pattern. The second bonding part 24 may be disposed on the second electrode pattern.

The bonding portion is Ti, Al, In, Ir, Ta, Pd, Co, Cr, Mg, Zn, Ni, Si, Ge, Ag, Ag alloy, Au, Hf, Pt, Ru, Rh, ZnO, IrOx, RuOx, One or more materials or alloys selected from the group including NiO, RuOx/ITO, Ni/IrOx/Au, and Ni/IrOx/Au/ITO may be used to form a single layer or multiple layers.

The semiconductor device 20 may be disposed on the body 10 .

The semiconductor device 20 may include a first bonding unit 22 and a second bonding unit 24 .

The first bonding unit 22 and the second bonding unit 24 may be disposed on one surface of the semiconductor device 20 .

The first bonding portion 22 may be disposed on the first opening 32 . The second bonding part 24 may be disposed on the second opening 34 .

The semiconductor device 20 may include first and second pad electrodes (not shown), and each pad electrode may contact the first bonding unit 22 and the second bonding unit 24 .

A current may flow to the semiconductor device 20 through the first bonding unit 22 and the second bonding unit 24 .

The first bonding portion 22 and the second bonding portion 24 may be formed of a material having excellent electrical contact.

The first bonding portion 22 and the second bonding portion 24 are Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, Be, Ge, ITO. (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide) ), ATO (Antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, and at least one of Ni/IrOx/Au/ITO, but is not limited thereto.

In addition, the first bonding unit 22 and the second bonding unit 24 may be formed of a single layer or multiple layers.

A first opening 32 , a second opening 34 , a first conductive layer 42 , a second conductive layer 44 , and a recess 50 may be disposed on the body 10 .

The body 10 includes polyphthalamide (PPA), polychloro triphenyl (PCT), liquid crystal polymer (LCP), polyamide9T (PA9T), silicone, epoxy molding compound (EMC), and a silicone molding compound. (SMC), ceramic photo sensitive glass (PSG), sapphire (Al2O3), etc. may be composed of at least one or more, but is not limited thereto.

A first opening 32 and a second opening 34 may be disposed in the body 10 .

The body 10 may include a first opening 32 and a second opening 34 passing through the lower surface from the upper surface of the body 10 .

The first opening 32 and the second opening 34 may perform a heat dissipation function of the semiconductor device package.

The first opening 32 may be disposed on one surface of the first bonding part 22 of the semiconductor device 20 . The first opening 32 may be disposed to overlap the first bonding portion 22 of the semiconductor device 20 .

The second opening 34 may be disposed on one surface of the second bonding part 24 of the semiconductor device 20 . The second opening 34 may be disposed to overlap the second bonding portion 24 of the semiconductor device 20 .

The first opening 32 and the second opening 34 may be disposed to be spaced apart from each other. The first opening 32 and the second opening 34 may be disposed to be spaced apart from each other on one surface of the semiconductor device 20 .

Horizontal widths of lower portions of the first and second openings 32 and 34 may be greater than horizontal widths of upper portions of the first and second openings 32 and 34 .

A horizontal width W1 of an upper portion of the first opening 32 may be smaller than a horizontal width W2 of the first bonding portion 22 .

A horizontal width W1 of an upper portion of the second opening 34 may be smaller than a horizontal width W2 of the second bonding portion 24 .

For example, in consideration of the tolerance between the semiconductor device 20 and the body 10 to implement the SMT, the horizontal width W1 of the upper portion of the opening 30 is the horizontal width W2 of the electrode. It can be arranged smaller than

* The opening 30 includes the first opening 32 and the second opening 34 , and the bonding part includes the first bonding part 22 and the second bonding part 24 .

Accordingly, the horizontal width W1 of the upper portion of the opening 30 is arranged to be smaller than the horizontal width W2 of the bonding portion, so that the semiconductor device 20 and the body 10 can be firmly attached.

The horizontal width W1 of the upper portion of the opening 30 may be 35 μm or more and 855 μm or less.

The horizontal width W2 of the first bonding unit 22 and the second bonding unit 24 may be 50 μm or more and 900 μm or less.

The horizontal width W1 of the upper portion of the opening 30 compared to the horizontal width W2 of the bonding portion may be 70% or more to 95% or less.

When the horizontal width W1 of the upper portion of the opening 30 compared to the horizontal width W2 of the bonding portion is 70% or more, the reliability of the semiconductor device package may be secured.

When the horizontal width W1 of the upper portion of the opening 30 is 95% or less compared to the horizontal width W2 of the bonding portion, the current injected into the semiconductor device 20 becomes smooth, so that the current characteristics of the semiconductor device package are improved. can be obtained

For example, when the horizontal width W2 of the bonding portion is 50 μm, the horizontal width W1 of the upper portion of the opening 30 may be 35 μm or more and 47.5 μm or less.

Alternatively, when the horizontal width W2 of the bonding portion is 900 μm, the horizontal width W1 of the upper portion of the opening 30 may be 630 μm or more and 855 μm or less.

Meanwhile, the first opening 32 and the second opening 34 according to the first embodiment may include, but are not limited to, an inclined shape in which the width gradually decreases from the lower part to the upper part.

The first opening 32 and the second opening 34 may have various shapes.

The upper and lower portions of the first opening 32 and the second opening 34 may be disposed to have the same width.

The first opening 32 and the second opening 34 may have different widths in the upper to lower direction.

The first opening 32 and the second opening 34 may be disposed in a shape having a curvature from the top to the bottom.

Also, the inclined surfaces between the upper and lower portions of the first opening 32 and the second opening 34 may have a plurality of inclined surfaces having different inclinations from each other.

In addition, the first opening 32 and the second opening 34 may be arranged in a multi-stage structure.

The horizontal width W3 between the first opening 32 and the second opening 34 on the lower surface of the body 10 may be 200 μm or more and 250 μm or less.

The horizontal width W3 between the first opening 32 and the second opening 34 is the inner surface of the first opening 32 in contact with the lower surface of the body 10 and the second opening 34 . means the width (W3) between the inner surfaces of

When the width W3 between the inner surface of the first opening 32 and the inner surface of the second opening 34 on the lower surface of the body 10 is 200 μm or more, the semiconductor device package according to the embodiment is mounted on a circuit board, etc. In this case, it is possible to prevent a short from occurring between regions to be bonded.

When the horizontal width W3 between the inner surface of the first opening 32 and the inner surface of the second opening 34 in the lower surface of the body 10 is 250 μm or less, the process and manufacturing yield of the semiconductor device package are secured can do.

The horizontal distance W9 between the lower end of the outer surface of the opening 30 and the outer surface of the body 10 may be 150 μm or more and 200 μm or less.

When the horizontal distance W9 between the lower end of the outer surface of the opening 30 and the outer surface of the body 10 is 150 μm or more, cracking of the body 10 can be prevented.

When the horizontal distance W9 between the lower end of the outer surface of the opening 30 and the outer surface of the body 10 is 200 μm or less, the manufacturing yield of the semiconductor device package can be secured.

The first opening 32 and the second opening 34 may include an angle with respect to an inner surface and an angle with respect to an outer surface of the lower surfaces of the first opening 32 and the second opening 34 .

The angle between the inner surfaces with respect to the lower surfaces of the first and second openings 32 and 34 is the first angle θ1, and between the outer surfaces with respect to the lower surfaces of the first and second openings 32 and 34. Assuming that the angle θ2 is the second angle θ2 , the first angle θ1 may be equal to or smaller than the second angle θ2 .

The first angle θ1 and the second angle θ2 may be 0 degrees or more and 90 degrees or less.

A detailed description of the first angle θ1 and the second angle θ2 will be described later with reference to FIG. 3 .

The semiconductor device package according to the embodiment may include the first conductive layer 42 and the second conductive layer 44 .

The first conductive layer 42 may be disposed in the first opening 32 . The first conductive layer 42 may be disposed in direct contact with the lower surface of the first bonding part 22 . The first conductive layer 42 may overlap the first bonding portion 22 in a vertical direction.

In addition, the horizontal width of the upper surface of the first conductive layer 42 may be the same as the horizontal width W1 of the upper surface of the first opening 32 .

Accordingly, the horizontal width of the upper surface of the first conductive layer 42 may be smaller than the horizontal width of the first bonding portion 22 .

Also, the upper surface of the first conductive layer 42 may be disposed on the same plane as the upper surface of the body 10 .

A lower surface of the first conductive layer 42 may be disposed on the same plane as a lower surface of the body 10 .

The second conductive layer 44 may be disposed in the second opening 34 . The second conductive layer 44 may be disposed in direct contact with the lower surface of the second bonding part 24 . The second conductive layer 44 may overlap the second bonding part 24 in a vertical direction.

In addition, the horizontal width of the upper surface of the second conductive layer 44 may be the same as the horizontal width of the upper surface of the second opening 34 .

Accordingly, the horizontal width of the upper surface of the second conductive layer 44 may be smaller than the horizontal width W2 of the first bonding portion 22 .

In addition, an upper surface of the second conductive layer 44 may be disposed on the same plane as the upper surface of the body 10 .

A lower surface of the second conductive layer 44 may be disposed on the same plane as a lower surface of the body 10 .

The first conductive layer 42 and the second conductive layer 44 are disposed in the first opening 32 and the second opening 34 to smooth the current injected into the semiconductor device 20, It may serve to mount the semiconductor device package on a circuit board or the like.

The first conductive layer 42 and the second conductive layer 44 may include at least one material such as Ag, Au, Pt, or the like. However, the present invention is not limited thereto, and may include a material capable of securing a conductive function.

The first conductive layer 42 and the second conductive layer 44 may be formed of a conductive paste.

For example, the first conductive layer 42 and the second conductive layer 44 may be formed of solder paste or silver paste, but is not limited thereto.

The recess 50 may be disposed between the first opening 32 and the second opening 34 .

The recess 50 may be disposed under the semiconductor device 20 .

In addition, inclined surfaces of the first opening 32 and the second opening 34 disposed between the first bonding unit 22 and the second bonding unit 24 may vertically overlap the recess 50 . can

The recess 50 may be concavely disposed in a direction from an upper surface to a lower surface of the body 10 .

The horizontal width W4 of the recess relative to the horizontal distance W7 between the first bonding part 22 and the second bonding part 24 may be 0.2:1 or more and less than 1:1.

When the horizontal distance W7 between the first bonding part 22 and the second bonding part 24 is the first distance W7, the horizontal width W4 of the recess compared to the first distance W7 ) is 0.2:1 or more, by improving the fixing force between the semiconductor device 20 and the body 10, it is possible to secure the reliability of the semiconductor device package.

When the horizontal width W4 of the recess 50 is less than 1:1 compared to the horizontal distance W7, the light extraction characteristics of the semiconductor device package may be improved.

The horizontal width W4 of the recess 50 may be 50 μm or more and 300 μm or less.

When the horizontal width W4 of the recess 50 is 50 μm or more, the fixing force between the semiconductor device 20 and the body 10 is improved, so that the reliability of the semiconductor device package can be secured.

When the horizontal width W4 of the recess 50 is 300 μm or less, the process yield of the semiconductor device package may be improved.

The thickness d1 of the recess 50 is configured to be smaller than the thickness d2 of the first opening 32 and the second opening 34 .

A thickness d2 of the first opening 32 and the second opening 34 may be 50 μm or more to 300 μm.

The thickness d1 of the recess 50 is greater than 0um to 250 μm or less.

When the thickness d1 of the recess 50 is greater than 0 μm, the fixing force between the body 10 and the semiconductor device 20 is improved, so that the reliability of the semiconductor device package can be secured.

When the thickness d1 of the recess 50 is 250 μm or less, the recess 50 is prevented from coming into contact with the opening 30 to prevent damage to the recess 50 .

Also, the thickness d1 of the recess 50 may be determined in consideration of the adhesive force of the adhesive 60 .

The thickness d1 of the recess 50 compared to the thickness d2 of the first opening 32 and the second opening 34 may be greater than 0 to 5/6 or less.

Assuming that the thickness d1 of the recess 50 is a first thickness, and the thickness d2 of the first opening 32 and the second opening 34 is a second thickness,

When the first thickness d1 compared to the second thickness d2 is greater than 0, the recess 50 is disposed to secure the reliability of the semiconductor device package.

When the first thickness d1 compared to the second thickness d2 is 5/6 or less, the heat dissipation characteristic of the opening 30 may be improved.

An adhesive 60 may be disposed in the recess 50 .

The adhesive 60 may be disposed between the lower surface of the semiconductor device 20 and the upper surface of the body 10 .

The adhesive 60 may be disposed between the first bonding unit 22 and the second bonding unit 24 .

The adhesive 60 may be in contact with the inner surface of the first bonding unit 22 and the inner surface of the second bonding unit 24 .

The adhesive 60 may be in direct contact with the upper surface of the body 10 .

In addition, the adhesive 60 may be disposed in direct contact with one surface of the semiconductor device 20 .

Accordingly, the adhesive 60 may provide a stable fixing force between the semiconductor device 20 and the body 10 .

When light is emitted to the lower surface of the semiconductor device 20 , the adhesive 60 may function to diffuse light between the semiconductor device 20 and the body 10 .

In addition, the adhesive 60 may improve the light conversion efficiency of the semiconductor device package by performing a light diffusion function.

The adhesive 60 may include at least one of an epoxy-based material, a silicone-based material, an epoxy-based material, and a hybrid material including a silicone-based material, but is limited thereto. don't do it

The molding member 70 may be disposed on the semiconductor device 20 . The molding member 70 may be disposed on the body 10 .

The outer surface of the molding member 70 may be disposed on the same plane as the outer surface of the body 10 .

The horizontal distance W8 between the side surface of the semiconductor device 20 and the outer surface of the molding member 70 may be 50 μm or more and 200 μm or less.

When the horizontal distance W8 between the side surface of the semiconductor device 20 and the outer surface of the molding member 70 is 50 μm or more, cracking of the molding member 70 can be prevented.

When the horizontal distance W8 between the side surface of the semiconductor device 20 and the outer surface of the molding member 70 is 200 μm or less, the process yield of the semiconductor device package can be secured.

The molding member 70 may convert the wavelength of the light emitted from the molding member 70 to the outside when the light incident on the molding member 70 from the semiconductor device 20 is emitted to the outside.

The molding member 70 may be made of a polymer resin containing a wavelength conversion material.

The polymer resin is a permeable epoxy resin, a silicone resin. It may include at least one of polyimide resin, urea resin, and acrylic resin, but is not limited thereto. The wavelength conversion material may be a phosphor. The wavelength conversion material may include at least one of a sulfide-based compound, an oxide-based compound, or a nitride-based compound, but is not limited thereto.

The phosphor may be variously selected to realize a color desired by a user.

For example, when the semiconductor device 20 emits light in an ultraviolet wavelength band, a green phosphor, a blue phosphor, and a red phosphor may be selected as the phosphor. When the semiconductor device 20 emits light in a blue wavelength band, a yellow phosphor, a combination of a red phosphor and a green phosphor, or a combination of a yellow phosphor, a red phosphor, and a green phosphor may be selected as the phosphor.

The molding member 70 may be composed of a plurality of layers.

The molding member 70 may include a first layer including a wavelength conversion material and a second layer (not shown) disposed on the side of the semiconductor device under the first layer.

The second layer may be made of a transparent resin.

The resin may be one or more of an epoxy resin, a silicone resin, a polyimide resin, a urea resin, and an acrylic resin, but is not limited thereto.

The second layer (not shown) may have a refractive index different from that of the semiconductor device 20 , and the refractive index of the second layer may have a refractive index equal to or less than that of the semiconductor device 20 .

The molding member 70 may further include a third layer (not shown).

The third layer (not shown) may be made of a resin including a reflective material.

The reflective material may be TiO2 or SiO2, but is not limited thereto.

The resin may be one or more of an epoxy resin, a silicone resin, a polyimide resin, a urea resin, and an acrylic resin, but is not limited thereto.

The third layer may be disposed to surround the second layer.

The first angle θ1 and the second angle θ2 included in the first opening 32 and the second opening 34 will be described with reference to FIG. 3 .

The first opening 32 and the second opening 34 have a first angle θ1 between the inner surface and a second angle θ1 between the outer surface with respect to the lower surfaces of the first opening 32 and the second opening 34. θ2), and the horizontal width W4 of the recess 50 may be adjusted through the first angle θ1 and the second angle θ2.

When the first angle θ1 includes an angle smaller than the second angle θ2, the recess 50 is greater than when the first angle θ1 includes the same angle as the second angle θ2. ), the horizontal width W4 may be increased.

In order to secure the horizontal width W4 of the recess 50 in which the adhesive 60 for fixing the body 10 and the semiconductor device 20 is disposed, the first angle θ1 is the second angle θ2 ) can be equal to or smaller than the angle.

When the first angle θ1 includes an angle smaller than the second angle θ2, the horizontal width W4 of the recess 50 is determined such that the first angle θ1 is the second angle θ2 ) can be increased compared to the case of the same angle.

As the horizontal width W4 of the recess 50 increases, the space in which the adhesive 60 disposed in the recess 50 is disposed increases, so that the body 10 and the semiconductor device 20 The fixing force between them may be improved.

Also, the thickness d1 of the recess 50 may be adjusted through the first angle θ1 and the second angle θ2 .

When the first angle θ1 includes an angle smaller than the second angle θ2 , the recess 50 is connected to the semiconductor device 20 through the adhesive 60 disposed in the recess 50 . ), it is possible to secure a thickness that can sufficiently reflect the light emitted from the lower surface.

In addition, as the thickness d1 of the recess 50 that can ensure the reflectivity is secured, the adhesive 60 disposed in the recess 50 absorbs light emitted from the lower surface of the semiconductor device 20 . A light conversion rate that can be converted can be secured.

Accordingly, the recess 50 has a horizontal width W4 of the recess 50 by the first angle θ1 and the second angle θ2 of the first opening 32 and the second opening 34 . ) and the thickness d1 can be adjusted.

The thickness d1 of the recess 50 and the width W4 in the horizontal direction may be considered within a range capable of securing the fixing force between the body 10 and the semiconductor device 20 through the adhesive 60 . can

Meanwhile, the horizontal distance W6 between the outer end of the recess 50 and the inner surface of the first opening 32 and the inner surface of the second opening 34 may be 50 μm or more and 150 μm or less. .

When the horizontal distance W6 between the outer surface of the recess 50 and the inner surface of the first opening 32 and the inner surface of the second opening 34 is 50 μm or more, the recess 50 and the first opening 32 and the second opening 34 are prevented from coming into contact with each other, thereby preventing damage to the recess 50 .

When the horizontal distance W6 between the outer surface of the recess 50 and the inner surface of the first opening 32 and the inner surface of the second opening 34 is 150 μm or less, the recess 50 By securing a horizontal width W4 of a certain distance or more, the body 10 and the semiconductor device 20 can be firmly fixed through the adhesive 60 disposed in the recess 50 .

The first angle θ1 and the second angle θ2 of the first opening 32 and the second opening 34 may be adjusted within the horizontal distance range.

A method of manufacturing a semiconductor device package according to the first embodiment will be described with reference to FIG. 4 .

In describing the method of manufacturing the semiconductor device package according to the first embodiment, detailed descriptions of the components overlapping those described with reference to FIGS. 1 to 3 will be omitted.

The semiconductor device package manufacturing method according to the first embodiment is applied to a chip scale package (chip scale package) process.

First, referring to FIG. 4A , the body 10 may be disposed on a substrate.

It is described as an example that only one body 10 is provided on the substrate, but the present invention is not limited thereto, and a plurality of bodies 10 may be disposed.

One or more bodies 10 may be disposed on the substrate through an injection process or the like.

The substrate may include at least one or more of a polyimide-based resin, glass, an acrylic-based resin, an epoxy-based resin, and a silicone-based resin, but is not limited thereto.

The substrate may be one of a sapphire substrate, a printed circuit board, a ceramic substrate, and a semiconductor substrate, but is not limited thereto.

The body 10 may include a first opening 32 and a second opening 34 . Also, the body 10 may include a recess 50 .

The first opening 32 may be disposed through the body 10 . The first opening 32 may be disposed through the upper and lower surfaces of the body 10 .

The second opening 34 may be disposed through the body 10 . The second opening 34 may be disposed to penetrate through the upper and lower surfaces of the body 10 .

The first opening 32 and the second opening 34 may be disposed to be spaced apart from each other in the body 10 .

The recess 50 may be disposed in the body 10 . The recess 50 may be disposed between the first opening 32 and the second opening 34 .

The recess 50 may be concavely disposed in a direction from an upper surface to a lower surface of the body 10 .

Referring to FIG. 4B , an adhesive 60 is disposed in the recess 50 .

The adhesive 60 may be disposed in the recess 50 through a doting method or the like.

The adhesive 60 may be disposed in a predetermined amount in the recess 50 , and may be disposed to overflow out of the recess 50 .

The adhesive 60 applied in the recess 50 may be moved to the lower region of the semiconductor device 20 through a capillary phenomenon or the like.

The lower region of the semiconductor device 20 may be a region between the first bonding portion 32 and the second bonding portion 34 .

Referring to FIG. 4C , a semiconductor device 20 may be disposed on the body 10 .

In the process of being disposed on the body 10 , the recess 50 may serve as a kind of align key.

The semiconductor device 20 may be fixed to the body 10 by the adhesive 60 .

The first opening 32 may be disposed on one surface of the first bonding part 22 of the semiconductor device 20 .

The first opening 32 may be vertically overlapped with the first bonding portion 22 of the semiconductor device 20 .

The second opening 34 may be disposed on one surface of the second bonding part 24 of the semiconductor device 20 . The second opening 34 may be vertically overlapped with the second bonding portion 24 of the semiconductor device 20 .

One surface of the first bonding part 22 may be exposed through the first opening 32 . In addition, one surface of the second bonding part 24 may be exposed through the second opening 34 .

Referring to FIG. 4D , the first conductive layer 42 and the second conductive layer 44 may be disposed by disposing a conductive material in the first opening 32 and the second opening 34 . .

In order to dispose the first conductive layer 42 and the second conductive layer 44 , the substrate may be removed.

In order to arrange the first conductive layer 42 and the second conductive layer 44 , the process may be performed by turning the body 10 on which the semiconductor device 20 is disposed.

The first conductive layer 42 and the second conductive layer 44 may be formed of a conductive paste. A conductive paste may be applied in the first opening 32 and the second opening 34 .

The conductive paste may include at least one material or alloy such as Ag, Au, and Pt, but is not limited thereto.

Referring to FIG. 4E , a molding member 70 may be disposed on the semiconductor device 20 .

The molding member 70 may be disposed on the semiconductor device 20 and the body 10 through a dispenser of a resin material including a wavelength conversion material.

Alternatively, a resin film including a wavelength conversion material may be disposed on the semiconductor device 20 .

By attaching a resin film to the semiconductor device 20 and the body 10 through a heat and pressure process, the molding member 70 may be disposed.

For example, the molding member 70 may be disposed on the semiconductor device 20 and the body 10 through a resin film lamination process.

Through the lamination process, a resin film may be attached to the semiconductor device 20 and the body 10 by heating and pressing.

The resin film may include silicone composed of only a bonding group.

Since the silicone has no unbonded components, the resin is not discolored or damaged by heat.

When the temperature, pressurization pressure, and pressurization time are adjusted, lamination proceeds between the semiconductor element 20 and the body 10 and the resin film, so that the molding member 70 surrounding the semiconductor element 20 is disposed. can

A resin film is laminated on one semiconductor device 20 to manufacture a semiconductor device package in which the molding member 70 is disposed.

In addition, a semiconductor device array including a molding member 70 formed by laminating a silicon film on a plurality of semiconductor devices 20 on a substrate may be manufactured.

Thereafter, a cutting process is performed on the semiconductor device array, so that the semiconductor device 20 can be individually manufactured. In the individual semiconductor device 20 cut in this way, the edge of the semiconductor device 20 may be angled.

Referring to FIG. 4(f) , the semiconductor device package according to the first embodiment of the present invention may be provided by removing the substrate.

As described with reference to FIG. 4, according to the method for manufacturing a semiconductor device package according to the embodiment, the reliability of the semiconductor device package is improved, and as a lamination process is applied, the resin is discolored and cracks are generated. problem can be solved.

In addition, the yield of the semiconductor device package may be improved.

A semiconductor device package according to a second embodiment will be described with reference to FIG. 5 .

In the description of the semiconductor device package according to the second embodiment shown in FIG. 5 , descriptions of configurations overlapping those described with reference to FIGS. 1 to 3 will be omitted.

The semiconductor device 20 according to the second embodiment may be a vertical light emitting device.

The semiconductor device 20 may include a first bonding unit 22 and a second bonding unit 24 .

A first opening 32 , a second opening 34 , a first conductive layer 42 , a second conductive layer 44 , a recess 50 and a contact layer 80 are disposed on the body 10 . can be

The body 10, the first opening 34, the second opening 34, the first conductive layer 42, the second conductive layer 44, the recess 50, the adhesive 60, and a molding member ( 70) has the same configuration as the semiconductor device package according to the first embodiment, and thus a detailed description thereof will be omitted.

A horizontal width W1 of an upper portion of the first opening 32 may be greater than a horizontal width W2 of the first bonding portion 22 .

A horizontal width W1 of an upper portion of the second opening 34 may be greater than a horizontal width W2 of the second bonding portion 24 .

The contact layer 80 may include a first contact layer 82 and a second contact layer 84 .

The first contact layer 82 may be disposed on the first opening 32 . The first contact layer 820 may be disposed between the first bonding portion 22 and the first opening 32 .

The second contact layer 84 may be disposed on the second opening 34 . The second contact layer 84 may be disposed between the second bonding portion 24 and the second opening 34 .

In the semiconductor device package according to the second embodiment, since the horizontal width W2 of the first bonding portion 22 is smaller than the horizontal width W1 of the first opening 32, the first contact layer 82 Through this, the current injected into the semiconductor device 20 may be more smoothly.

In addition, since the horizontal width W2 of the second bonding portion 24 is smaller than the horizontal width W1 of the second opening 34, the semiconductor device 20 through the second contact layer 84. The injected current can be made more smoothly.

The horizontal width W5 of the first contact layer 82 is greater than the horizontal width W2 of the first bonding portion 22 and greater than the horizontal width W1 of the upper portion of the first opening 32 . can

The horizontal width W5 of the second contact layer 84 is greater than the horizontal width W2 of the second bonding portion 24 and greater than the horizontal width W1 of the upper portion of the second opening 34 . can

The first contact layer 82 and the second contact layer 84 may be formed of at least one material such as Ag, Au, Pt, or the like.

However, the present invention is not limited thereto, and may include at least one material among materials capable of securing a conductive function.

The first contact layer 82 and the second contact layer 84 may be formed of a conductive paste.

For example, the first contact layer 82 and the second contact layer 84 may be formed of solder paste or silver paste, but is not limited thereto.

The first contact layer 82 may be made of the same material as the first conductive layer 42 , but is not limited thereto.

In addition, the second contact layer 84 may be made of the same material as the second conductive layer 44, but is not limited thereto.

The adhesive 60 may be disposed between the first bonding unit 22 and the second bonding unit 24 .

The adhesive 60 may be disposed between the lower surface of the semiconductor device 20 and the upper surface of the body 10 .

The adhesive 60 may be disposed between the first bonding unit 22 and the second bonding unit 24 .

The adhesive 60 may be in contact with a side surface of the first bonding unit 22 and a side surface of the second bonding unit 24 .

The adhesive 60 may be disposed between the first contact layer 82 and the second contact layer 84 .

The adhesive 60 may be in contact with the inner surface of the first contact layer 82 and the inner surface of the second contact layer 84 .

The adhesive 60 may be in direct contact with the upper surface of the body 10 .

In addition, the adhesive 60 may be disposed in direct contact with one surface of the semiconductor device 20 .

Accordingly, the adhesive 60 may provide a stable fixing force between the semiconductor device 20 and the body 10 .

When light is emitted to the lower surface of the semiconductor device 20 , the adhesive 60 may function to diffuse light between the semiconductor device 20 and the body 10 .

In addition, the adhesive 60 may improve the light conversion efficiency of the semiconductor device package by performing a light diffusion function.

The adhesive 60 may include at least one of an epoxy-based material, a silicone-based material, an epoxy-based material, and a hybrid material including a silicone-based material, but is limited thereto. don't

6 is a view for explaining the first angle θ1 and the second angle θ2 included in the first opening 32 and the second opening 34 .

The first opening 32 and the second opening 34 include a first angle θ1 between the inner surfaces and a second angle θ2 between the outer surfaces with respect to the lower surface of the body 10, wherein the first The horizontal width W4 of the recess 50 may be adjusted through the angle θ1 and the second angle θ2 .

When the first angle θ1 includes an angle smaller than the second angle θ2, the recess 50 compared to the case where the first angle θ1 includes an angle equal to the second angle θ2 ), the horizontal width W4 may be increased.

In order to secure the horizontal width W4 of the recess 50 in which the adhesive 60 for fixing the body 10 and the semiconductor device 20 is disposed, the first angle θ1 is the second angle θ2 ) can be equal to or less than the angle.

When the first angle θ1 includes an angle smaller than the second angle θ2, the horizontal width W4 of the recess 50 is determined such that the first angle θ1 is the second angle θ2 ) can be increased compared to the case of the same angle.

As the horizontal width W4 of the recess 50 increases, the space in which the adhesive 60 disposed in the recess 50 is disposed increases, so that the body 10 and the semiconductor device 20 The fixing force between them may be improved.

Also, the thickness d1 of the recess 50 may be adjusted through the first angle θ1 and the second angle θ2 .

When the first angle θ1 includes an angle smaller than the second angle θ2 , the recess 50 is connected to the semiconductor device 20 through the adhesive 60 disposed in the recess 50 . ), it is possible to secure a thickness that can sufficiently reflect the light emitted from the lower surface.

In addition, as the thickness d1 of the recess 50 that can ensure the reflectivity is secured, the adhesive 60 disposed in the recess 50 absorbs light emitted from the lower surface of the semiconductor device 20 . A light conversion rate that can be converted can be secured.

Accordingly, the recess 50 has a horizontal width W4 of the recess 50 by the first angle θ1 and the second angle θ2 of the first opening 32 and the second opening 34 . ) and the thickness d1 can be adjusted.

The thickness d1 of the recess 50 and the width W4 in the horizontal direction may be considered within a range capable of securing the fixing force between the body 10 and the semiconductor device 20 through the adhesive 60 . can

Meanwhile, the horizontal distance W6 between the end of the outer surface of the recess 50 and the inner surface of the first opening 32 may be 50 μm or more to 150 μm or less.

When the width in the horizontal direction between the outer surface of the recess 50 and the inner surface of the first opening 32 is 50 μm or more, contact between the recess 50 and the first opening 32 is prevented, , it is possible to prevent damage to the recess 50 .

When the horizontal distance between the outer surface of the recess 50 and the inner surface of the first opening 32 is 150 μm or less, the width of the recess 50 is secured by a certain distance or more, The body 10 and the semiconductor device 20 may be firmly fixed through the adhesive 60 disposed in the 50 .

The first angle θ1 and the second angle θ2 of the first opening 32 and the second opening 34 may be adjusted within the horizontal distance range.

A method of manufacturing a semiconductor device package according to a second embodiment will be described with reference to FIG. 7 .

In describing the method of manufacturing a semiconductor device package according to the second embodiment, a detailed description of the configuration overlapping with those described with reference to FIGS. 1 to 6 will be omitted.

In the semiconductor device package manufacturing method according to the second embodiment, a chip scale package process is applied.

First, referring to FIG. 7A , the body 10 may be disposed on a substrate.

It is described as an example that only one body 10 is provided on the substrate, but the present invention is not limited thereto, and a plurality of bodies 10 may be disposed.

One or more bodies 10 may be disposed on the substrate through an injection process or the like.

The substrate may include at least one or more of a polyimide-based resin, glass, an acrylic-based resin, an epoxy-based resin, and a silicone-based resin, but is not limited thereto.

The substrate may be one of a sapphire substrate, a printed circuit board, a ceramic substrate, and a semiconductor substrate, but is not limited thereto.

The body 10 may include a first opening 32 and a second opening 34 . Also, the body 10 may include a recess 50 .

The first opening 32 may be disposed through the body 10 . The first opening 32 may be disposed to penetrate through the upper and lower surfaces of the body 10 .

The second opening 34 may be disposed through the body 10 . The second opening 34 may be disposed to penetrate through the upper and lower surfaces of the body 10 .

The first opening 32 and the second opening 34 may be disposed to be spaced apart from each other in the body 10 .

The recess 50 may be disposed in the body 10 . The recess 50 may be disposed between the first opening 32 and the second opening 34 .

The recess 50 may be concavely disposed in a direction from an upper surface to a lower surface of the body 10 .

Referring to FIG. 7B , the first contact layer 80 and the second contact layer 80 may be disposed on the first opening 32 and the second opening 34 .

Since the horizontal width W2 of the first bonding portion 22 is smaller than the horizontal width W1 of the first opening 32 , it is injected into the semiconductor device 20 through the first contact layer 80 . The current can be made more smoothly.

In addition, since the horizontal width W2 of the second bonding portion 24 is smaller than the horizontal width W1 of the second opening 34, the second contact layer 80 passes through the semiconductor device 20. The injected current can be made more smoothly.

The horizontal width W5 of the first contact layer 80 is greater than the horizontal width W2 of the first bonding portion 22 and greater than the horizontal width W1 of the upper portion of the first opening 32 . can

The horizontal width W5 of the second contact layer 80 is greater than the horizontal width W2 of the second bonding portion 24 and greater than the horizontal width W1 of the upper portion of the second opening 34 . can

The first contact layer 80 and the second contact layer 80 may be made of at least one material such as Ag, Au, Pt, etc., but is not limited thereto.

The first contact layer 80 and the second contact layer 80 may be formed of a conductive paste.

For example, the first contact layer 80 and the second contact layer 80 may be formed of solder paste or silver paste, but is not limited thereto.

Referring to FIG. 7C , an adhesive 60 is disposed in the recess 50 .

The adhesive 60 may be disposed in the recess 50 through a doting method or the like.

The adhesive 60 may be disposed in a predetermined amount in the recess 50 , and may be disposed to overflow out of the recess 50 .

The adhesive 60 applied in the recess 50 may be moved to the lower region of the semiconductor device 20 through a capillary phenomenon or the like.

The lower region of the semiconductor device 20 may be a region between the first bonding portion 32 and the second bonding portion 34 .

Referring to FIG. 7D , the semiconductor device 20 may be disposed on the body 10 .

In the process of being disposed on the body 10 , the recess 50 may serve as a kind of align key.

The semiconductor device 20 may be fixed to the body 10 by the adhesive 60 .

The first opening 32 may be vertically overlapped with the first bonding portion 22 of the semiconductor device 20 through the first contact layer 82 .

The second opening 34 may be vertically overlapped with the second bonding portion 24 of the semiconductor device 20 through the second contact layer 84 .

Referring to FIG. 7E , the first conductive layer 42 and the second conductive layer 44 may be disposed by disposing a conductive material in the first opening 32 and the second opening 34 . .

In order to dispose the first conductive layer 42 and the second conductive layer 44 , the substrate may be removed.

In order to arrange the first conductive layer 42 and the second conductive layer 44 , the process may be performed by turning the body 10 on which the semiconductor device 20 is disposed.

The first conductive layer 42 and the second conductive layer 44 may be formed of a conductive paste. A conductive paste may be applied in the first opening 32 and the second opening 34 .

The conductive paste may include at least one material or alloy such as Ag, Au, and Pt, but is not limited thereto.

Referring to FIG. 7(f) , a molding member 70 may be disposed on the semiconductor device 20 .

The molding member 70 may be disposed on the semiconductor device 20 and the body 10 through a dispenser of a resin material including a wavelength conversion material.

Alternatively, a resin film including a wavelength conversion material may be disposed on the semiconductor device 20 .

By attaching a resin film to the semiconductor device 20 and the body 10 through a heat and pressure process, the molding member 70 may be disposed.

For example, the molding member 70 may be disposed on the semiconductor device 20 and the body 10 through a resin film lamination process.

Through the lamination process, a resin film may be attached to the semiconductor device 20 and the body 10 by heating and pressing.

The resin film may include silicone composed of only a bonding group.

Since the silicone has no unbonded components, the resin is not discolored or damaged by heat.

When the temperature, pressurization pressure, and pressurization time are adjusted, lamination proceeds between the semiconductor element 20 and the body 10 and the resin film, so that the molding member 70 surrounding the semiconductor element 20 is disposed. can

A resin film is laminated on one semiconductor device 20 to manufacture a semiconductor device package in which the molding member 70 is disposed.

Thereafter, a cutting process is performed on the array of semiconductor devices 20 so that the semiconductor devices 20 can be individually manufactured. In the individual semiconductor device 20 cut in this way, the edge of the semiconductor device 20 may be angled.

As described with reference to FIG. 7, according to the method for manufacturing a semiconductor device package according to the embodiment, the reliability of the semiconductor device package is improved, and as a lamination process is applied, the resin is discolored and cracks are generated. problem can be solved.

In addition, the manufacturing yield of the semiconductor device package may be improved.

Meanwhile, a plurality of semiconductor device packages according to the present invention described above may be arrayed on a substrate, and optical members such as a light guide plate, a prism sheet, and a diffusion sheet may be disposed on a light path of the semiconductor device package.

In addition, it may be implemented as a light source device including the semiconductor device package according to the present invention.

In addition, the light source device includes a light source module including a substrate and a semiconductor device package according to the present invention, a heat sink for dissipating heat from the light source module, and a power supply unit that processes or converts an electrical signal received from the outside and provides it to the light source module may include For example, the light source device may include a lamp, a head lamp, or a street lamp. In addition, the light source device according to the embodiment may be variously applied to products requiring output light.

In addition, the light source device includes a bottom cover, a reflecting plate disposed on the bottom cover, a light emitting module that emits light and includes a semiconductor element, and a light guide plate disposed in front of the reflecting plate and guiding light emitted from the light emitting module to the front; An optical sheet including prism sheets disposed in front of the light guide plate, a display panel disposed in front of the optical sheet, an image signal output circuit connected to the display panel and supplying an image signal to the display panel, disposed in front of the display panel A color filter may be included. Here, the bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.

As another example of the light source device, the head lamp is a light emitting module including a light emitting device package disposed on a substrate, a reflector that reflects light irradiated from the light emitting module in a predetermined direction, for example, forward, and is reflected by the reflector It may include a lens that refracts light forward, and a shade that blocks or reflects a portion of light reflected by the reflector and directed to the lens to form a light distribution pattern desired by a designer.

Although the present invention has been described as above, those of ordinary skill in the art to which the present invention pertains will recognize that the present invention may be implemented in other forms while maintaining the technical spirit and essential features of the present invention .

The scope of the present invention will be defined by the claims, but all changes or modifications derived from the configuration directly derived from the claims as well as other equivalent configurations are also included in the scope of the present invention. should be interpreted as

10: body
20: semiconductor device
22: first bonding unit
24: second bonding unit
30: opening
32: first opening
34: second opening
50: recess
60: adhesive
70: molding member
80: contact layer
82: first contact layer
84: second contact layer

Claims (19)

a body having a flat lower surface, an upper surface parallel to the lower surface, and first and second openings penetrating the upper and lower surfaces;
a semiconductor device disposed on the body;
an adhesive disposed between the body and the semiconductor device;
a molding member disposed to surround the semiconductor device; and
a recess disposed between the first opening and the second opening and concavely disposed in a direction from an upper surface to a lower surface of the body; and
The semiconductor device includes first and second bonding portions respectively disposed on the first and second openings,
The outer surface of the molding member is disposed on the same plane as the outer surface of the body,
A first contact layer is disposed between the first bonding portion and the first opening, and a second contact layer is disposed between the second bonding portion and the second opening, respectively;
The adhesive is in contact with the upper surface of the body, the lower surface of the semiconductor device, inner surfaces of the first and second bonding portions, and inner surfaces of the first and second contact layers,
A ratio of the thickness of the recess to the thickness of the first and second openings is greater than 0 and less than or equal to 5/6;
The adhesive is disposed in the recess, the semiconductor device package. delete delete delete delete delete The method of claim 1,
The first opening and the second opening include a first angle θ1 between the inner surfaces and a second angle θ2 between the outer surfaces with respect to the lower surfaces of the first opening and the second opening,
The first angle and the second angle are in the range of 0 degrees or more to 90 degrees or less,
The first angle is equal to or smaller than the second angle, the semiconductor device package. delete The method of claim 1,
A width of lower surfaces of the first and second openings is greater than a width of upper surfaces of the first and second openings. delete delete delete delete delete The method of claim 1,
The molding member includes a first layer including a wavelength conversion material, a second layer disposed on the side of the semiconductor device under the first layer, and a third layer disposed to surround the second layer,
The second layer is composed of a transparent resin having a refractive index different from that of the semiconductor device,
The third layer is composed of a resin including a reflective material, a semiconductor device package. delete The method of claim 1,
The horizontal widths of the upper portions of the first opening and the second opening are greater than the horizontal widths of the first bonding portion and the second bonding portion,
A horizontal width of the first contact layer is greater than a horizontal width of the first bonding portion and greater than a horizontal width of an upper portion of the first opening,
A horizontal width of the second contact layer is greater than a horizontal width of the second bonding portion and greater than a horizontal width of an upper portion of the second opening. delete delete

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