KR102368618B1 - System on chip and method of design layout for the same - Google Patents

Abstract

The present invention relates to a system on a chip and a layout design method thereof, and more particularly, to a substrate including an active pattern thereon; a gate electrode crossing the active pattern and extending in a first direction parallel to a top surface of the substrate; and a first metal layer electrically connected to the active pattern and the gate electrode. In this case, the first metal layer may include: a first metal wire extending in the first direction; and a second metal wire spaced apart from the first metal wire in the first direction and extending in a second direction intersecting the first direction, wherein the first metal wire has a first direction in the second direction. a sidewall, wherein the second metal wiring includes a second sidewall in the second direction, wherein the first sidewall and the second sidewall face each other, and a length of the first sidewall is twice a minimum line width to 3 times.

Description

System on chip and method of design layout for the same

The present invention relates to a system-on-chip and a layout design method for forming the same, and to a system-on-chip including a plurality of standard cells and a layout design method for metal layers formed thereon.

Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing cost, a semiconductor device is in the spotlight as an important element in the electronic industry. The semiconductor devices may be classified into a semiconductor memory device for storing logic data, a semiconductor logic device for processing logic data, and a hybrid semiconductor device including a storage element and a logic element. As the electronic industry is highly developed, demands for characteristics of semiconductor devices are increasing. For example, there is an increasing demand for high reliability, high speed and/or multifunctionality of semiconductor devices. In order to satisfy these required characteristics, structures in semiconductor devices are becoming increasingly complex, and semiconductor devices are becoming more and more highly integrated. Meanwhile, semiconductor devices include a semiconductor memory device for storing logic data, a semiconductor logic device for processing logic data, and a system-on-chip (system-on-chip) including both functions of the semiconductor memory device and the semiconductor logic device. SoC) and the like.

SUMMARY OF THE INVENTION An object of the present invention is to provide a system-on-chip having a reduced standard cell height.

Another object of the present invention is to provide a system-on-chip layout design method capable of reducing the height of a standard cell.

According to a concept of the present invention, a system on a chip includes: a substrate including an active pattern thereon; a gate electrode crossing the active pattern and extending in a first direction parallel to a top surface of the substrate; and a first metal layer electrically connected to the active pattern and the gate electrode. In this case, the first metal layer may include: a first metal wire extending in the first direction; and a second metal wire spaced apart from the first metal wire in the first direction and extending in a second direction intersecting the first direction, wherein the first metal wire has a first direction in the second direction. a sidewall, wherein the second metal wiring includes a second sidewall in the second direction, wherein the first sidewall and the second sidewall face each other, and a length of the first sidewall is twice a minimum line width to 3 times.

The minimum line width may be a minimum width of the second metal wiring in the first direction.

The first metal layer may further include a third metal wire extending in the second direction, the second metal wire and the third metal wire being spaced apart from each other by a first distance in the first direction, A second distance between the sidewall and the second sidewall may be substantially equal to or greater than the first distance, and may be less than 1.2 times the first distance.

The first metal layer may include: a third metal wire extending in the second direction; and a fourth metal wire spaced apart from the third metal wire in the first direction and extending in the first direction, wherein the third metal wire includes a third sidewall in the second direction, the fourth metal wiring includes a fourth sidewall in the second direction, the third sidewall and the fourth sidewall face each other, and a length of the fourth sidewall is smaller than a length of the first sidewall; A second distance between the first sidewall and the second sidewall may be smaller than a third distance between the third sidewall and the fourth sidewall.

The system on chip further includes a second metal layer on the first metal layer, wherein the second metal layer includes fifth metal wires extending in the first direction parallel to each other, and any one of the fifth metal The wiring may be electrically connected to the first metal wiring to provide pin regions for routing.

A plurality of second metal wires may be provided, the second metal wires may be spaced apart from each other in the first direction, and the other fifth metal wire may electrically connect the second metal wires spaced apart from each other.

The system-on-chip further includes a third metal layer on the second metal layer, wherein the third metal layer includes sixth metal wires extending in the second direction parallel to each other, and any one of the sixth metal A wiring may be connected to the pin regions of the fifth metal wirings to be electrically connected to the first metal wirings.

The system on chip may include source/drain regions respectively formed on both sides of the gate electrode and on the active pattern; and contacts respectively connected to the gate electrode and the source/drain regions, wherein the first and second metal lines may be electrically connected to the contacts.

A method for designing a layout of a system on a chip according to another concept of the present invention may include configuring a layout pattern for forming a system on a chip including a plurality of standard cells. In this case, configuring the layout pattern may include configuring a first metal layout corresponding to the first metal layer. The first metal layout may include: a first metal pattern extending in a first direction; and a second metal pattern spaced apart from the first metal pattern in the first direction and extending in a second direction intersecting the first direction, wherein the first and second metal patterns include a second metal pattern facing each other. Each of the first and second sidewalls may be included, and the distance between the first sidewall and the second sidewall may be substantially equal to or greater than a minimum separation distance allowed by a design rule of a layout, and may be less than 1.2 times the minimum separation distance. .

The length of the first sidewall may be 2 to 3 times the minimum line width allowed by the design rule of the layout.

A length of the first sidewall may be greater than or equal to a minimum sidewall length that may be spaced apart from the second sidewall by the minimum separation distance, and a length of the first sidewall may be less than a length of the second sidewall.

The first metal layout may include: a third metal pattern extending in the first direction; and a fourth metal pattern spaced apart from the third metal pattern in the first direction and extending in the second direction, wherein the third and fourth metal patterns have third and fourth sidewalls facing each other and a length of the third sidewall may be smaller than a length of the first sidewall, and a distance between the third sidewall and the fourth sidewall may be greater than a distance between the first sidewall and the second sidewall.

A length of the third sidewall may be substantially equal to or greater than a minimum line width allowed by a design rule of a layout, and may be less than twice the minimum line width.

Composing the layout pattern further includes configuring a second metal layout corresponding to the second metal layer and a third metal layout corresponding to the third metal layer, wherein the first to third metal layers are sequentially disposed on the substrate. , wherein the second metal layout includes fifth metal patterns extending in the first direction parallel to each other, and the third metal layout includes a sixth metal pattern extending in the second direction parallel to each other and the first direction may be an extension direction of the gate pattern.

At least one of the fifth metal patterns may overlap the first metal pattern, and the fifth metal pattern may include a plurality of pin regions for routing.

In the system on chip and the layout thereof according to the present invention, by disposing wide metal wirings on the first metal layer, it is possible to reduce the spacing between metal wiring patterns and reduce the cell height. Furthermore, through the second metal layer capable of securing pin regions, a degree of freedom in implementing a schematic circuit may be increased and smooth routing may be performed.

1 is a block diagram illustrating a configuration of an electronic device including a semiconductor device according to embodiments of the present invention.
2 is a plan view of a semiconductor device according to embodiments of the present invention.
3 is a flowchart illustrating a method of designing and manufacturing a semiconductor device according to embodiments of the present invention.
4 is a plan view illustrating layout patterns for explaining a method of designing a metal layout according to embodiments of the present invention.
5 and 6 are plan views illustrating a layout of a logic cell for explaining a method of designing a metal layout according to embodiments of the present invention.
7, 8, and 10 are plan views illustrating a layout of a logic cell for explaining a method of designing a metal layout according to other embodiments of the present invention.
9 is a plan view illustrating fin regions of a first lower metal pattern, a wide metal pattern, and a first intermediate metal pattern according to embodiments of the present invention.
11 to 13 are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention, and are cross-sectional views corresponding to lines II', II-II', and III-III' of FIG. 10 , respectively.
14 is a block diagram of an electronic system including a semiconductor device according to embodiments of the present invention.
15 to 17 are diagrams illustrating examples of multimedia devices including semiconductor devices according to embodiments of the present invention.

In order to fully understand the configuration and effect of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various forms and various modifications may be made. However, it is provided so that the disclosure of the present invention is complete through the description of the present embodiments, and to fully inform those of ordinary skill in the art to which the present invention belongs, the scope of the invention.

In this specification, when a component is referred to as being on another component, it means that it may be directly formed on the other component or a third component may be interposed therebetween. In addition, in the drawings, the thickness of the components is exaggerated for effective description of the technical content. Parts indicated with like reference numerals throughout the specification indicate like elements.

Embodiments described herein will be described with reference to cross-sectional and/or plan views, which are ideal illustrative views of the present invention. In the drawings, thicknesses of films and regions are exaggerated for effective description of technical content. Accordingly, the regions illustrated in the drawings have a schematic nature, and the shapes of the illustrated regions in the drawings are intended to illustrate specific shapes of regions of the device and not to limit the scope of the invention. In various embodiments of the present specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Embodiments described and illustrated herein also include complementary embodiments thereof.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, the terms 'comprises' and/or 'comprising' do not exclude the presence or addition of one or more other components.

1 is a block diagram illustrating a configuration of an electronic device including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 1 , an electronic device 1 may include a semiconductor chip 10 . The semiconductor chip 10 may include a processor 11 , an embedded memory 13 , and a cache memory 15 . The semiconductor chip 10 may be a system on chip.

The processor 11 may include one or more processor cores (C1-Cn). The one or more processor cores C1-Cn may process data and signals. The processor cores C1-Cn may include semiconductor devices according to embodiments of the present invention, and may include a plurality of logic cells, which will be described later with reference to FIG. 2 .

The electronic device 1 may perform a unique function by using the processed data and signals. For example, the processor 11 may be an application processor.

The embedded memory 13 may exchange first data DAT1 with the processor 11 . The first data DAT1 is data processed or to be processed by one or more processor cores C1-Cn. The embedded memory 13 may manage the first data DAT1 . For example, the embedded memory 13 may buffer the first data DAT1 . That is, the embedded memory 13 may operate as a buffer memory or a working memory of the processor 11 .

According to an embodiment, the electronic device 1 may be applied to a wearable electronic device. The wearable electronic device may perform more functions requiring a small amount of calculation than a function requiring a large amount of calculation. Accordingly, when the electronic device 1 is applied to a wearable electronic device, the embedded memory 13 may not have a large buffer capacity.

The embedded memory 13 may be SRAM. The SRAM may operate at a faster speed than DRAM. When the SRAM is embedded in the semiconductor chip 10 , the electronic device 1 having a small size and operating at a high speed can be implemented. Furthermore, when the SRAM is embedded in the semiconductor chip 10 , the consumption of active power of the electronic device 1 may be reduced. For example, the SRAM may include semiconductor devices according to embodiments of the present invention.

The cache memory 15 may be mounted on the semiconductor chip 10 together with the one or more processor cores C1 to Cn. The cache memory 15 may store cache data DATc. The cache data DATc may be data used by the one or more processor cores C1 to Cn. The cache memory 15 has a small storage capacity, but can operate at a very high speed. For example, the cache memory 15 may include SRAM. When the cache memory 15 is used, the number and time of the processor 11 accessing the embedded memory 13 may be reduced. Accordingly, when the cache memory 15 is used, the operating speed of the electronic device 1 may be increased.

For ease of understanding, in FIG. 1 , the cache memory 15 is illustrated as a separate component from the processor 11 . However, the cache memory 15 may be configured to be included in the processor 11 . 1 is not intended to limit the protection scope of the technical spirit of the present invention.

The processor 11 , the embedded memory 13 , and the cache memory 15 may transmit data based on various interface protocols. For example, the processor 11, the embedded memory 13, and the cache memory 15 are USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnect) Express, ATA (Advanced Technology Attachment) ), PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), UFS (Universal Flash Storage), etc., data can be transmitted based on one or more interface protocols.

2 is a plan view of a semiconductor device according to embodiments of the present invention.

Referring to FIG. 2 , a semiconductor device according to an exemplary embodiment may include a plurality of logic cells C1 , C2 , C3 , and C4 provided on a substrate. The plurality of logic cells C1 , C2 , C3 , and C4 may include a plurality of standard cells. In addition, each of the logic cells C1 , C2 , C3 , and C4 may include a plurality of transistors. For example, the semiconductor device includes a first logic cell C1, a second logic cell C2 spaced apart from the first logic cell C1 in a first direction Y, and the first logic cell C1 and A third logic cell C3 spaced apart in a second direction X crossing the first direction Y, and a fourth logic spaced apart from the second logic cell C2 in the second direction X It may include a cell C4. Each of the logic cells C1 , C2 , C3 , and C4 may include active regions separated by second device isolation layers ST2 . Each of the logic cells C1 , C2 , C3 , and C4 may include a PMOSFET region PR and an NMOSFET region NR separated by the second device isolation layers ST2 .

For example, the PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in the first direction Y. The PMOSFET region PR of the first logic cell C1 may be adjacent to the PMOSFET region PR of the second logic cell C2 in the first direction Y. Hereinafter, in the present specification, a logic cell may refer to a unit for performing one logic operation. The number of logic cells is illustrated as four, but is not limited thereto.

3 is a flowchart illustrating a method of designing and manufacturing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 3 , a high level design of a semiconductor integrated circuit may be performed using a computer system ( S110 ). High-level design may mean describing a design target integrated circuit in a language higher than a computer language. For example, a higher-level language such as C language can be used. Circuits designed by high-level design can be expressed more specifically by Register Transfer Level (RTL) coding or simulation. Furthermore, the code generated by the register transfer level coding may be converted into a netlist and synthesized into an entire semiconductor device. The synthesized schematic circuit is verified by a simulation tool, and an adjustment process may be accompanied according to the verification result.

A layout design for implementing a logically completed semiconductor integrated circuit on a silicon substrate may be performed ( S120 ). For example, layout design may be performed by referring to a schematic circuit synthesized in a higher-level design or a netlist corresponding thereto. Layout design may include a routing procedure for arranging and connecting various cells provided from a cell library according to a prescribed design rule. In layout design related to embodiments of the present invention, designing a plurality of metal layouts may be included. The plurality of metal layouts may correspond to a plurality of metal layers sequentially stacked on a silicon substrate. While the metal patterns are disposed for each of the metal layouts, routing in which a data path is connected may be performed.

The cell library for layout design may also include information on cell operation, speed, and power consumption. A cell library for expressing a specific gate level circuit as a layout is defined in most layout design tools. Layout may actually be a procedure for defining the shape or size of a pattern for configuring transistors and metal wirings to be formed on a silicon substrate. For example, in order to actually form an inverter circuit on a silicon substrate, it is possible to appropriately arrange layout patterns such as PMOS, NMOS, N-WELL, gate lines, and metal wirings to be disposed thereon. For this, first, a suitable one can be searched and selected from among inverters already defined in the cell library. In addition, routing for selected and deployed cells may be performed. Most of these series of processes may be performed automatically or manually by the layout design tool.

After routing, verification of the layout may be performed whether there is a part that violates the design rule. Items to be verified include DRC (Design Rule Check) that verifies that the layout is properly aligned with the design rule, ERC (Electronical Rule Check) that verifies whether the layout is properly executed without electrical breakage, and whether the layout matches the gate-level netlist It may include LVS (Layout vs Schematic) to check.

An optical proximity correction (OPC) procedure may be performed (S130). Layout patterns obtained through layout design may be implemented on a silicon substrate by using a photolithography process. In this case, optical proximity correction may be a technique for correcting distortion that may occur in a photolithography process. That is, through the optical proximity correction, it is possible to correct distortions such as refraction or process effects that occur due to the characteristics of light during exposure using the laid out pattern. While performing optical proximity correction, the shape and position of the designed layout patterns may be slightly changed.

A photomask may be manufactured based on the layout changed by the optical proximity correction (S140). In general, a photomask may be manufactured in a manner that depicts layout patterns using a thin chrome film applied on a glass substrate.

A semiconductor device may be manufactured using the generated photomask (S150). In a manufacturing process of a semiconductor device using a photomask, various types of exposure and etching processes may be repeated. Through these processes, shapes of patterns configured during layout design may be sequentially formed on a silicon substrate.

4 is a plan view illustrating layout patterns for explaining a method of designing a metal layout according to embodiments of the present invention. Specifically, FIG. 4 may show a first metal layout for implementing a first metal layer on a semiconductor substrate.

Referring to FIG. 4 , first lower metal patterns M11 , a wide metal pattern M11 ′, and second lower metal patterns M12 may be provided. The first lower metal patterns M11 and the wide metal pattern M11 ′ may have a line shape extending in the first direction (Y). The second lower metal patterns M12 may have a line shape extending in a second direction (X) crossing the first direction (Y). The first lower metal patterns M11 may include first to third sub-patterns M11a, M11b, and M11c.

Specifically, each of the first lower metal patterns M11 includes narrow horizontal sidewalls TP1 in the second direction (X) and a first type in the first direction (Y). vertical sidewalls (SP1). The wide metal pattern M11' includes wide horizontal sidewalls (WP1) in the second direction (X) and second longitudinal sidewalls (SP1') in the first direction (Y). may include A length of the wide lateral sidewalls WP1 of the wide metal pattern M11 ′ may be greater than a length of the narrow lateral sidewalls TP1 of the first lower metal pattern M11 . A length of the second type sidewalls SP1 ′ of the wide metal pattern M11 ′ may be smaller than a length of the first type sidewalls SP1 of the first lower metal pattern M11 . Each of the second lower metal patterns M12 may have second sidewalls SP2 in the second direction X.

Each of the first lower metal patterns M11 may have a first line width W1 in the second direction X, and the wide metal pattern M11 ′ may extend in the second direction X. may have a second line width W2 of In addition, each of the second lower metal patterns M12 may have a third line width W3 in the first direction Y. For example, the first line width W1 and the third line width W3 may be substantially the same. The second line width W2 may be larger than the first and third line widths W1 and W3. The first and third line widths W1 and W3 may correspond to a minimum line width allowed by a design rule prescribed when designing a corresponding layout. However, this is only one embodiment, and in other embodiments, the first and third line widths W1 and W3 may be larger than the minimum line width. As another example, the first line width W1 may be substantially equal to the length of the narrow lateral sidewalls TP1 , and the second line width W2 may be substantially equal to the length of the wide lateral sidewalls WP1 . can be the same as

The metal patterns M11, M11', and M12 may be spaced apart from each other in the first direction Y and the second direction X. In this case, the metal patterns M11, M11', and M12 may be spaced apart from each other by at least a minimum spacing allowed by the design rule. The minimum separation distance may be defined according to a limit of patterning in a photolithography process, and further, it may be automatically defined in a layout design tool. For example, the second lower metal patterns M12 may be spaced apart from each other by a second distance D2 in the first direction Y. Here, the second distance D2 may be the minimum separation distance. This is only an example when they are disposed closest to each other, and the second distance D2 may be greater than the minimum separation distance.

On the other hand, as described above with reference to the optical proximity correction ( S130 ) of FIG. 3 , while performing a photolithography process based on the layout patterns, distortion may occur in the shapes of patterns and the spacing between the patterns. In particular, since the first lower metal patterns M11 have narrow lateral sidewalls TP1 , distortion in a gap between the pattern adjacent to the narrow lateral sidewall TP1 and the first lower metal pattern M11 is distorted. This can happen greatly. This is because, since the narrow lateral sidewalls TP1 have very fine sizes, the effect of refraction of light increases. Accordingly, a distance between the pattern adjacent to the narrow lateral sidewall TP1 and the first lower metal pattern M11 may be greater than the minimum separation distance.

For example, the second lower metal pattern M12 and the third sub-pattern M11c may be respectively disposed adjacent to the pair of narrow lateral sidewalls TP1 of the first sub-pattern M11a. . Specifically, any one of the narrow lateral sidewalls TP1 may face the second sidewall SP2 of the second lower metal pattern M12, and the other narrow lateral sidewall TP1 may have the first It may face the narrow lateral sidewall TP1 of the third sub-pattern M11c. In this case, the first sub-pattern M11a and the second lower metal pattern M12 are spaced apart from each other by a first distance D1 in the first direction Y, and the first sub-pattern M11a and the second lower metal pattern M12 are spaced apart from each other by a first distance D1. The three sub-patterns M11c may be spaced apart from each other by the first distance D1 in the first direction Y. Here, the first distance D1 may be greater than the second distance D2, which is the minimum separation distance. Specifically, the first distance D1 may be at least equal to or greater than 1.2 times the minimum separation distance.

On the other hand, a second sub-pattern M11b may be disposed adjacent to the first longitudinal sidewall SP1 of the first sub-pattern M11a. The first longitudinal sidewall SP1 of the first sub-pattern M11a may face the first longitudinal sidewall SP1 of the second sub-pattern M11b. Since the first longitudinal sidewall SP1 is relatively longer than the narrow transverse sidewall TP1, a distortion of a gap between patterns may be reduced. Accordingly, the first and second sub-patterns M11a and M11b may be spaced apart from each other by the second distance D2 that is the minimum separation distance in the second direction X.

The wide metal pattern M11 ′ may be a line extending in the first direction Y in the same manner as the first lower metal patterns M11 . However, unlike the first lower metal patterns M11 , the wide metal pattern M11 ′ may include a pair of wide lateral sidewalls WP1 . For example, the second lower metal pattern M12 may be disposed adjacent to the wide lateral sidewall WP1 . Since the wide lateral sidewall WP1 is relatively longer than the narrow lateral sidewall TP1 , a distortion of a gap between patterns may be reduced. Accordingly, the wide metal pattern M11 ′ and the second lower metal pattern M12 may be spaced apart from each other by a third distance D3 in the first direction Y. For example, the third distance D3 may be substantially the same as the second distance D2 that is the minimum separation distance. As another example, the third distance D3 may be greater than the second distance D2 and smaller than the first distance D1 .

In summary, the first and second type sidewalls SP1 and SP1 ′ and the second sidewalls SP2 can secure the pattern adjacent thereto and the minimum separation distance (eg, D2 ). can be sidewalls. For example, the lengths of the first and second type sidewalls SP1 and SP1 ′ and the second sidewalls SP2 may be greater than about three times the minimum line width (eg, W1 , W3 ). .

The narrow lateral sidewalls TP1 may be sidewalls capable of securing a separation distance (eg, D1 ) greater than the minimum separation distance from a pattern adjacent thereto. For example, the narrow lateral sidewalls TP1 may be equal to or greater than the minimum line width and may be smaller than about twice the minimum line width.

The wide lateral sidewalls WP1 may be sidewalls having the smallest length that can secure the minimum separation distance from the pattern adjacent thereto. For example, the wide lateral sidewalls WP1 may be about 2 to about 3 times the minimum line width.

However, the range of the length of each of the sidewalls of the patterns may be defined differently according to a design rule, and is not particularly limited.

5 and 6 are plan views illustrating a layout of a logic cell for explaining a method of designing a metal layout according to embodiments of the present invention. Specifically, FIG. 5 may show a first metal layout for implementing the first metal layer on any one logic cell of FIG. 2 . 6 may additionally show a second metal layout for implementing a second metal layer on the first metal layer. 5 and 6 show an embodiment to which the first lower metal patterns M11 described above with reference to FIG. 4 are applied, and the wide metal pattern M11' is omitted.

Referring to FIG. 5 , first, layout patterns defining active regions may be provided. The active regions may include a PMOSFET region PR and an NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in the first direction Y.

Gate patterns GP extending in the first direction Y may be provided to cross the PMOSFET region PR and the NMOSFET region NR. The gate patterns GP may be spaced apart from each other in the second direction X crossing the first direction Y.

Additionally, although not shown, active patterns to be formed on the semiconductor substrate and layout patterns defining source/drain regions may be provided in the PMOSFET region PR and the NMOSFET region NR. Furthermore, although not shown, layout patterns defining source/drain contacts and gate contacts connected to the first metal layer may be provided.

A first metal layout defining the first metal layer may be provided. The first metal layout may include first to fifth lower metal patterns M11, M12, M13, M14, and M15. The first to third lower metal patterns M11 , M12 , and M13 include metal lines electrically connected to the PMOSFET region PR, the NMOSFET region NR, or the gate patterns GP, respectively. can be defined Each of the fourth and fifth lower metal patterns M14 and M15 includes a metal wire that is a passage through which a drain voltage Vdd, that is, a power voltage, and a passage through which a source voltage Vss, that is, a ground voltage, is provided. You can define a phosphorus metal wiring.

The first lower metal patterns M11 may have a line shape extending in the first direction Y, and a detailed description thereof has been described with reference to FIG. 4 above. Each of the first lower metal patterns M11 may include narrow lateral sidewalls TP1 and first longitudinal sidewalls SP1 . The first lower metal patterns M11 may include first to fourth sub-patterns M11a-M11d. The second to fifth lower metal patterns M12, M13, M14, and M15 may include second to fifth sidewalls SP2, SP3, SP4, and SP5 in the second direction X, respectively. can

The first to fifth lower metal patterns M11, M12, M13, M14, and M15 may be spaced apart from each other in first and second directions Y and X. The logic cell shown in FIG. 5 may have a first height H1 in the first direction Y. The first height H1 may be a length from the center of the fourth lower metal pattern M14 to the center of the fifth lower metal pattern M15. The first height H1 may be a minimum cell height allowed by a corresponding design rule. In this case, in order to satisfy the minimum cell height, the first to fifth lower metal patterns M11 , M12 , M13 , M14 , and M15 are aligned in the first direction Y by the minimum separation distance allowed by the design rule. can be separated from each other.

For example, the fourth sidewall SP4 of the fourth lower metal pattern M14 faces the second sidewall SP2 of the second lower metal pattern M12, and in this case, the second and fourth lower portions The metal patterns M12 and M14 may be spaced apart from each other by a second distance D2 in the first direction Y. Here, the second distance D2 may be the same as the second distance D2 described above with reference to FIG. 4 , that is, it may represent the minimum separation distance.

In the case of the second lower metal pattern M12 and the third lower metal pattern M13 , relatively long second and third sidewalls SP2 and SP3 may face each other. Accordingly, the second and third lower metal patterns M12 and M13 may be spaced apart from each other by a second distance D2 in the first direction Y.

Meanwhile, in the case of the second lower metal pattern M12 and the second sub pattern M11b , the second sidewall SP2 may face the relatively short narrow lateral sidewall TP1 . Accordingly, the second lower metal pattern M12 and the second sub pattern M11b may be spaced apart from each other by a first distance D1 in the first direction Y. Here, the first distance D1 may be the same as the first distance D1 described above with reference to FIG. 4 , that is, it may be equal to or greater than 1.2 times the minimum separation distance.

The second lower metal pattern M12 may include a relatively short sidewall by including a portion extending in the first direction Y. In this case, the one sidewall may be the second narrow lateral sidewall TP2 . Meanwhile, the narrow lateral sidewall TP1 of the fourth sub-pattern M11d may face the second narrow lateral sidewall TP2 . Accordingly, the second lower metal pattern M12 and the fourth sub-pattern M11d may be spaced apart from each other by a first distance D1 in the first direction Y.

In the case of the third lower metal pattern M13 and the third sub-pattern M11c, the third sidewall SP3 may face the relatively short narrow lateral sidewall TP1. Accordingly, the third lower metal pattern M13 and the third sub-pattern M11c may be spaced apart from each other by a first distance D1 in the first direction Y.

As a result, due to the first lower metal patterns M11 including the narrow lateral sidewalls TP1 , the first lower metal patterns M11 and adjacent patterns are inevitably formed in the first direction. As (Y), it is necessary to secure a separation distance equal to at least the first distance D1. Accordingly, the logic cell has a limit in that a minimum cell height (ie, H1) of a certain value or more must be secured.

Also, in order to reduce the first height H1 , there may be a method of reducing the length of each of the first lower metal patterns M11 in the first direction Y. However, in this case, the number of pin regions for routing of the first lower metal patterns M11 is reduced, and a problem in routing may occur. As a result, a method for reducing the length of each of the first lower metal patterns M11 may also be limited.

Referring to FIG. 6 , a second metal layout defining a second metal layer may be provided on the first metal layout. For convenience of description, the active regions PR and NR described above with reference to FIG. 5 are omitted.

The second metal layout may include intermediate metal patterns M2 in the form of lines extending in the second direction (X). The intermediate metal patterns M2 may be respectively connected to the first to third lower metal patterns M11 , M12 , and M13 through second vias V2 .

Although not shown, additional metal layouts may be provided on the second metal layout. These may define additional metal layers stacked on the second metal layer. Accordingly, routing in which data paths are connected can be sequentially performed.

7, 8, and 10 are plan views illustrating a layout of a logic cell for explaining a method of designing a metal layout according to other embodiments of the present invention. Specifically, FIG. 7 may show a first metal layout for implementing the first metal layer on any one logic cell of FIG. 2 . 8 may additionally show a second metal layout for implementing a second metal layer on the first metal layer. 10 may additionally show a third metal layout for implementing a third metal layer on the second metal layer. 7, 8, and 10 show an embodiment to which the wide metal pattern M11 ′ described above with reference to FIG. 4 is applied, and the first lower metal patterns M11 are omitted.

In this embodiment, detailed descriptions of technical features overlapping with those described above with reference to FIGS. 5 and 6 will be omitted, and differences will be described in detail. The same reference numerals may be provided for the same components as the layout for explaining the concept of the present invention.

Referring to FIG. 7 , a first metal layout defining a first metal layer may be provided on the layout patterns including the gate patterns GP and the active regions PR and NR. The first metal layout may include wide metal patterns M11 ′ and second to fifth lower metal patterns M12 , M13 , M14 , and M15 . The wide metal patterns M11 ′ and the second and third lower metal patterns M12 and M13 are the PMOSFET region PR, the NMOSFET region NR, or the gate patterns GP, respectively. It is possible to define metal wires electrically connected to the .

The wide metal patterns M11 ′ may have a line shape extending in the first direction Y, and a detailed description thereof is the same as described above with reference to FIG. 4 . Each of the wide metal patterns M11 ′ may include wide lateral sidewalls WP1 and second longitudinal sidewalls SP1 ′. The wide metal patterns M11' may include first to fourth wide sub-patterns M11'a-M11'd. The third lower metal patterns M13 may include first and second horizontal patterns M13a and M13b.

The logic cell shown in FIG. 7 may have a second height H2 in the first direction Y. The second height H2 may be a length from the center of the fourth lower metal pattern M14 to the center of the fifth lower metal pattern M15 . The second height H2 may be a minimum cell height allowed by a corresponding design rule. Here, the second height H2 may be smaller than the first height H1 described with reference to FIG. 5 . In this case, the respective heights of the PMOSFET region PR and the NMOSFET region NR may be smaller than the heights of the PMOSFET region PR and the NMOSFET region NR described with reference to FIG. 5 . Alternatively, the interval between the PMOSFET region PR and the NMOSFET region NR may be smaller than the interval between the PMOSFET region PR and the NMOSFET region NR described with reference to FIG. 5 . Hereinafter, unlike FIG. 5 , it will be described that the first metal layout according to the present embodiment can be applied to the logic cell having the second height H2 .

The wide metal patterns M11 ′ and the second to fifth lower metal patterns M12 , M13 , M14 , and M15 may be spaced apart from each other in first and second directions Y and X. In this case, in order to satisfy the minimum cell height (ie, H2), the wide metal patterns M11 ′ and the second to fifth lower metal patterns M12 , M13 , M14 and M15 follow the design rule. They may be spaced apart from each other in the first direction (Y) by an allowable minimum separation distance.

For example, the second and fourth lower metal patterns M12 and M14 may be spaced apart from each other by a second distance D2 in the first direction Y. The first horizontal pattern M13a may be spaced apart from the second lower metal pattern M12 by the second distance D2 in the first direction Y.

Meanwhile, in the case of the first horizontal pattern M13a and the third wide sub-pattern M11'c, a third sidewall SP3 may face the wide horizontal sidewall WP1. Accordingly, the first horizontal pattern M13a and the third wide sub-pattern M11'c may be spaced apart from each other by a third distance D3 in the first direction Y. Here, the third distance D3 may be the same as the third distance D3 described above with reference to FIG. 4 . That is, the third distance D3 may be substantially equal to or greater than the minimum separation distance (ie, D2), and may be less than 1.2 times the minimum separation distance.

In the case of the second horizontal pattern M13b and the third wide sub-pattern M11'c, a third sidewall SP3 may also face the wide horizontal sidewall WP1. Accordingly, the second horizontal pattern M13b and the third wide sub-pattern M11'c may be spaced apart from each other by a third distance D3 in the first direction Y.

As a result, due to the wide metal patterns M11 ′ including the wide lateral sidewalls TP1 , the wide metal patterns M11 ′ and patterns adjacent to the wide metal patterns M11 ′ move in the first direction Y. A separation distance equal to at least the third distance D3 needs to be secured. In this case, since the third distance D3 is smaller than the first distance D1 described above, the height of the cell (ie, H2 ) may be reduced compared to the case where the first lower metal patterns M11 of FIG. 5 are applied. .

Furthermore, the wide metal patterns M11 ′ may have a shorter length in the first direction Y than the first lower metal patterns M11 of FIG. 5 . Accordingly, the logic cell according to the present embodiment may have the second height H2. In this case, a problem of routing that may occur due to a reduction in the length of the wide metal patterns M11 ′ may be solved by a second metal layout (ie, a second metal layer) to be described later.

Referring to FIG. 8 , a second metal layout defining a second metal layer may be provided on the first metal layout. For convenience of description, the active regions PR and NR are omitted.

The second metal layout may include first to fifth intermediate metal patterns M21 to M25 in the form of lines extending in the first direction Y. The first, second, third, and fifth intermediate metal patterns M21 - M23 and M25 are the first to fourth wide sub-patterns M11'a-M11'd and second vias, respectively. V2) can be connected. The first, second, third, and fifth intermediate metal patterns M21 - M23 and M25 may sufficiently provide pin regions for routing while extending in the first direction (Y).

9 is a plan view illustrating fin areas PA of a first lower metal pattern M11, a wide metal pattern M11', and a first intermediate metal pattern M21 according to embodiments of the present disclosure; am.

Referring to FIG. 9 , the first lower metal pattern M11 may have three fin areas PA, and the wide metal pattern M11' may have two fin areas PA. That is, since the first lower metal pattern M11 is relatively longer than the wide metal pattern M11 ′, it may have more fin areas PA. The fin areas PA may be positions at which a via for connecting a metal pattern to another metal pattern disposed thereon may be formed. Accordingly, since the wide metal pattern M11 ′ has fewer pin areas PA than the first lower metal pattern M11 , the wide metal pattern M11 ′ may have limitations in routing performance.

Meanwhile, since the first intermediate metal pattern M21 has a longer length than that of the first lower metal pattern M11 , it may have five fin areas PA. When the first intermediate metal pattern M21 and the wide metal pattern M11 ′ are coupled to each other, the wide metal pattern M11 ′ may enable expansion of pin areas PA for routing.

Referring back to FIG. 8 , in order to compensate for insufficient fin areas PA of the wide metal patterns M11 ′, the first, second, third and fifth intermediate metal patterns M21 - M23 , M25) may be provided. Through the first, second, third and fifth intermediate metal patterns M21 - M23 and M25 , the wide metal patterns M11 ′ are identical to the first lower metal patterns M11 of FIG. 5 . Routing can be done.

The fourth intermediate metal pattern M24 may be connected to the first and second horizontal patterns M13a and M13b through the second vias V2 to electrically connect them. That is, through the fourth intermediate metal pattern M24 , the first and second horizontal patterns M13a and M13b may perform the same routing as the third lower metal pattern M13 of FIG. 5 .

Referring to FIG. 10 , a third metal layout defining a third metal layer may be provided on the second metal layout.

The third metal layout may include first to fourth upper metal patterns M31 to M34 having a line shape extending in the second direction X. The first to fourth upper metal patterns M31 - M34 may be respectively connected to the first to fifth intermediate metal patterns M21 - M25 and third vias V3 .

Although not shown, additional metal layouts may be provided on the third metal layout. These may define additional metal layers stacked over the third metal layer. Accordingly, routing in which data paths are connected can be sequentially performed.

Meanwhile, the metal layout according to the present embodiment is shown to further include an additional metal layer (eg, a second metal layout) compared to the metal layout described with reference to FIG. 6 . However, in general, seven or more metal layers are stacked on a semiconductor substrate, and therefore, in the metal layout according to the present embodiment, routing can be performed through the metal layers (not shown) without adding a special metal layer.

Although the present embodiment has described a layout design method for any one logic cell, it may be applied to a plurality of logic cells (or a plurality of standard cells) at the same time, thereby reducing the overall height of the cells.

The metal layouts of the present embodiment described with reference to FIGS. 7, 8, and 10 and the metal layouts described with reference to FIGS. 5 and 6 above may be applied to different logic cells described with reference to FIG. 2 , respectively. Furthermore, they may be respectively applied within the different processor cores described in FIG. 1 .

11 to 13 are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention, and are cross-sectional views corresponding to lines II', II-II', and III-III' of FIG. 10 , respectively. Specifically, FIGS. 11 to 13 show an example of a semiconductor device implemented through the layout described above with reference to FIGS. 7 to 10 .

11 to 13 , the same reference numerals may be provided to components corresponding to the layout patterns according to the embodiments of the present invention. However, the configuration of the semiconductor device is implemented on the semiconductor substrate through the photolithography process described above, and may not be completely identical to the layout patterns described above. The semiconductor device may be, for example, a system-on-chip.

10 and 11 to 13 , second device isolation layers ST2 defining the PMOSFET region PR and the NMOSFET region NR may be provided on the substrate 100 . The second device isolation layers ST2 may be formed on the substrate 100 . For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate.

The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction Y parallel to the top surface of the substrate 100 with the second device isolation layers ST2 interposed therebetween. In an embodiment, each of the PMOSFET region PR and the NMOSFET region NR is illustrated as one region, but differently it may include a plurality of regions separated by the second device isolation layers ST2. can

A plurality of active patterns FN extending in a second direction X crossing the first direction Y may be provided on the PMOSFET region PR and the NMOSFET region NR. The active patterns FN may be arranged along the first direction Y. First device isolation layers ST1 extending in the second direction X may be disposed on both sides of each of the active patterns FN. In an embodiment, a plurality of fin portions may be provided on upper portions of the plurality of active patterns FN, respectively. For example, the fin portions may have a fin shape protruding between the first isolation layers ST1 .

Although three active patterns FN are shown in each of the PMOSFET region PR and the NMOSFET region NR, the present invention is not limited thereto. The second device isolation layers ST2 and the first device isolation layers ST1 may be a part of one insulating layer that is substantially connected. A thickness of the second device isolation layers ST2 may be greater than a thickness of the first device isolation layers ST1 . In this case, the first device isolation layers ST1 may be formed by a process separate from the second device isolation layers ST2 . In another embodiment, the first device isolation layers ST1 may be formed simultaneously with the second device isolation layers ST2 and may have substantially the same thickness. The first and second device isolation layers ST1 and ST2 may be formed on the substrate 100 . For example, the first and second device isolation layers ST1 and ST2 may include a silicon oxide layer.

Gate patterns GP that cross the active patterns FN and extend in the first direction Y may be provided on the active patterns FN. The gate patterns GP may be spaced apart from each other in the second direction X. Each of the gate patterns GP may extend in the first direction Y to cross the PMOSFET region PR, the second device isolation layers ST2 and the NMOSFET region NR.

A gate insulating pattern GI may be provided under each of the gate patterns GP, and gate spacers GS may be provided on both sides of each of the gate patterns GP. Furthermore, a capping pattern CP covering an upper surface of each of the gate patterns GP may be provided. However, as an example, the capping pattern CP may be removed on a portion of the gate pattern GP GP to which the gate contact CB is connected. First to seventh interlayer insulating layers 110 to 170 covering the gate patterns GP may be provided.

The gate patterns GP may include at least one of a doped semiconductor, a metal, and a conductive metal nitride. The gate insulating pattern GI may include a silicon oxide layer, a silicon oxynitride layer, or a high dielectric constant having a higher dielectric constant than that of the silicon oxide layer. Each of the capping pattern CP and the gate spacers GS may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Each of the first to seventh interlayer insulating layers 110 to 170 may include a silicon oxide layer or a silicon oxynitride layer.

Source/drain regions SD may be provided in the active patterns FN positioned on both sides of each of the gate patterns GP. As shown in FIG. 13 , the source/drain regions SD may be defined in the active patterns FN, but differently from the upper portion of the substrate 100 , that is, the first device isolation layers ( ST1) can be extended. The source/drain regions SD in the PMOSFET region PR may be p-type impurity regions, and the source/drain regions SD in the NMOSFET region NR may be n-type impurity regions. The fin portions positioned under each of the gate patterns GP and overlapping each of the gate patterns GP may be used as channel regions AF.

The source/drain regions SD may be epitaxial patterns formed by a selective epitaxial growth process. Accordingly, upper surfaces of the source/drain regions SD may be positioned at a higher level than upper surfaces of the fin portions. The source/drain regions SD may include a semiconductor element different from that of the substrate 100 . For example, the source/drain regions SD may include a semiconductor element having a lattice constant greater or less than a lattice constant of the semiconductor element of the substrate 100 . Since the source/drain regions SD include a semiconductor element different from that of the substrate 100 , compressive stress or tensile stress may be applied to the channel regions AF. For example, when the substrate 100 is a silicon substrate, the source/drain regions SD of the PMOSFET region PR may include silicon-germanium (embedded SiGe) or germanium. In this case, the source/drain regions SD may provide compressive stress to the channel regions AF. As another example, when the substrate 100 is a silicon substrate, the source/drain regions SD of the NMOSFET region NR may include silicon carbide (SiC). In this case, a tensile stress may be applied to the channel regions AF. Accordingly, mobility of carriers generated in the channel areas AF may be improved.

Source/drain contacts CA may be provided between the gate patterns GP. The source/drain contacts CA may be arranged in the second direction X along the active patterns FN. In addition, the source/drain contacts CA may be arranged in the first direction Y along one sidewall of the one or more gate patterns GP. For example, between the gate patterns GP, the source/drain contacts CA are respectively disposed on the PMOSFET region PR and the NMOSFET region NR in the first direction Y can be arranged (see FIG. 13 ). The source/drain contacts CA may be directly connected to and electrically connected to the source/drain regions SD. The source/drain contacts CA may be provided in the first interlayer insulating layer 110 .

According to an embodiment, in the PMOSFET region PR, the three source/drain regions SD spaced apart from each other in the first direction Y with the first device isolation layers ST1 interposed therebetween are , may be electrically connected to each other by one of the source/drain contacts CA. That is, at least one of the source/drain contacts CA may cover the active patterns FN in common and connect the source/drain regions SD spaced apart in the first direction Y to each other. There is (see Fig. 13).

The source/drain regions SD in the NMOSFET region NR may also be connected by the source/drain contacts CA in the same manner. That is, in the NMOSFET region NR, the source/drain regions SD spaced apart from each other in the first direction Y by the first device isolation layers ST1 are the source/drain contacts CA. ) can be interconnected by Meanwhile, one of the source/drain contacts CA may be connected to one of the source/drain regions SD.

Meanwhile, a gate contact CB may be provided on at least one of the gate patterns GP.

First vias V1 may be provided in the second interlayer insulating layer 120 on the first interlayer insulating layer 110 . A first metal layer may be provided in the third interlayer insulating layer 130 on the second interlayer insulating layer 120 . The first metal layer may include the wide metal patterns M11 ′ described above with reference to FIG. 7 and the second to fifth lower metal patterns M12 , M13 , M14 , and M15 .

For example, the second horizontal pattern M13b and the third wide sub-pattern M11'c may be electrically connected to the source/drain contacts CA through the first via V1, respectively. The first wide sub-pattern M11'a may be electrically connected to the gate contact CB through the first via V1.

Referring back to FIG. 13 , the first horizontal pattern M13a, the third wide sub-pattern M11'c, and the third wide sub-pattern M11'c and the second horizontal pattern M13b are Each may be spaced apart from each other by a third distance D3 in the first direction Y. This is because the third wide sub-pattern M11'c has wide lateral sidewalls WP1 facing the third sidewalls SP3 as described above.

The fourth and fifth lower metal patterns M14 and M15 may be provided outside the PMOSFET region PR and outside the NMOSFET region NR, respectively. Although not shown, the fourth lower metal pattern M14 is connected to the source/drain contact CA through the first via V1 to provide a drain voltage Vdd, that is, to the PMOSFET region PR. A power voltage can be applied. The fifth lower metal pattern M15 is connected to the source/drain contact CA through the first via V1 to apply a source voltage Vss, that is, a ground voltage, to the NMOSFET region NR. can do.

Second vias V2 may be provided in the fourth interlayer insulating layer 140 on the third interlayer insulating layer 130 . A second metal layer may be provided in the fifth interlayer insulating layer 150 on the fourth interlayer insulating layer 140 . The second metal layer may include the first to fifth intermediate metal patterns M21 to M25 described above with reference to FIG. 8 . The first to fifth intermediate metal patterns M21 - M25 are the wide metal patterns M11 ′ and the second and third lower metal patterns M12 and M13 through the second vias V2 . can be electrically connected to.

Third vias V3 may be provided in the sixth interlayer insulating layer 160 on the fifth interlayer insulating layer 150 . A third metal layer may be provided in the seventh interlayer insulating layer 170 on the sixth interlayer insulating layer 160 . The third metal layer may include the first to fourth upper metal patterns M31 to M34 described above with reference to FIG. 10 . The first to fourth upper metal patterns M31 - M34 may be electrically connected to the first to fifth intermediate metal patterns M21 - M25 through the third vias V3 .

The first to third metal layers may be formed using the method of designing and manufacturing a semiconductor device described above with reference to FIG. 3 . Specifically, the first to third metal layouts described above with reference to FIGS. 7 to 10 may be prepared by performing high-level design and layout design of the semiconductor integrated circuit. Then, optical proximity correction may be performed, and photomasks may be manufactured based on the changed metal layouts.

Forming the first metal layer may include forming a photoresist pattern corresponding to the first metal layout on the third interlayer insulating layer 130 . Specifically, first, a photoresist layer may be formed on the third interlayer insulating layer 130 . An exposure and development process may be performed on the photoresist layer using a photomask corresponding to the first metal layout. Accordingly, the photoresist pattern may be formed. The photoresist pattern may have openings defining metal wiring holes.

Subsequently, the metal wiring holes may be formed by etching the third interlayer insulating layer 130 using the photoresist pattern as an etch mask. Thereafter, the wide metal patterns M11 ′ and the second to fifth lower metal patterns M12 , M13 , M14 , and M15 may be formed by filling the metal wiring holes with a conductive material. The conductive material may include metal, for example, copper.

The second and third metal layers may be formed using a method similar to that of the first metal layer.

14 is a block diagram of an electronic system including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 14 , an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an input/output device 1120, I/O, a memory device 1130, a memory device, an interface 1140, and a bus ( 1150, bus). The controller 1110 , the input/output device 1120 , the memory device 1130 , and/or the interface 1140 may be coupled to each other through the bus 1150 . The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing functions similar thereto. The input/output device 1120 may include a keypad, a keyboard, and a display device. The memory device 1130 may store data and/or commands. The memory device 1130 may include a nonvolatile memory device (eg, a flash memory device, a phase change memory device, and/or a magnetic memory device). In addition, the memory device 1130 may further include a volatile memory device. In this case, the memory device 1130 may include a static random access memory (SRAM) including semiconductor devices according to embodiments of the present invention. The memory device 1130 may be omitted depending on the application of the electronic system 1100 or the electronic product to which the electronic system 1100 is applied. The interface 1140 may perform a function of transmitting data to or receiving data from a communication network. The interface 1140 may be wired or wireless. For example, the interface 1140 may include an antenna or a wired/wireless transceiver. The semiconductor device according to embodiments of the present invention may be provided as a part of the controller 1110 or the input/output device 1120 (I/O). Although not shown, the electronic system 1100 may further include a high-speed dynamic random access memory (DRAM) device and/or an SRAM device as a working memory device for improving the operation of the controller 1110 .

15 to 17 are diagrams illustrating examples of multimedia devices including semiconductor devices according to embodiments of the present invention. The electronic device 1 of FIG. 1 and/or the electronic system 1100 of FIG. 14 may be applied to the mobile phone or smart phone 2000 shown in FIG. 15 , and the tablet or smart tablet 3000 shown in FIG. 16 . may be applied to, and may also be applied to the notebook computer 4000 illustrated in FIG. 17 .

Claims (10)

a substrate including an active pattern thereon;
a gate electrode crossing the active pattern and extending in a first direction parallel to a top surface of the substrate; and
A first metal layer electrically connected to the active pattern and the gate electrode,
The first metal layer comprises:
a first metal wire extending in the first direction;
a second metal line spaced apart from the first metal line in the first direction and extending in a second direction crossing the first direction;
a third metal wire extending in the second direction; and
and a fourth metal wire spaced apart from the third metal wire in the first direction and extending in the first direction;
the first metal wiring includes a first sidewall in the second direction;
the second metal wiring includes a second sidewall in the second direction;
the first sidewall and the second sidewall are opposite to each other;
The length of the first sidewall is 2 to 3 times the minimum line width,
The third metal wiring includes a third sidewall in the second direction,
the fourth metal wiring includes a fourth sidewall in the second direction;
the third sidewall and the fourth sidewall are opposite to each other;
a length of the fourth sidewall is smaller than a length of the first sidewall;
a first distance between the first sidewall and the second sidewall is less than a second distance between the third sidewall and the fourth sidewall.
According to claim 1,
The minimum line width is a minimum width of the second metal line in the first direction.
According to claim 1,
the second metal wire and the third metal wire are spaced apart from each other by a third distance in the first direction;
The first distance is 1 to 1.2 times the third distance.
delete According to claim 1,
Further comprising a second metal layer on the first metal layer,
The second metal layer includes fifth metal wires extending in the first direction parallel to each other;
Any one of the fifth metal wires is electrically connected to the first metal wire to provide pin regions for routing.
6. The method of claim 5,
A plurality of the second metal wires are provided, and the second metal wires are spaced apart from each other in the first direction;
The other fifth metal wiring is a system-on-chip electrically connecting the second metal wirings spaced apart from each other.
6. The method of claim 5,
Further comprising a third metal layer on the second metal layer,
The third metal layer includes sixth metal wires extending in the second direction parallel to each other,
Any one of the sixth metal wires is connected to the pin regions of the fifth metal wires to be electrically connected to the first metal wire.
According to claim 1,
source/drain regions respectively formed on the active pattern on both sides of the gate electrode; and
Further comprising contacts respectively connected to the gate electrode and the source/drain regions,
The first and second metal wires are electrically connected to the contacts.
A layout design method comprising configuring a layout pattern for forming a system-on-chip including a plurality of standard cells,
Configuring the layout pattern includes configuring a first metal layout corresponding to the first metal layer,
The first metal layout is:
a first metal pattern extending in a first direction;
a second metal pattern spaced apart from the first metal pattern in the first direction and extending in a second direction crossing the first direction;
a third metal pattern extending in the first direction; and
and a fourth metal pattern spaced apart from the third metal pattern in the first direction and extending in the second direction;
The first and second metal patterns each include first and second sidewalls facing each other,
The distance between the first sidewall and the second sidewall is 1 to 1.2 times the minimum separation distance allowed by the design rule of the layout,
The third and fourth metal patterns each include third and fourth sidewalls facing each other,
a length of the third sidewall is smaller than a length of the first sidewall;
A distance between the first sidewall and the second sidewall is smaller than a distance between the third sidewall and the fourth sidewall.
10. The method of claim 9,
The length of the first sidewall is 2 to 3 times the minimum line width allowed by the layout design rule.

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