KR102261740B1 - High frequency device and manufacturing method thereof - Google Patents

Abstract

The high frequency device according to the present invention includes a semiconductor substrate 100 , a first trench and a second trench provided on the semiconductor substrate and spaced apart from each other, a third trench and a fourth trench between the first trench and the second trench , a source ohmic metal electrode 210 filling the first trench, a drain ohmic metal electrode 220 filling the second trench, and an asymmetric gate electrode 400 filling the third trench and the fourth trench. . The third trench has a first width in a first direction parallel to a top surface of the substrate, the fourth trench has a second width in the first direction, and the second width is smaller than the first width. .

Description

A high-frequency device and a manufacturing method therefor {HIGH FREQUENCY DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a high-frequency device and a method for manufacturing the same, and more particularly, to a method for manufacturing a high-frequency device with improved electrical characteristics.

High-Electron-Mobility Transistor (HEMT) forms a 2-dimensional electron gas (2DEG) due to the polarization characteristics of hetero semiconductor layers having different energy band gaps. . The 2DEG forms a channel between the source and drain electrodes and is controlled by the bias voltage of the gate electrode. HEMTs are being applied to high voltage and high frequency systems due to their high breakdown voltage and fast response speed.

One problem to be solved by the present invention is to provide a method of manufacturing a high-frequency device having improved electrical characteristics.

However, the problem to be solved by the present invention is not limited to the above disclosure.

A high-frequency device manufacturing method according to exemplary embodiments of the present invention for solving the above problems is an AlGaN/AlN transition layer, an undoped AlGaN buffer layer, a GaN channel layer, an undoped AlN layer, forming a semiconductor substrate by depositing an undoped AlxGa1-xN (x=20-28%) Schottky layer and an undoped GaN capping layer; forming an ohmic electrode filling the region removed through the trench etching after trench-etching one side of the upper portion of the semiconductor substrate in a lattice shape; forming a device isolation region on the other side of the upper portion of the semiconductor substrate through an ion implantation process; depositing an LPCVD SiN thin film and a PECVD SiN thin film sequentially on the semiconductor substrate; forming an asymmetric gate photoresist pattern having a gate pattern and a slit-shaped auxiliary gate pattern on the PECVD SiN thin film by electron beam lithography; forming a PECVD SiN pattern and an LPCVD SiN pattern by sequentially etching the PECVD SiN thin film and the LPCVD SiN thin film using the asymmetric gate photoresist pattern as an etch mask; after removing the asymmetric gate photoresist pattern, forming a T-type head photoresist pattern of an asymmetric gate electrode on the PECVD SiN pattern and the LPCVD SiN pattern through a photolithography method; Recessing the undoped GaN capping layer and the undoped AlxGa1-xN (x=20-28%) Schottky layer sequentially through a plasma etching method; depositing a gate metal on the PECVD SiN pattern and then removing the T-shaped head photoresist pattern of the asymmetric gate electrode to form an asymmetric T-shaped gate electrode; The method may include depositing an aluminum-based oxide film on the PECVD SiN pattern and the asymmetric T-shaped gate electrode through an atomic layer deposition (ALD) method.

In general, the resistance of the ohmic electrode may increase due to the undoped GaN capping layer and the undoped AlGaN Schottky layer. In addition, a high electric field is formed between the gate and the drain, so that the breakdown voltage of the device may be lowered. According to the concept of the present invention, after trench-etching the upper portion of the semiconductor substrate 100 in a lattice shape, an ohmic electrode filling the inside is formed, so that the resistance of the ohmic electrode can be lowered. In addition, since the magnitude of the electric field between the gate and the drain is reduced through the slit-shaped auxiliary gate electrode, the breakdown voltage may be increased.

However, the effects of the present invention may not be limited to the above disclosure.

1 to 8 are cross-sectional views for explaining a method of manufacturing a high-frequency device according to exemplary embodiments of the present invention.

The above objects, other objects, features and advantages of the present invention will be easily understood through the following preferred embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

In this specification, when a certain film (or layer) is referred to as being on another film (or layer) or substrate, it may be formed directly on the other film (or layer) or substrate or a third film between them. (or layer) may be interposed. In addition, in the drawings, the sizes and thicknesses of components are exaggerated for clarity. In addition, although the terms first, second, third, etc. are used to describe various directions, films (or layers), etc. in various embodiments of the present specification, these directions and films (or layers) It should not be limited by the same terms. These terms are only used to distinguish one direction or film (or layer) from another direction or film (or layer). Thus, a film referred to as a first film (or layer) in one embodiment may be referred to as a second film (or layer) in another embodiment. Each embodiment described and illustrated herein also includes a complementary embodiment thereof. Parts indicated with like reference numerals throughout the specification indicate like elements.

1 to 8 are cross-sectional views for explaining a method of manufacturing a high-frequency device according to exemplary embodiments of the present invention.

Referring to FIG. 1 , a semiconductor substrate 100 may be formed. Forming the semiconductor substrate 100 is performed on the substrate 110 in sequence by the transition layer 120 , the buffer layer 130 , the channel layer 140 , the undoped AlN layer 150 , the Schottky layer 160 , and the cap. Depositing the ping layer 170 may be included. The substrate 110 may be a high-resistance silicon (Si) substrate. The transition layer 120 may include an AlGaN/AlN layer. The buffer layer 130 may include an AlN layer. The channel layer 140 may include an undoped GaN layer. The Schottky layer 160 may include an undoped AlGaN layer. In exemplary embodiments, the Schottky layer 160 may include an Al _x Ga _{1 -x} N (x=20 to 28%) layer. The capping layer 170 may include an undoped GaN layer. An ohmic photoresist pattern 10 may be formed on the capping layer 170 . However, the pattern shape of the grid-shaped ohmic photoresist pattern 10 may not be limited to the grid shape.

Referring to FIG. 2 , a source ohmic region OR1 and a drain ohmic region OR2 may be formed. The source ohmic region OR1 and the drain ohmic region OR2 may be referred to as a first trench and a second trench. The first trench and the second trench may be formed in plurality. Forming the source and drain ohmic regions OR1 and OR2 may include a trench etching process using the lattice-shaped ohmic photoresist pattern 10 as an etch mask. The source ohmic region OR1 and the drain ohmic region OR1 may extend from the top surface of the capping layer 170 to the inside of the Schottky layer 150 .

Referring to FIG. 3 , a source ohmic metal electrode 210 and a drain ohmic metal electrode 220 may be formed. Forming the source ohmic metal electrode 210 and the drain ohmic metal electrode 220 is a process of removing the grid-shaped ohmic photoresist pattern 10, forming a photoresist pattern (not shown) for the ohmic electrode, The method may include sequentially depositing Ti, Al, Ni, and Au metals using an electron beam vacuum deposition method, and then lifting off the metals, and heat treating the lifted off metals. For example, the heat treatment of the lifted-off metals may include a rapid thermal annealing (RTA) method. In exemplary embodiments, the rapid heat treatment method may be performed at a temperature of about 900° C. for about 30 seconds (sec). The lower surfaces of the source ohmic metal electrode 210 and the drain ohmic metal electrode 220 may have a plurality of concavo-convex portions. After the ohmic metal electrode is manufactured, the device isolation region 180 may be formed using an ion implantation method. The device isolation region 180 may be formed on the semiconductor substrate 100 .

Referring to FIG. 4 , an LPCVD SiN thin film 310 and a PECVD SiN thin film 320 may be sequentially deposited on the source ohmic metal electrode 210 and the drain ohmic metal electrode 220 . The LPCVD SiN thin film 310 and the PECVD SiN thin film 320 may be referred to as a first SiN thin film 310 and a second SiN thin film 320 , respectively. The LPCVD SiN thin film 310 may be formed through a low pressure chemical vapor deposition (LPCVD) process. The PECVD SiN thin film 320 may be formed through plasma chemical vapor deposition (PECVD). The LPCVD SiN thin film 310 may have a higher density than the PECVD SiN thin film 320 . The LPCVD SiN thin film 310 and the PECVD SiN thin film 320 may protect the active region of the semiconductor substrate 100 , the source ohmic metal electrode 210 , and the drain ohmic metal electrode 220 . The active region may be a region disposed between the device isolation regions 180 .

Referring to FIG. 5 , an asymmetric gate insulating layer pattern 302 may be formed. Forming the asymmetric gate insulating film pattern 302 is a process of forming an asymmetric gate photoresist pattern 20 having a gate pattern GP and a slit-shaped auxiliary gate pattern SGP by an electron beam lithography method, and an asymmetric gate photoresist Dry etching of the PECVD SiN thin film (320 of FIG. 4 ) and the LPCVD SiN thin film (310 of FIG. 4 ) with _{CHF 4} /SF ₆ plasma sequentially may include dry etching using the pattern 20 as an etching mask. The PECVD SiN thin film ( 320 in FIG. 4 ) and the LPCVD SiN thin film ( 310 in FIG. 4 ) are sequentially dry-etched to form a PECVD SiN pattern 322 and an LPCVD SiN pattern 312 . That is, the asymmetric gate insulating layer pattern 302 may include a PECVD SiN pattern 322 and an LPCVD SiN pattern 312 . The asymmetric gate insulating layer pattern 302 may include a gate pattern GP and a slit-shaped auxiliary gate pattern SGP therein.

Referring to FIG. 6 , after the asymmetric gate photoresist pattern 20 is removed, a T-type head photoresist pattern 30 of the asymmetric gate electrode may be formed. In example embodiments, the T-shaped head photoresist pattern 30 of the asymmetric gate electrode may be formed through a photolithography method (eg, an image reversal method). _{Thereafter, the capping layer 170 and the Schottky layer 160 are sequentially formed through a BCl 3} /Cl ₂ ICP (inductively coupled plasma) plasma etching method using the T-type head photoresist pattern 30 of the asymmetric gate electrode as an etch mask. can be etched. By etching the capping layer 170 and the Schottky layer 160 , a third trench and a fourth trench may be formed. The third trench may correspond to the gate insulating pattern GP, and the fourth trench may correspond to the slit-shaped auxiliary pattern SGP. The third trench and the fourth trench may be interposed between the first trenches and the second trenches. The third trench may have a first width in a first direction parallel to the upper surface of the substrate, and the fourth trench may have a second width in the first direction. The second width of the fourth trench may be smaller than the first width of the third trench.
Referring to FIG. 7 , an asymmetric T-shaped gate electrode 300 may be formed. Forming the asymmetric T-shaped gate electrode 310 includes _{a plasma treatment process using O 2} plasma, a wet etching process using HCl as an etchant, a gate metal (not shown) deposition process, and an asymmetric gate on the semiconductor substrate 100 . It may include a process of removing the T-shaped head photoresist pattern (30 in FIG. 6 ) of the electrode. In exemplary embodiments, the gate metal may include Ni/Au or W/Ti/Au. In example embodiments, the gate metal deposition process may be performed through an electron beam vacuum deposition method or a sputtering vacuum deposition method. The asymmetric T-shaped gate electrode 400 may include a gate electrode head portion 410 , a gate electrode leg portion 420 , and a slit-shaped auxiliary gate electrode 430 . The gate electrode leg 420 may be disposed in the third trench, and the auxiliary gate electrode 430 may be disposed in the fourth trench. The gate head part 410 may extend from the gate electrode leg part 420 and the auxiliary gate electrode 430 , and may connect the gate electrode leg part 420 and the auxiliary gate electrode 430 .

delete

Referring to FIG. 8 , a passivation pattern 330 , a source wiring electrode SE, and a drain wiring electrode DE may be formed. In exemplary embodiments, forming the passivation pattern 330 may include _{PECVD of an aluminum-based oxide film (eg, Al 2} O ₃ film) (not shown) through an atomic layer deposition (ALD) method. After deposition on the SiN pattern 322 and the gate electrode head 410, a portion of the aluminum-based oxide film is removed to expose the top surfaces of the source ohmic metal electrode 210 and the drain ohmic metal electrode 220. may include

The source wiring electrode SE and the drain wiring electrode DE are formed on the passivation pattern 330 , the source ohmic metal electrode 210 , and the drain ohmic metal electrode 220 by electron beam vacuum deposition on the Ti/Au metal layer. After depositing (not shown), a step of lifting off the Ti/Au metal layer may be included.

In general, the resistance of the ohmic electrode may increase due to the undoped GaN capping layer and the undoped AlGaN Schottky layer. In addition, a high electric field is formed between the gate and the drain, so that the breakdown voltage of the device may be lowered. According to the concept of the present invention, after trench-etching the upper portion of the semiconductor substrate 100 in a lattice shape, an ohmic electrode filling the inside is formed, so that the resistance of the ohmic electrode can be lowered. In addition, since the magnitude of the electric field between the gate and the drain is reduced through the slit-shaped auxiliary gate electrode, the breakdown voltage may be increased.

So far, the present invention has been looked at with respect to preferred embodiments thereof. Those of ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in modified forms without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the scope equivalent thereto should be construed as being included in the present invention.

Claims (10)

AlGaN/AlN transition layer 120, undoped AlGaN buffer layer 130, GaN channel layer 140, undoped AlN layer 150, undoped AlxGa1-xN(x) sequentially on the silicon substrate 110 = 20 to 28%) forming a semiconductor substrate 100 by depositing a Schottky layer 160 and an undoped GaN capping layer 170;
forming a plurality of first trenches and a plurality of second trenches on the semiconductor substrate 100 ;
forming a source ohmic metal electrode 210 filling the first trenches and a drain ohmic metal electrode 220 filling the second trenches;
forming a third trench and a fourth trench interposed between the first trenches and the second trenches on the semiconductor substrate 100 ; and
forming an asymmetric gate electrode 400 filling the third trench and the fourth trench;
the third trench has a first width in a first direction parallel to the upper surface of the substrate;
the fourth trench has a second width in the first direction;
The second width is smaller than the first width,
The first trenches, the second trenches, the third trench and the fourth trench are in an undoped AlxGa1-xN (x=20-28%) Schottky layer 160 and an undoped GaN capping layer 170 . formed,
The bottom surfaces of each of the first trenches, the second trenches, the third trench and the fourth trench are provided above the top surface of the undoped AlN layer (150).
delete According to claim 1,
Forming the first trenches and the second trenches comprises:
forming an ohmic photoresist pattern on the undoped GaN capping layer; and
Using the ohmic photoresist pattern as an etch mask to etch from the top surface of the undoped GaN capping layer to the inside of the undoped AlxGa1-xN (x=20 to 28%) Schottky layer,
The photoresist pattern for ohmic is a method of manufacturing a high-frequency device having a lattice shape.
According to claim 1,
Forming the third trench and the fourth trench comprises:
Forming a first SiN thin film on the source ohmic metal electrode and the drain ohmic metal electrode sequentially through a low-pressure chemical vapor deposition (LPCVD) process, forming a second SiN thin film through a plasma chemical vapor deposition (PECVD) process that;
forming an asymmetric gate insulating film pattern by dry etching the first SiN thin film and the second SiN thin film, the asymmetric gate insulating film pattern including an opening gate pattern and a slit-shaped auxiliary gate pattern; and
and sequentially etching an undoped GaN capping layer and an undoped AlxGa1-xN (x=20 to 28%) Schottky layer through the gate pattern and the slit-shaped auxiliary gate pattern.
5. The method of claim 4,
The method of manufacturing a high-frequency device further comprising forming an aluminum oxide film on the insulating pattern and the asymmetric gate electrode through atomic layer deposition (ALD).

semiconductor substrate 100;
a first trench and a second trench provided on the semiconductor substrate and spaced apart from each other;
a third trench and a fourth trench between the first trench and the second trench;
a source ohmic metal electrode 210 filling the first trench;
a drain ohmic metal electrode 220 filling the second trench; and
an asymmetric gate electrode 400 filling the third trench and the fourth trench;
the third trench has a first width in a first direction parallel to the upper surface of the substrate;
the fourth trench has a second width in the first direction;
The second width is smaller than the first width,
The semiconductor substrate comprises:
silicon substrate;
a schottky layer on the silicon substrate; and
A capping layer on the Schottky layer,
The Schottky layer contains undoped AlxGa1-xN (x=20-28%),
The capping layer includes undoped GaN,
The first to fourth trenches are provided in the Schottky layer and the capping layer.
delete 7. The method of claim 6,
The first trench and the second trench are provided in plurality,
The upper portion of the substrate has a grid shape in regions in which the first trenches and the second trenches are located.
9. The method of claim 8,
A lower surface of the source ohmic metal electrode and a lower surface of the drain ohmic metal electrode have a plurality of concavo-convex portions.
7. The method of claim 6,
The asymmetric gate electrode comprises:
a gate electrode leg in the third trench;
an auxiliary gate electrode in the fourth trench; and
and a gate head extending from the gate electrode leg and the auxiliary gate electrode and connecting the gate electrode leg and the auxiliary gate electrode.

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