KR102242402B1 - Method of converting analog signal to digital information having a plurality of bits - Google Patents

Abstract

According to an embodiment of the present invention, outputting n-bit first digital information using a result of comparison between a plurality of reference currents and a first input current of the analog signal, and an analog value calculated from the first digital information Calculating a second input current by multiplying the difference between the first input currents by 2 ⁿ , and using the comparison result between the plurality of reference currents and the second input current, n bits that are lower bits of the first digital information A method of converting an analog signal into a plurality of bits of digital information comprising the step of outputting the second digital information of is provided.

Description

How to convert analog signals into multiple bits of digital information {METHOD OF CONVERTING ANALOG SIGNAL TO DIGITAL INFORMATION HAVING A PLURALITY OF BITS}

The present invention relates to a method of converting an analog signal into a plurality of bits of digital information.

Typically, processors require analog-to-digital conversion (ADC) capabilities. ADCs can be used to sample and digitize analog signals. Digitization of analog signals is required in a variety of applications.

Among the various techniques for performing ADC, the most commonly known techniques are a successive approximation resistor (SAR) type ADC circuit and a flash type ADC circuit. According to the ADC circuit of the continuous approximation method, a digital representation is generated by processing the input analog signal in successive steps. In each step, the analog signal input through the comparison process is continuously converted into a more accurate digital representation. So that you can get it. On the other hand, according to the ADC circuit of the flash method, a value of an input analog signal is compared with various reference levels, which is performed at once using a plurality of comparators. That is, in the flash-type ADC circuit, instead of multiple steps in the SAR-type ADC circuit, analog signals are compared simultaneously with multiple reference levels in one step. Accordingly, according to the ADC circuit of the flash method, in generating a digital representation of an analog signal, the latency is lower than that of the ADC circuit of the SAR method.

Accordingly, when the speed of other circuits included in the processor is slow, it is necessary to increase the overall speed of the processor by using a flash-type ADC circuit. On the other hand, when the speed of other circuits included in the processor is fast, power consumption and the area occupied by the ADC circuit can be reduced by using the SAR type ADC circuit. That is, the speed improvement and power consumption/area in the ADC circuit have a trade off relationship. Accordingly, there is a need for an ADC device that occupies a small area and can operate at high speed with low power and has high accuracy.

The technical problem to be solved by the present invention is to provide an ADC device and method capable of operating at high speed with low power and having high accuracy while occupying a small area.

The method of converting an analog signal into a plurality of bits of digital information according to an embodiment of the present invention outputs n-bit first digital information by using a comparison result between a plurality of reference currents and a first input current of the analog signal. The step of calculating a second input current by multiplying the difference between the analog value calculated from the first digital information and the first input current by 2 ⁿ , and a result of comparing the plurality of reference currents with the second input current And outputting n-bit second digital information, which is a lower bit of the first digital information.

In the step of outputting the first digital information, a ratio between the plurality of reference currents and the first input current is compared, and in the step of outputting the second digital information, a ratio between the plurality of reference currents and the second input current Can be compared.

A plurality of reference currents compared to the first input current to output the first digital information and a plurality of reference currents compared to the second input current to output the second digital information may be the same.

The outputting of the n-bit first digital information includes finding which section of the section where ^{the first input current is divided by 2 n of the full scale region (FSR) of the reference current, and the first input current} It may include the step of reading an n-bit value indicating a section to which is belong.

The n bits are 3 bits, and the analog value calculated from the first digital information is a value obtained by multiplying the digital value of the most significant bit of the first digital information by 1/2 FSR, and the lower bit of the most significant bit of the first digital information. It may be a sum of a digital value multiplied by 1/4 FSR and a digital value of the least significant bit of the first digital information multiplied by 1/8 FSR.

According to an embodiment of the present invention, it is possible to obtain an ADC device and method that occupies a small area and operates at high speed with low power and has high accuracy. The ADC device and method according to an embodiment of the present invention can be applied to an artificial intelligence processor that needs to process a lot of data at high speed.

1 is a diagram for explaining a method of converting an analog signal into digital information.
2 is an example of a circuit diagram applied to FIG. 1.
3 is a flowchart of a method for analog to digital conversion according to an embodiment of the present invention.
4 is a conceptual diagram of an ADC device for implementing a method for analog to digital conversion according to an embodiment of the present invention.
5 is a block diagram of a unit unit constituting an ADC device according to an embodiment of the present invention.
6 is an implementation example of the block diagram of FIG. 5.
7 is an implementation example of a comparison unit according to an embodiment of the present invention.
8 is an example of implementation of an XOR operator according to an embodiment of the present invention.
9 is an example of an input current of an XOR operator according to an embodiment of the present invention.
10 is an example of an implementation of a ROM circuit according to an embodiment of the present invention.
11 is an example of an input current of a ROM circuit according to an embodiment of the present invention.
12 is an example implementation of an operation unit according to an embodiment of the present invention.
13 is an example of an input current of an operation unit according to an embodiment of the present invention.

The present invention is intended to illustrate and describe specific embodiments in the drawings, as various changes may be made and various embodiments may be provided. However, this is not intended to limit the present invention to a specific embodiment, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms including ordinal numbers such as second and first may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the second element may be referred to as the first element, and similarly, the first element may be referred to as the second element. The term and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. It should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof does not preclude in advance.

Unless otherwise defined, all terms used herein including technical or scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in the present application. Does not.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings, but identical or corresponding components are denoted by the same reference numerals regardless of reference numerals, and redundant descriptions thereof will be omitted.

1 is a diagram illustrating a method of converting an analog signal into digital information, and FIG. 2 is an example of a circuit diagram applied to FIG. 1.

Referring to FIG. 1, in order to convert an analog signal into digital information, an input current of an analog signal is compared with a plurality of reference currents. If a current mode other than a voltage mode is used, the swing width of the voltage can be reduced based on the relationship between the current and the voltage of the MOSFET transistor, and it can operate at a higher speed and low power than in the voltage mode.

Hereinafter, a case where the full scale region (FSR) is 50 μA and the input current of the analog signal is 40 μA will be described as an example. Here, the full scale region (FSR) may be a DAC output when all bits are 1. An input current of 40 μA of the analog signal is compared with 1/2FSR (25 μA) of a first reference current, and since the input current is greater than the first reference current, the MSB (most significant bit) of digital information may be 1. Next, when the MSB of the digital information ^{represents 2 m} , in order to calculate the lower bit of the MSB, 2 ^m-1 , 15 μA, the difference between the input current 40 μA and the first reference current 25 μA, is 1/ Compared to 4FSR (12.5μA), 15μA is greater than 12.5μA, so 2 ^m-1 can be 1. ^{Next, in order to calculate 2 m-2} of digital information, 2.5 μA, the difference between 15 μA and 12.5 μA, which is the second reference current, is compared with 1/8 FSR (6.2 μA), which is the third reference current, and 2.5 μA is 6.2 μA. Is less than 2 ^m-2 can be 0.

When performing the ADC in this way, the reference current from MSB to the least significant bit (LSB) decreases by 1/2 per bit. If, in order to represent the analog signal as 12-bit digital information, the ratio between the reference current of the MSB and the reference current of the LSB is 2048:1, so the area occupied by the ADC circuit becomes considerably larger as illustrated in FIG. Power consumption also increases.

To solve this problem, when one bit of digital information is output and then the next bit of digital information is output using a current mirror, the area occupied by the ADC circuit can be reduced. However, since a mismatch in the channel width inevitably exists in the process, there is a problem that the accuracy of the ADC decreases whenever a current mirror is used.

For example, when 10 current mirrors are used in a process having an error of 1%, a total error of 10% is accumulated, and thus, the error problem due to a mismatch in the channel width increases as high-bit digital information increases.

In an embodiment of the present invention, it is possible to operate at high speed while reducing the area occupied by the ADC circuit and power consumption, and to minimize an error due to a mismatch in a channel width.

3 is a flowchart of a method for analog-to-digital conversion according to an embodiment of the present invention, FIG. 4 is a conceptual diagram of an ADC device for implementing the method for analog-to-digital conversion according to an embodiment of the present invention, and FIG. It is a block diagram of a unit unit constituting an ADC device according to an embodiment of the present invention, and FIG. 6 is an implementation example of the block diagram of FIG. 5.

Hereinafter, n bits are 3 bits, and the digital information converted from the input current of the analog signal is a total of 12 bits of digital information.

3 to 4, the first unit unit 410 of the ADC device 400 according to an embodiment of the present invention uses a result of comparing a plurality of reference currents and a first input current of an analog signal to obtain n bits. After outputting the first digital information of (S300), the second input current is calculated by multiplying the difference between the analog value calculated from the first digital information and the first input current by 2 ^{n (S310).} Then, the second unit unit 420 outputs the second digital information of n bits, which is the lower bit of the first digital information, using the comparison result between the plurality of reference currents and the second input current (S320), and The third input current is calculated by multiplying the difference between the analog value calculated from the information and the second input current by 2 ^n. If this process is repeated until the fourth digital information is extracted, a total of 12 bits of digital information can be obtained.

In this case, each unit unit may include a flash type ADC circuit, and a plurality of unit units may be connected in a cascade manner. As described above, when one unit unit generates n-bit digital information in a flash method and then the next unit unit generates n-bit digital information in a flash manner, the speed of the ADC can be increased.

More specifically, referring to FIGS. 5 to 6, the first unit unit 410 includes an n-bit generation unit 500 and an operation unit 510. Hereinafter, for convenience of description, the first unit 410 is described as an example, but the same structure may be applied to the second unit 420 to the fourth unit 440 as well.

The n-bit generator 500 outputs n-bit first digital information by using a comparison result between the plurality of reference currents and the first input current of the analog signal. To this end, the n-bit generator 500 ^{finds which section of the section in which the first input current of the analog signal is divided by 2 n} FSR of the reference current, and then reads the n-bit value representing the section. The first digital information of the bit can be output. Here, the first input current of the analog signal may be an input current of an analog signal input to the ADC device according to an embodiment of the present invention. Hereinafter, a specific method of outputting n-bit first digital information by the n-bit generator 500 will be described.

According to an embodiment of the present invention, in order for the n-bit generator 500 to output n-bit first digital information, the comparison unit 502 of the n-bit generator 500 includes a plurality of reference currents and a first input current. You can compare the ratio of the liver. 7 is an implementation example of a comparison unit according to an embodiment of the present invention. Referring to FIG. 7, when the reference current is Iref and the input current is Iin, instead of comparing Iref and Iin itself, the ratio of (1/x)Iref and (1/x)I may be compared. For example, when the reference current (1/2FSR) of the MSB is 25 μA and the input current of the analog signal is 30 μA, it is possible to compare 5 μA and 6 μA, which is a ratio of 25 μA and 30 μA. For example, a reference current made of 1, 2, 3, 4, 5, 6, and 7 times the LSB _{is not compared with 7 input currents W IN} , but the reference current is as shown. _{Input current W IN} , 1/2 W _IN , 1/3 W _IN , 1/2 W _IN , W _IN , made of 1, 1, 1, 2, 5, 1, and 7 times the LSB. It can be compared with 1/6 W _IN and W _{IN respectively.} According to this, not only the area occupied by the comparison unit is reduced, but also power consumed by the comparison unit can be greatly reduced. In this case, the n-bit generator 500 according to an embodiment of the present invention may be implemented in a flash method. That is, the input current of the analog signal can be compared with a plurality of comparators at the same time. For example, when the n-bit generator 500 wants to output 3-bit digital information, the actual value of the reference current (1/2FSR, Iref) of the MSB and the input current (Iin) of the analog signal is compared. In addition, Iref/x and Iin/x, which are ratios of the reference current (1/2FSR) of the MSB and the input current of the analog signal, may be compared. Accordingly, the FSR of the reference current ^{is divided into 2 3} , that is, 8 sections, and a ratio between the reference current in each section and the input current of the analog signal can be compared. As a result of the comparison, when the ratio of the input current is higher than the ratio of the reference current, it may be displayed as HIGH(H), and when the ratio of the input current is lower than the ratio of the reference current, it may be displayed as LOW(L).

Next, according to an embodiment of the present invention, the XOR operator 504 of the n-bit generator 500 uses the comparison result of the comparator 502 to make the first input current of the analog signal equal the FSR of the reference current by 2 ^{Among the sections divided by n} , you can find out which section belongs. 8 is an example of implementation of the XOR operator 504 according to an embodiment of the present invention, and FIG. 9 is an example of input current of the XOR operator according to an embodiment of the present invention. Here, as in FIG. 7, the n-bit generator 500 wants to output 3-bit digital information, the MSB reference current (1/2FSR) is 25 μA, and the analog signal input current is 30 μA. Explain. That is, the XOR operator 504 according to an embodiment of the present invention performs an XOR operation using the comparison result of FIG. 7, and an interval in which the comparison result changes from H to L may be displayed as 1 and the remaining intervals may be displayed as 0. . In addition, it may be determined that the section in which the XOR operation result is 1 is the section to which the first input current of the analog signal belongs.

Next, according to an embodiment of the present invention, the ROM circuit 506 of the n-bit generator 500 may read an n-bit value indicating a section to which the first input current of the analog signal belongs. 10 is an example of an implementation of a ROM circuit according to an embodiment of the present invention, and FIG. 11 is an example of an input current of a ROM circuit according to an embodiment of the present invention. Here, as in FIG. 7, the n-bit generator 500 wants to output 3-bit digital information, the MSB reference current (1/2FSR) is 25 μA, and the analog signal input current is 30 μA. Explain. When the FSR of the reference current ^{is divided into 2 3} , that is, 8 sections, as shown in FIG. 11, a 3-bit digital code may be allocated to each section. That is, digital codes of 000, 001, 010, 011, 100, 101, 110, 111 may be allocated to each section in the direction from 0 to the FSR. The section in which the operation result of the XOR operator 504 according to the embodiment of the present invention is 1 is a section to which a digital code of 100 is assigned. Accordingly, the ROM circuit 506 may read 100 digital codes, and the n-bit generator 500 may output 100 first digital information. Here, the n-bit generator ^{may include a 2 n} to n encoder.

Referring back to FIGS. 5 to 6, according to an exemplary embodiment of the present invention, the calculation unit 510 calculates the second input current by using the difference between the analog value calculated from the first digital information and the first input current. 12 is an example of implementation of an operation unit according to an embodiment of the present invention, and FIG. 13 is an example of an input current of an operation unit according to an embodiment of the present invention.

At this time, the n-bit first digital information is D ₁ D _2? In the _{case of D n} , the analog value calculated from the first digital information may be D ₁ *1/2FSR+D ₂ *1/4FSR+...+D _n *(1/2 ⁿ )FSR.

Meanwhile, the difference between the analog value calculated from the extracted first digital information and the first input current may be input to the next unit 420 and used to output the second digital information of n bits, which is the lower bit of the first digital information. have.

In this case, the reference level may be different as it is calculated for the lower bit of the first digital information. For example, when n bits are 3 bits, the reference level applied when calculating the second digital information should be 1/8 times the reference level applied when calculating the first digital information. However, when the reference level is changed as described above, the area occupied by the comparison unit of each unit unit may increase exponentially, and even if a current mirror is used, an error due to a mismatch in the channel width may increase significantly.

Accordingly, in an embodiment of the present invention, the reference level is fixed and the input current is increased by a ratio at which the reference level should be reduced.

That is, the reference current is fixed in the same manner as the FSR of the reference current in step S300 and the first unit unit 410, but the difference between the analog value calculated from the first digital information and the first input current (that is, the input current is 30 μA). Minus D ₁ *1/2FSR+D ₂ *1/4FSR+...+D _n *(1/2 ⁿ )FSR, i.e. (1*25+0*12.5+0*6.25+1*3.125)μA It is 2 or ³ times the value, and this can be used as the second input current input to the second unit unit 420. Accordingly, the area limitation is reduced even in the ADC that requires high-bit digital information, and the accuracy of conversion is reduced. It can be high.

Thereafter, the second unit unit 420 may compare the second input current and the reference current output from the first unit unit 410 to output n-bit second digital information, which is a lower bit of the first digital information. . In this case, the reference current may be the same as the reference current in the first unit unit 410, and the second digital information may be output in the same manner as the method performed by the first unit unit 410.

Thereafter, the second unit unit 420 may output second digital information and a third input current, and the third unit unit 430 may output third digital information using the third input current. In this way, a plurality of unit units can sequentially output n-bit digital information, and a final ADC result can be obtained.

As described above, according to an embodiment of the present invention, it is possible to obtain the effects of high speed, small area, low power consumption, and high resolution while using a flash-type ADC circuit.

As described above, according to the exemplary embodiment of the present invention, since the ratio of the reference current and the input current, not the actual value of the reference current and the input current, is used, static power consumption can be reduced by up to 30%.

Accordingly, it is possible to obtain an ADC device and method with a high speed and low power consumption by the flash method.

In addition, according to the exemplary embodiment of the present invention, since the reference current is fixed, the area occupied by the comparison unit can be significantly reduced.

Accordingly, the ADC device and method according to an embodiment of the present invention can be applied to an artificial intelligence field requiring high speed, low power, small area, and high resolution.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can do it.

Claims (5)

In the method of converting an analog signal into a plurality of bits of digital information,
Outputting n-bit first digital information using a comparison result between each of a plurality of reference currents and a first input current of the analog signal,
Calculating a second input current by multiplying the difference between the analog value calculated from the first digital information and the first input current by 2 ^{n, and}
Outputting n-bit second digital information, which is a lower bit of the first digital information, using a comparison result between each of the plurality of reference currents and the second input current
Including,
Each of the plurality of reference currents is a value corresponding to a section obtained by dividing a ^{full scale region (FSR) by 2 n,}
The FSR is a digital analog converter (DAC) output value when all bits are 1. The method of claim 1,
In the step of outputting the first digital information, a ratio between each of the plurality of reference currents and the first input current is compared,
In the step of outputting the second digital information, a method of comparing a ratio between each of the plurality of reference currents and the second input current. The method of claim 2,
Each of a plurality of reference currents compared with the first input current to output the first digital information and each of a plurality of reference currents compared with the second input current to output the second digital information are the same. The method of claim 2,
The step of outputting the n-bit first digital information,
Finding which section of the section in which ^{the first input current is divided by 2 n} of the full scale region (FSR), and
Reading an n-bit value indicating a section to which the first input current belongs
How to include. The method of claim 4,
The n bits are 3 bits,
The analog value calculated from the first digital information is a value obtained by multiplying the digital value of the most significant bit of the first digital information and 1/2 FSR, and the digital value of the lower bit of the most significant bit of the first digital information multiplied by 1/4 FSR. A method that is a sum of a value and a value obtained by multiplying the digital value of the least significant bit of the first digital information by 1/8 FSR.

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