KR102191712B1 - Liquid crystal display device - Google Patents

Abstract

The present invention discloses a liquid crystal display device. More specifically, the present invention relates to a liquid crystal display device having a structure in which the transmittance of a liquid crystal panel is improved while applying a frame rate control technology (FRC).
According to an embodiment of the present invention, by adding a white pixel for increasing the panel transmittance to the liquid crystal panel, and adding a driving circuit having a separate data processing means for processing data for the white pixel, the FRC applied liquid crystal display device There is an effect of improving the transmittance of the panel.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display having a structure in which the transmittance of a liquid crystal panel is improved while applying frame rate control (FRC) technology.

Flat panel display devices include LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), and OLED (Organic Light Emitting Diodes). Dual mass production technology, ease of driving means, high-definition implementation, Due to the realization of a large-area screen, in particular, a lot of research is being conducted on a liquid crystal display (LCD).

Among them, an active matrix liquid crystal display device using a thin film transistor (TFT) as a switching element is suitable for displaying a dynamic image.

An active matrix type liquid crystal display device includes a liquid crystal panel formed by crossing a plurality of gate wirings and data wirings in a matrix form and having a plurality of pixels controlled by a switching element at the intersection point, and a driving circuit for controlling the same Consists of Such a liquid crystal display device converts a digital video signal applied from an external system into an analog data voltage using a reference voltage and supplies it to the data line, and at the same time, sequentially supplies a gate driving signal to the gate line to conduct the switching element, thereby generating a data signal. It is a structure to fill the liquid crystal cell.

The liquid crystal display of this configuration receives RGB data provided from the outside and modulates it into data for display on the liquid crystal panel. In particular, the input RGB data is typically 8 bits, and at this time, an integrated circuit (IC) The driving circuits, which are custom-made in the form of, use a 6-bit processing IC to reduce manufacturing cost. At this time, one of the methods proposed by the necessity of the required data processing technology is a frame rate control technology (FRC).

The FRC may reduce the number of bits of RGB data input to the data driving IC while compensating for a loss in the number of gray levels that can be represented. FRC has been applied to many liquid crystal display devices because it can reduce the cost of liquid crystal display devices and reduce image quality degradation.

1 and 2 are diagrams for explaining the principle of an FRC applied to a conventional liquid crystal display device.

FIG. 1 shows an example of temporally dispersing a compensation value in order to finely adjust the luminance with a few grayscales less than one grayscale. Referring to FIG. 1, if a compensation value '1' is written to a pixel for only one frame period (4 ^th Frame) among four frame periods (1 ^st Frame ~ 4 ^th Frame), the viewer The gradation of the pixel is recognized as 1/4 gradation (25%) (a).

Further, of the four frame periods, the two frame periods when writing the compensation values '1' to the (3 ^rd Frame, Frame 4 ^th) to the pixel, the viewer is the gray level of the pixel gray levels for 4 1/2 frame period (50 %) (b). In addition, if the compensation value '1' is written to a pixel in three frame periods among the four frame periods, the viewer recognizes the gray level of the pixel as 3/4 gray level (75%) for the four frame periods (c).

In addition, FIG. 4 shows an example in which compensation values are spatially distributed in order to finely adjust the luminance with a few grayscales less than one grayscale. Referring to FIG. 4, in order to finely adjust the luminance to a small number of gradations less than one gradation, a plurality of pixels P1 to P4 are divided into blocks, and compensation is compensated by adjusting the number of pixels to which a compensation value is written in the block The teeth are spatially distributed. As an example, when 2×2 pixels are used as one block, if a compensation value '1' is written to one pixel P1 among the pixels P1 to P4 in the block, the viewer The gradation of is recognized as 1/4 gradation (25%) (a).

In addition, if a compensation value '1' is written to two pixels P1 and P3 among the pixels in the block, the viewer recognizes the gray level of the block as 1/2 gray level (50%) (b). In addition, as shown in FIG. 4C, if a compensation value '1' is written to three of the pixels in the block, the viewer recognizes the gray level of the block as 3/4 gray level (75%) (c).

In general, FRC applied to a liquid crystal display device is implemented in parallel with the temporal dispersion method of FIG. 1 and the spatial dispersion method of FIG. 2.

3 is a diagram showing an example of a frame rate pattern in a liquid crystal display to which a conventional FRC driving method is applied, and pixels to which a compensation value is written are indicated by hatching.

Referring to FIG. 3, if 12 X 4 pixels are used as one block and a compensation value '1' is written to 6 pixels during 4 frame periods (1 ^st Frame ~ 4 ^th Frame), the viewer Korean gradations are recognized as 1/8 gradations (12.5%). Here, if the positions of the pixels to which the compensation value is written are the same, the luminance of the pixels may be different from those of the surrounding pixels, so that the viewer may perceive them as noise. Accordingly, the positions of the pixels to which the compensation value '1' is written are changed every frame period.

However, according to the above-described FRC driving method, there is an advantage in that the number of bits that can be processed by the driving circuit IC can be increased and gradation can be finely adjusted, but there is a limitation in that the luminance of the entire pixel cannot be increased.

The present invention has been conceived to solve the above problems, and an object of the present invention is to provide a liquid crystal display device capable of improving panel transmittance while applying FRC.

In order to achieve the above object, a liquid crystal display device according to a preferred embodiment of the present invention includes a liquid crystal panel in which a plurality of gate wirings and data wirings are cross-formed, and red, green, blue, and white pixels are provided at intersection points; A gate driver outputting a gate driving signal to the gate wiring; A data driver outputting a data signal to the data line; A data conversion unit that adds W data for the white pixel in response to RGB data applied from the outside; An FRC processor configured to receive RGBW data from the data conversion unit and generate a frame rate pattern; And a timing controller that controls the gate driver and the data driver, and applies the frame rate pattern to the data signal.

The red, green, blue, and white pixels are arranged alternately in order in a vertical direction.

The data conversion unit may include a luminance calculating unit receiving the RGB data and calculating a luminance value of each color pixel; And an output signal generator configured to generate and output the RGBW data including W data based on the luminance value calculated according to the set value.

The FRC processing unit may include a data extracting unit for extracting upper and lower bits of the RGBW data; And a frame rate control unit for outputting a frame rate control signal corresponding to the extracted lower bit.

The frame rate pattern is characterized in that a compensation value is added to an upper bit with respect to at least one of pixels in each frame in units of 16×4 pixel blocks or 32×4 pixel blocks.

The frame rate pattern is characterized in that the number of R, G, B and W pixels to which a compensation value is added in one frame is the same.

According to an embodiment of the present invention, by adding a white pixel for increasing the panel transmittance to a liquid crystal panel, and having a data modulator and an FRC processing unit having separate data processing means for processing data for the white pixel, FRC There is an effect of improving the panel transmittance of the applied liquid crystal display device.

1 and 2 are diagrams for explaining the principle of an FRC applied to a conventional liquid crystal display device.
3 is a diagram illustrating an example of a frame rate pattern in a liquid crystal display device to which a conventional FRC driving method is applied.
4 is a diagram showing the structure of a liquid crystal display according to an embodiment of the present invention.
5 is a diagram illustrating a data conversion unit and an FRC processing unit provided in a liquid crystal display according to an exemplary embodiment of the present invention.
6 and 7 are diagrams illustrating frame rate patterns applied to a liquid crystal display according to an exemplary embodiment of the present invention.

In this specification, terms including ordinal numbers such as first and second are used to refer to various elements, and the corresponding elements are not limited by these terms. The terms described in the following description are used for the purpose of distinguishing one component from another component.

In particular, when a component is described as being'connected' or'connected' to another component, it may be directly connected or connected to the other component, but other components may exist in the middle. On the other hand, when a component is described as being'directly connected' or'directly connected' to another component, there is no other component in the middle.

The terms used in the present application are only used to describe specific embodiments and are not intended to limit the present invention, and expressions in the singular include plural expressions unless the context clearly indicates otherwise.

Hereinafter, a liquid crystal display device according to a preferred embodiment of the present invention will be described with reference to the drawings.

4 is a diagram showing the structure of a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 4, in the liquid crystal display device of the present invention, a plurality of gate lines GL and data lines DL are cross-formed, and red, green, blue, and white pixels R, G, B, and W are formed at intersection points. ), a gate driver 110 for outputting a gate driving signal Vg to the gate line GL, and a data driver for outputting a data signal Vdata to the data line GL ( 120), a data conversion unit 140 that adds W data for the white pixel W in response to RGB data (RGB) applied from the outside, and a frame rate by receiving RGBW data from the data conversion unit 140 An FRC processing unit 150 generating a pattern, and a timing controller 160 controlling the gate driving unit 110 and the data driving unit 120, and applying the frame rate pattern to the data signal Vdata.

In the liquid crystal panel 100, two transparent substrates are bonded to each other by a predetermined distance, and a liquid crystal layer is interposed therebetween. Of the two substrates, a plurality of gate lines GL and a plurality of data lines DL are cross-formed on a transparent substrate on an array substrate, and a plurality of pixels PX are defined at the intersection points. Each pixel consists of three primary color pixels (R, G, B) and white pixels (W), and at least one thin film transistor and liquid crystal capacitor are provided in each of the pixels (R, G, B, W). To display the image.

Therefore, based on a liquid crystal display device having a full HD (Full High-definition) resolution, as a conventional liquid crystal panel includes pixels of three primary colors, the total number of pixels is 1920 × 1080 × 3, but according to the present invention In the liquid crystal panel, 1440 × 1080 × 4 pixels are provided.

Unlike the conventional stripe structure, the RGBW pixels R, G, B, and W are alternately arranged in each color in the vertical direction. The stripe structure is a structure in which red, green, and blue pixels are each arranged in the same color in the vertical direction (see Fig. 3), and such a stripe structure is applied to the liquid crystal panel 100 of the present invention to which a white pixel (W) is added. In this case, a problem of lowering the readability of an image may occur due to a white pixel W having a relatively higher luminance than other pixels R, G, and B.

In order to minimize this problem, in the liquid crystal display according to the exemplary embodiment of the present invention, the pixels R, G, B, and W are arranged so that the same color is not continuous with each other in the vertical direction.

In addition, red, green, and blue color filters for implementing the three primary colors are formed on the color filter substrate, and the color filter is not formed in a portion corresponding to the white pixel W, but remains as an empty space. That is, the white pixel (W) does not have a color filter, so its transmittance is relatively higher than that of the three primary color pixels (RGB), and only white light is emitted. There is an effect of increasing the brightness.

The data for the white pixel W is generated by RGB data, and its luminance is determined according to the intention of the setter.

As an example, when the transmittance of the three primary RGB pixels (R, G, B) is 1, the liquid crystal display has a luminance of 350 nit. And, when a white pixel (W) is added, the area ratio of the R, G, B pixels (R, G, B) is 75%, the area ratio of the white pixel (W) is 25%, and the transmittance of the color filter is 0.33. If is, the transmittance of the RGBW pixels (R, G, B, W) is 0.75 + (0.25 / 0.33) ≒ 1.5. That is, the transmittance of the RGBW pixels (R, G, B, W) of the present invention is increased by about 1.5 times compared to that of the conventional RGB pixels (R, G, B) alone.

Meanwhile, in the thin film transistor provided in each pixel PX, the gate electrode is connected to the gate line GL, and the source electrode is connected to the data line DL. Further, the drain electrode is connected to the pixel electrode opposite to the common electrode. As a material forming the active layer of such a thin film transistor, a-si silicon and poly silicon may be used, but the device performance is also required as high performance according to the trend of increasing the size and high definition of liquid crystal displays Accordingly, oxide silicon having improved mobility characteristics may be used.

The gate driver 110 is formed of a plurality of thin film transistors formed in a non-display area excluding a pixel area of the liquid crystal panel 100 or is formed of a separate driving IC. Although not shown, in a large-area and high-resolution liquid crystal display device, a plurality of gate driving units 110 may be provided on both sides of the liquid crystal panel 100 as shown.

In particular, the gate driver 110 responds to the gate control signal GCS input from the timing control unit 160 through the gate wiring GL formed on the liquid crystal panel 100 for 1 to 2 horizontal periods (1 to 2H). A high-level gate driving signal Vg is output. Accordingly, the thin film transistors in the pixels (R, G, B, W) are conducted in units of one horizontal line, and in synchronization with this, the data signal (Vdata) is output through the data line (DL) to be charged into the liquid crystal capacitor, The light transmittance is changed to display an image.

The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (Gate Output Enable, GOE).

The data driver 120 converts the aligned digital image data aRGB into an analog data signal Vdata according to a reference voltage in response to the data control signal DCS input from the timing controller 160. In addition, the data driver 120 latches the converted data signal Vdata in units of one horizontal line and outputs it to the liquid crystal panel 100 at the same time through all the data lines DL every 1 to 2 horizontal periods (1 to 2H). do.

The data control signal DCS includes a source start pulse (SSP), a source shift clock (SSC), and a source output enable signal (Source Output Enable, SOE).

In this case, the aligned image data aRGBW is frame rate-processed data, and is an RGBW video signal to which a compensation value is added by the FRC driving method. This FRC driving method is implemented by the FRC processing unit 150 and the timing controller 160 to be described later.

The data conversion unit 140 converts RGB data (RGB) for R, G, B pixels input from an external system into R, G, B, W data (RGBW) according to a set value, and sends the data to the FRC processing unit 150. Print. That is, RGB data (RGB) related to an image provided by an external system does not include W data related to luminance, and the data conversion unit 140 is based on R, G, B data (R, G, B). RGBW data (RGBW) is generated.

The FRC processing unit 150 receives the RGB data (RGB) output from the data conversion unit 140, extracts the high-order and low-order bits therefrom, and then transfers the image data (HRGBW) for the high-order bit to the timing control unit 160. It supplies, analyzes the lower bits, generates a frame rate control signal (FCS) for driving the frame rate, and inputs it to the timing controller 160. Accordingly, the timing controller 160 adds and aligns a compensation value according to the frame rate pattern with respect to the received image of the higher bit, and outputs the aligned RGBW data aRGBW to the data driver 120.

The data conversion unit 140 and the FRC processing unit 150 described above may be mounted in the timing controller 160 and implemented as one IC.

The timing controller 160 receives the timing signal Ts from an external system and generates control signals GCS and DCS of the gate driver 110 and the data driver 120 in response thereto.

In addition, the timing control unit 160 receives image data (HRGBW) composed of high-order bits and a frame rate control signal (FCS) from the FRC processing unit 150, adds a compensation value to the image data (HRGBW), and the data driver 120 RGBW data (aRGBW) is output to the data driver 120 by arranging in a form that can be processed by

The image data HRGBW is composed of upper 6 bits, and the frame rate control signal FCS is an addition of a compensation value defined by 2 bits. Therefore, as the frame rate is adjusted for 4 frames, the R, G, B, W pixels (R, G, B, W) display a gray level corresponding to the original 8-bit data in which 6 bits and 2 bits of the frame rate are combined. do.

Accordingly, in the image data HRGBW, a gray scale value of each pixel is 6 bits, and up to 64 gray scales can be implemented, but 256 gray scales of 8 bits can be implemented according to frame rate control.

That is, the upper bit (6 bits) of W data is converted into analog W data, and the converted analog W data is added with a correction value of '1' for four frames according to the frame rate control signal (FCS). Bits) and lower bits (2 bits) are combined to realize the luminance corresponding to the original (8 bits) of W data.

According to this structure, the liquid crystal display device of the present invention further includes a white pixel (W) that increases the luminance of an image in addition to the basic three primary colors, and increases the number of bits that the driver circuit IC can process by applying a frame rate control method. This has the effect of finely adjusting the gradation.

Hereinafter, a driving circuit of a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

5 is a diagram illustrating a data conversion unit and an FRC processing unit provided in a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the liquid crystal display device of the present invention corresponds to the data conversion unit 140 and RGBW data to add W data (W) for the white pixel in response to RGB data (RGB) applied from the outside. Thus, an FRC processing unit 150 is provided to apply the frame rate pattern to the timing control unit.

The data conversion unit 140 receives the RGB data (RGB) and calculates a luminance value of a pixel for each color, and RGBW data including W data based on a luminance value calculated according to a set value. It consists of an output signal generator 145 that generates and outputs (RGBWo).

In detail, the luminance determination unit 141 receives 8-bit RGB data (RGB) applied from an external system, determines a luminance value (lum) for each color, and provides it to the output signal generation unit 150. .

The output signal generator 145 generates W data (Wo) according to a set value (set) and a luminance value (lum), adjusts the luminance of R, G, B data (RGB), and adjusts the RGB data (Ro) for output. ,Go,Bo). Here, the luminance adjustment of the R, G, B data (RGB) is to minimize the occurrence of color change due to the addition of white pixels. The generated output RGBW data (RGBWo) is provided to the FRC processing unit 150.

The FRC processing unit 150 includes a data extracting unit 152 that extracts upper and lower bits of the RGBW data RGBWo, and a frame rate control unit that outputs a frame rate control signal (FCS) in response to the extracted lower bits. 156).

The data extraction unit 152 divides and inputs 8-bit output data (RGBWo) to which data for white pixels is added, into R data (Ro), G data (Go), B data (Bo), and W data (Wo). Receive and arrange them sequentially. As an example, the data for output (RGBWo) may be input in units of one frame, and the data extraction unit 152 includes R data (Ro), G data (Go), B data (Bo), and W data (Wo). After arranging one frame at a time, subsequent data processing is performed.

After data arrangement, the data extracting unit 152 extracts upper and lower bits for each of R data Ro, G data Go, B data Bo, and W data Wo. As an example, if each data is 8-bit data and one data is '10001001', 6-bit data '100010' is extracted as the upper bit, and 2-bit data '01' is extracted as the lower bit. The data extraction unit 152 performs this data processing process on all R, G, B, and W data included in one frame.

Among the bits extracted by the data extracting unit 152, the upper bit (HRGB) is output to the timing control unit, and the lower bit (LR, LG, LB, LW) is output to the frame rate control unit 156, which will be described later.

The frame rate control unit 156 receives the lower bits (LR, LG, LB, LW) for each data extracted by the data extracting unit 152 and generates a control signal FCS for controlling the frame rate. This frame rate control signal is to add the compensation value by the lower bit for 4 frames for R, G, B, W data, and the timing control unit (not shown) applies the compensation value when aligning the upper bit. .

In particular, the pixels to which the compensation value included in each frame is added must be set so that the total number of pixels is the same for each corresponding color, otherwise, a problem of image quality degradation such as flicker is minimized.

6 and 7 are diagrams illustrating frame rate patterns applied to a liquid crystal display according to an exemplary embodiment of the present invention.

6 illustrates a frame rate pattern of an FRC type liquid crystal display device having a 16×4 pixel block, and hatched pixels indicate pixels to which compensation values are written. The drawing shows an example of a structure in which RGBW pixels (R, G, B, W) are not arranged with the same color in the vertical direction, but in which different colors are arranged, but the pixel arrangement is limited to the structure shown in the drawing. It is not.

Referring to FIG. 6, in the FRC driving method of the present invention, a pattern for a 16×4 pixel block is repeated within one frame, and four frame periods (1) for each pixel (R, G, B, W). by writing the compensation value "1" to the eight pixels for 4 ^th ~ ^st frame frame) in addition to the original gray level for four-frame period is a 1/8 gradation display (12.5%). In addition, the occurrence of noise is prevented by shifting the positions of pixels to which a compensation value is written in each frame period (1 ^st Frame ~ 4 ^th Frame).

If you want to display by adding 1/2 gray scale, you can write a compensation value '1' to 32 pixels per pixel block.

Here, the sum of the pixels R, G, B, and W to which the compensation value is added must be controlled to be the same in one frame. That is, in FIG. 6, two of the R pixel (R), G pixel (G), B pixel (B), and W pixel (W) are collectively written with the compensation value '1'.

In addition, FIG. 7 is an illustration of a frame rate pattern of an FRC type liquid crystal display device having a 32×4 pixel block. As in the example above, four frame periods for each of the pixels R, G, B, and W ( 1 ^st Frame ~ 4 ^th Frame), by writing the compensation value '1' to 16 pixels, 1/8 gray scale (12.5%) is displayed in addition to the original gray scale during the 4 frame period. In addition, positions of pixels to which the compensation value is applied are changed for each frame period (1 ^st Frame to 4 ^th Frame).

Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can do it.

100: liquid crystal panel 110: gate driver
120: data driving unit 140: data conversion unit
150: FRC processing unit 160: timing control unit
RGB: RGB data RGBWo: RGBW data for output
HRGBW: upper bit RGBW data FCS: frame rate control signal
GCS: Gate control signal DCS: Data control signal
aRGBW: Arranged RGBW data

Claims (6)

A liquid crystal panel in which a plurality of gate wires and data wires are cross-formed, and red, green, blue, and white pixels are provided at intersection points;
A gate driver outputting a gate driving signal to the gate wiring;
A data driver outputting a data signal to the data line;
A data conversion unit that adds W data for the white pixel in response to RGB data applied from the outside;
An FRC processor configured to receive RGBW data from the data conversion unit and generate a frame rate pattern; And
A timing controller that controls the gate driver and the data driver and applies the frame rate pattern to the data signal
Including,
In the frame rate pattern, positions of pixels to which a compensation value is applied are changed for each frame period. The method of claim 1,
The red, green, blue and white pixels,
A liquid crystal display device, characterized in that the order is alternately arranged in a vertical direction. The method of claim 1,
The data conversion unit,
A luminance calculator configured to receive the RGB data and calculate a luminance value of each color pixel; And
An output signal generator for generating and outputting the RGBW data including W data based on the luminance value calculated according to the set value
A liquid crystal display device comprising a. The method of claim 1,
The FRC processing unit,
A data extraction unit extracting upper and lower bits of the RGBW data; And
Frame rate control unit that outputs a frame rate control signal in response to the extracted lower bit
A liquid crystal display device comprising a. The method of claim 1,
The frame rate pattern,
A liquid crystal display device, comprising: adding a compensation value to an upper bit for at least one of pixels in each frame in units of 16×4 pixel blocks or 32×4 pixel blocks. The method of claim 1,
The frame rate pattern,
A liquid crystal display device, characterized in that the number of R, G, B and W pixels to which a compensation value is added in one frame is the same.

Images