KR102057106B1 - Receiving circuit for multi-level signal - Google Patents

Abstract

The present invention relates to a reception circuit for receiving a signal transmitted by multiple levels like signal transmission in a mobile industry process interface (MIPI) C-PHY and, more specifically, to a reception circuit for receiving a multilevel signal which adaptively delays a transition point of next predetermined data from a plurality of pieces of current data received through data receivers to attenuate pattern jitter. According to the present invention, the reception circuit for receiving a multilevel signal comprises a data-dependent elastic buffer (DDEB) (120) restoring first to third data from first to third data input signals when there are the first to third data swung between a plurality of levels, and adaptively delaying a predetermined transition point of first to third restoration signals when the first to third restoration signals are generated from the first to third data to attenuate patter jitter generated by a third level.

Description

RECEIVING CIRCUIT FOR MULTI-LEVEL SIGNAL}

The present invention relates to a technique for receiving a signal transmitted at multiple levels, such as a signal transmission of a Mobile Industry Process Interface (MIPI) C-PHY, and in particular, the transition point of the next specific data in the current data received through the data receivers. The present invention relates to a receiving circuit for a multi-level signal that adaptively delays attenuating pattern jitter.

In general, MIPI C-PHY transmits data using three lines, and there is no separate clock signal line, and recovers the clock signal using three-level signal transmission. In MIPI C-PHY specification, one or more transition points are encoded to generate a clock signal from the received data.

1 is a block diagram of a receiving circuit having a clock signal reconstructor for a multi-level signal according to the prior art and, as shown therein, a termination 10, a first used in MIPI C-PHY specification. -3 data receivers 20A-20C, clock signal recoverer 30, and three D-type flip-flops (DF / F).

The first data receiver 20A receives the data input signals A and B swinging at three levels and outputs the first data D_A at the CMOS level. The second data receiver 20B receives the data input signals B and C swinging at three levels and outputs the second data D_B at the CMOS level. The third data receiver 20C receives the data input signals C and A swinging at three levels and outputs the third data D_C at the CMOS level.

The clock signal restorer 30 receives the first-third data D_A, D_B, and D_C output from the first-three data receivers 20A-20C and detects a change in the previous clock signal whenever a change thereof is detected. The clock signal CLK is generated and output in the manner of inverting. Accordingly, the clock signal restorer 30 may output a clock signal CLK having a constant frequency while at least one of the first data D_A, D_B, and D_C is changed.

The three D-type flip-flops D-F / F sample the 1-3 data D_A, D_B, and D_C by using the clock signal CLK output from the clock signal recoverer 30.

In the clock signal restorer 30 performing such an operation, it is necessary to reduce the pattern jitter of the first to third data D_A, D_B, and D_C to generate a clock signal having better time jitter characteristics. There is. In addition, even when there is a separate clock signal for sampling data, it is necessary to secure enough time margin when sampling data using the clock signal so that time jitter of the 1-3 recovery data is reduced.

However, the reception circuit including the clock signal recoverer for the multi-level signal according to the prior art does not have a function of reducing the pattern jitter of the receiver, which makes it difficult to secure the stability of the reception circuit.

An object of the present invention is to adapt a specific transition point when recovering data from data input signals through a data dependent elastic buffer (DDEB) in a receiving circuit for signal transmission using a multi-level signal. To attenuate pattern jitter The purpose is to allow the clock to be recovered at the same transition point of the recovered data to eliminate pattern jitter.

According to an aspect of the present invention, there is provided a receiving circuit including a clock signal recoverer for a multi-level signal, the first data receiver receiving first and second data input signals and outputting first data; A second data receiver receiving the second data input signal and a third data input signal and outputting second data; A third data receiver receiving the third and first data input signals and outputting third data; Under the control of the first delay control signal, the first restore signal is delayed and output based on the current time point, and a specific transition point is output. A first programmable delay to adaptively delay to attenuate pattern jitter; A second programmable delayer under the control of the second delay control signal to delay and output the second restore signal based on the current time point, but adaptively delay a specific transition point to reduce pattern jitter; A third programmable delayer configured to delay and output a third restore signal based on a current time point under control of the third delay control signal, and to adaptively delay a specific transition point to reduce pattern jitter; And a controller configured to generate the 1-3 delay control signal based on the 1-3 restore signal and output the 1-3 delay control signal to the 1-3 programmable enable delay unit.

According to the present invention, a pattern jitter generated by three levels is applied in such a manner as to adaptively move a specific transition point of a reconstruction signal through a delay process when reconstructing a data signal in a receiving circuit for signal transmission using a multi-level signal. By attenuation, there is an effect of improving the stability of the receiving circuit.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a reception circuit for a multi-level signal according to the prior art and a reception circuit having a clock signal restorer as input to received data.
2 is a block diagram of a receiving circuit diagram for a multilevel signal according to the present invention;
Figure 3a is a waveform diagram showing that the pattern jitter is output as it is when the data-dependent elastic buffer is not used.
Figure 3b is a waveform diagram showing that the pattern jitter attenuated output using a data-dependent elastic buffer.
4 is a detailed circuit diagram of the control unit.
5A is an explanatory diagram of occurrence of time jitter appearing in an eye diagram when receiving a three-level signal when no data dependent elastic buffer is used.
5B is an explanatory diagram of occurrence of time jitter in an eye diagram when receiving a three-level signal when using a data dependent elastic buffer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a data dependent elastic buffer (DDEB) 120, which is a receiving circuit for receiving signals transmitted in multiple levels according to the present invention. As shown in FIG. The first data receiver includes the first to third data receivers 110A, 110B, and 110C, the first to third programmable delayers 120A, 120B, and 120C, and the controller 130.

The 1-3 data input signals A, B, and C input to the 1-3 data receivers 110A, 110B, and 110C swing at a plurality of levels (for example, 3 levels). For example, the three levels of swing may be a high level of 375 mV, a middle level of 250 mV, and a low level of 125 mV. The 1-3 data input signals A, B, and C may not have the same level according to the MIPI C-PHY interface.

The receiving circuit 100 restores the first to third data D_A, D_B, and D_C from the received first to third data input signals A, B, and C, and then stores the first to third data D_A, D_B. From the D_C, the 1-3 recovery signals AB, BC, and CA are generated. At this time, the pattern jitter caused by the three levels is attenuated by delaying the specific transition point of the 1-3 recovery signals AB, BC, and CA. Here, the first to third restore signals AB, BC, and CA are complementary metal oxide semiconductor (CMOS) single-ended signals.

The first data receiver 110A receives the first and second data input signals A and B swinging at three levels and outputs the first data D_A at the CMOS level.

The second data receiver 110B receives the second and third data input signals B and C swinging at three levels and outputs second data D_B at the CMOS level.

The third data receiver 110C receives the third and first data input signals C and A swinging at three levels and outputs the third data D_C at the CMOS level.

The first programmable delay unit 120A is controlled by the first delay control signal EB_AB to advance the first restoration signal AB to a minimum delay (without additional delay processing) or a minimum delay based on the current time. The output is delayed additionally by the set time (eg 1 step).

Under the control of the second delay control signal EB_BC, the second programmable enable delayer 120B delays and outputs the second restoration signal BC by one step to the minimum delay or the minimum delay based on the current time.

Under the control of the third delay control signal EB_CA, the third programmable delay unit 120C delays and outputs the third restoration signal CA by one step to the minimum delay or the minimum delay based on the current time point.

3A and 3B illustrate timing diagrams of five cases in which one of six states of the first to third data input signals A, B, and C may change from one state to the next. Here, the left side represents the current state and the right side represents the next state based on the reference center. In this case, the 1-3 data input signals A, B, and C may have six states by the MIPI C-PHY interface, and the next data may be changed to another state.

3A illustrates that the first to third restoration signals AB, BC, and CA are output without being delayed because the receiver circuit 100 is not used. Jitter is output as it is. Specifically, the data transition in five cases (Case1-Case5) generates three data transition intersection points (a reference time point, a left point relative to the reference time point, and a right point relative to the reference time point), and the pattern jitter is output as it is.

On the contrary, in FIG. 3B, the first restoration signal AB is output without being delayed and the second to third restoration signal BC are outputted according to a combination of logic values of the current data state restored using the reception circuit 100. Delays the transition point of the next restored data by delaying and outputting CA). This shows that the pattern jitter of the 1-3 data input signal is reduced to half level (Jitter / 2).

In FIG. 3B, in all five cases (Case1-Case5), the logic value of the current state of the first to third restoration signals AB, BC, and CA is 1,0,0. This means that the input of the first data receiver 110A swings with a large width and the inputs of the remaining 2-3 data receivers 110B, 110C swing with a small width. When the current logic value is 1,0,0, the first programmable delay 120A does not perform additional delay processing, while the second and third programmable delays 120B and 120C perform second and third delays. The second and third differential signals BC and CA are delayed under the control of the control signals EB_BC and EB_CA. As such, the reception circuit 100 adaptively controls the data transition point by controlling the first, second, and third programmable delays 120A, 120B, and 120C, respectively, according to the combination of the logic values of the restored current data state. . As a result, the occurrence of data transition intersections in three cases by the conventional method is changed to the occurrence of data transition intersections in two cases, thereby improving pattern jitter.

Specifically, the data transition in five cases (Case1-Case5) generates two data transition crossing points (the reference point and the right point relative to the reference point), thereby reducing the pattern jitter by half.

The controller 130 may control the first to third delay control signals EB_AB, EB_BC, based on the first to third restore signals AB, BC, and CA supplied from the first to third programmable enable delayers 120A to 120C. EB_CA) is generated as shown in the table below based on the control as shown in FIG. 3B and supplied to the first to third programmable delayers 120A to 120C. In the table below, "current state" indicates that the controller 130 is MIPI. The six states by the C-PHY interface are items representing logic values supplied from the first to third restoration signals AB, BC, and CA. The first state output from the control unit 123 is " state " It is a logic value of three delay control signals (EB_AB, EB_BC, EB_CA).

For example, when the logic value of the first to third restoration signals AB, BC, and CA is 1,0,0, the controller 130 is supplied from the controller 130 to the first to third programmable delayers 12A to 120C. The logic values of the 1-3 delay control signals EB_AB, EB_BC, and EB_CA are 0,1,1. Accordingly, the first programmable delayer 120A outputs the first differential signal AB without delaying as shown in FIG. 3B. The second and third programmable delayers 120B and 120C delay and output the second and third restore signals BC and CA as shown in FIG. 3B.

4 is a diagram of a logic circuit for the controller 130 to output the first to third delay control signals EB_AB, EB_BC, and EB_CA as shown in the table based on the first to third restoration signals AB, BC, and CA. An example is shown.

Referring to FIG. 4, the controller 130 NAND a second restore bar signal / BC, a third restore signal CA, a second restore signal BC, and a third restore bar signal / CA. First delay control signal output unit 130A for outputting the first delay control signal EB_AB, the third restoration signal CA, the first restoration bar signal / AB, and the third restoration bar signal A second delay control signal output unit 130B for performing NAND calculation of CA) and the first restore signal AB, and output a second delay control signal EB_BC, and a first restore signal AB and a second restore bar signal. (/ BC), the third delay control signal output unit 130C outputs a third delay control signal EB_CA by performing a NAND operation on the first restore bar signal / AB and the second restore signal BC. .

The first delay control signal output unit 130A includes a first NAND gate ND1, a second restored signal BC, and a third NAND operation for performing a NAND operation on the second restored bar signal / BC and the third restored signal CA. NAND operation of the second NAND gate ND2 for NAND operation of the recovery bar signal / CA, and output signals of the first and second NAND gates ND1 and ND2 to output the first delay control signal EB_AB accordingly. And a third NAND gate ND3.

The second delay control signal output unit 130B includes a fourth NAND gate ND4 and a third restored bar signal / CA for NAND operation of the third restored signal CA and the first restored bar signal / AB. NAND operation of the fifth NAND gate ND5 for NAND operation of the first restoration signal AB, and output signals of the fourth and fifth NAND gates ND4 and ND5 to output the second delay control signal EB_BC. And a sixth NAND gate ND6.

The third delay control signal output unit 130C includes a seventh NAND gate ND7 and a first restoring bar signal / AB for NAND operation of the first restoring signal AB and the second restoring bar signal / BC. NAND operation of the eighth NAND gate ND8 and the seventh and eighth NAND gates ND7 and ND8 for NAND operation of the second restoration signal BC to output the third delay control signal EB_CA. And a ninth NAND gate ND9.

5A is an explanatory diagram of occurrence of time jitter appearing in an eye diagram when receiving a signal that may have a three-level when not using a data dependent elastic buffer. Referring to FIG. 5A, when receiving a signal having three levels, time jitter is generated due to occurrence of three data transition crossing times.

5B is an explanatory diagram of occurrence of time jitter in an eye diagram when receiving a signal that may have a three-level when using a data dependent elastic buffer. Referring to FIG. 5B, when receiving a signal having a 3-level, first, second, and third programmable delayers respectively controlled according to the first to third delay control signals of the controller 130 of the receiving circuit 100. The adaptive delay of (120A, 120B, 120C) generates two data transition intersections. This leads to a reduction in time jitter.

Although the preferred embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto, and may be implemented in various embodiments based on the basic concept of the present invention defined in the following claims. Such embodiments are also within the scope of the present invention.

100: receiving circuit 110A-110C: 1-3 data receiver
120A-120C: 1-3 Programmable Delay 130: Control Unit
130A-130C: 1-3 delay control signal output unit

Claims (7)

A first data receiver receiving first and second data input signals and outputting first data;
A second data receiver receiving the second data input signal and a third data input signal and outputting second data;
A third data receiver receiving the third and first data input signals and outputting third data;
A first programmable delayer for delaying and outputting a first restoration signal based on a current delay time under control of the first delay control signal, and adaptively delaying a specific transition point to reduce pattern jitter;
A second programmable delayer under the control of the second delay control signal to delay and output the second restore signal based on the current time point, but adaptively delay a specific transition point to reduce pattern jitter;
Under the control of the third delay control signal, the third restoration signal is delayed and output based on the current time point, and the specific transition point is adaptively output. A third programmable delay to delay the pattern jitter; And
And a controller configured to generate the 1-3 delay control signal based on the 1-3 restore signal and to output the 1-3 delayable control signal to the 1-3 programmable enable delayer.
The control unit
A first delay control signal output unit for performing a NAND operation on a second restore bar signal, the third restore signal, the second restore signal, and a third restore bar signal and output a result of the operation as the first delay control signal;
A second delay control signal output unit for performing a NAND operation on the third restore signal, the first restore bar signal, the third restore bar signal, and the first restore signal, and output the operation result as the second delay control signal; And
And a third delay control signal output unit configured to NAND the first restore signal, the second restore bar signal, the first restore bar signal, and the second restore signal, and output a result of the operation as the third delay control signal. Receiving circuit for a multi-level signal, characterized in that.
2. The receiving circuit of claim 1, wherein the first to third data input signals swing at a plurality of levels.
The method of claim 1, wherein the 1-3 restore signal is
Complementary Metal Oxide Semiconductor (CMOS) A receiving circuit for a multi-level signal, characterized in that the single-ended signal.
delete The method of claim 1, wherein the first delay control signal output unit
A first NAND gate NAND-operating the second restore bar signal and the third restore signal;
A second NAND gate NAND operation of the second restore signal and the third restore bar signal; And
And a third NAND gate performing NAND operation on the output signals of the first and second NAND gates, and outputting the result of the operation as the first delay control signal.
The method of claim 1, wherein the second delay control signal output unit
A fourth NAND gate NAND operation of the third restored signal and the first restored bar signal;
A fifth NAND gate NAND operation of the third restored bar signal and the first restored signal; And
And a sixth NAND gate NAND of the output signals of the fourth and fifth NAND gates, and outputting the result of the operation as the second delay control signal.
The method of claim 1, wherein the third delay control signal output unit
A seventh NAND gate NAND operation of the first restored signal and the second restored bar signal;
An eighth NAND gate NAND operation of the first restored bar signal and the second restored signal; And
And a ninth NAND gate NAND of an output signal of the seventh and eighth NAND gates, and outputting a result of the operation as the third delay control signal.

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