KR102039410B1 - Liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof capable of preventing a malfunction due to a delay of a gate signal.
A driving method of a liquid crystal display device according to an exemplary embodiment of the present invention includes: a first gate high voltage for turning on TFTs formed in a plurality of pixels of a liquid crystal panel; A second gate high voltage having a voltage value lower than the first gate high voltage; A first gate low voltage for maintaining a turn-off state of the TFT; And a second gate low voltage for turning off the TFT to a voltage value lower than the first gate low voltage, wherein the TFT is formed in the plurality of pixels of the liquid crystal panel using the gate signal. It characterized in that the switching.

Description

Liquid crystal display device and driving method thereof {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of preventing malfunction due to a delay of a gate signal.

The gate driving circuit of the liquid crystal display device includes a shift register for sequentially supplying gate pulses to a plurality of gate lines. The shift register includes a plurality of stages including a plurality of transistors, and the stages are cascaded to sequentially output the gate pulses.

Recently, a gate in panel (GIP) gate driving circuit has been applied in which a transistor constituting the shift register of the gate driving circuit is embedded in a substrate of a display panel in the form of a thin film transistor (TFT).

1 is a view for explaining a method of driving a liquid crystal display device according to the prior art.

1, a gate signal (gate signal) generated in the gate drive circuit through the plurality of stages are sequentially output to the first gate signal (1 ^st gate signal) the last gate signal (last gate signal) from the liquid crystal The first gate line formed in the panel is sequentially supplied to the last gate line. When the gate signal is supplied to the pixels, the TFTs of the respective pixels are turned on.

In recent years, as the liquid crystal panel has been enlarged and narrowed in bezels, there has been a problem in that malfunctions due to signal delays occur due to an increase in resistance and parasitic capacitance of lines formed in the liquid crystal panel.

As the liquid crystal panel becomes larger, the length of the gate line becomes longer, and a delay occurs in the gate signal, and the gate signal delay prevents the TFT of the pixel from being driven at the correct timing, thereby causing a malfunction.

In particular, the deviation of the pixel voltage charged to the pixel to which the gate signal is initially applied (? Vp1) and the deviation of the pixel voltage charged to the pixel to which the gate signal is applied to the last (? Vp2) are increased to uniformly drive the entire pixel. You won't be able to.

In addition, the narrow bezel reduces the width of the lines outside the active area, and integrating many lines and configurations in a narrow space increases the rising time and the falling time of the gate signal. As a result, the charging ratio of the pixel voltage is reduced. When the charging ratio of the pixel voltage is decreased, the image may not be displayed according to the source data, and flicker may increase, thereby reducing display quality.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is an object of the present invention to provide a liquid crystal display device and a driving method thereof capable of preventing malfunction of a pixel due to a delay of a gate signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a liquid crystal display device and a driving thereof capable of reducing a rising time and a falling time of a gate signal and increasing a charging ratio of a pixel voltage. It is a technical task to provide a method.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and includes a deviation (ΔVp1) of a pixel voltage charged to a pixel to which a gate signal is initially applied and a difference (ΔVp2) of a pixel voltage to a pixel to which a gate signal is last applied. It is a technical object of the present invention to provide a liquid crystal display device and a method of driving the same, which can reduce the number of steps.

In addition to the technical task of the present invention mentioned above, other features and advantages of the present invention will be described below, or from such description and description will be clearly understood by those skilled in the art.

A driving method of a liquid crystal display device according to an embodiment of the present invention for achieving the above object is a first gate high voltage for turning on the TFT formed in a plurality of pixels of the liquid crystal panel; A second gate high voltage having a voltage value lower than the first gate high voltage; A first gate low voltage for maintaining a turn-off state of the TFT; And a second gate low voltage for turning off the TFT to a voltage value lower than the first gate low voltage, and generating a gate signal and using the gate signal to form a plurality of pixels of the liquid crystal panel. It characterized in that for switching.

The liquid crystal display device and the driving method thereof according to the embodiment of the present invention can prevent the malfunction of the pixel due to the delay of the gate signal.

The liquid crystal display device and the driving method thereof according to an embodiment of the present invention can reduce the rising time and the falling time of the gate signal, and increase the charging ratio of the pixel voltage.

According to an exemplary embodiment of the present invention, a liquid crystal display device and a driving method thereof according to the present invention provide a deviation (ΔVp1) of a pixel voltage charged to a pixel to which a gate signal is initially applied and a difference of a pixel voltage charged to a pixel to which a gate signal is last applied. It is possible to improve display quality by reducing (ΔVp2).

In addition, other features and advantages of the present invention may be newly understood through the embodiments of the present invention.

1 is a view for explaining a method of driving a liquid crystal display device according to the prior art.
2 is a schematic view of a liquid crystal display device according to an exemplary embodiment of the present invention.
3 is a diagram illustrating a pixel structure of a liquid crystal display device according to an exemplary embodiment of the present invention.
FIG. 4 is a diagram illustrating a method of driving a liquid crystal display device according to an exemplary embodiment of the present invention, and illustrates waveforms of a gay signal applied to a gate line and a data voltage applied to a pixel.
5 is a view showing an effect of improving the deviation of the pixel voltage.
6 is a schematic view of a liquid crystal display device according to another embodiment of the present invention.
7 is a view illustrating a drive IC of a liquid crystal display according to another exemplary embodiment of the present invention.
8 illustrates a pixel structure of a liquid crystal display according to another exemplary embodiment of the present invention.

In the present specification, in adding reference numerals to components of each drawing, the same components are described with the same reference numerals as much as possible even if they are shown on different drawings.

On the other hand, the meaning of the terms described herein will be understood as follows. A singular expression should be understood to include a plurality of expressions unless the context clearly indicates otherwise, and the terms “first”, “second”, and the like are intended to distinguish one component from another. These terms do not limit the scope of rights.

It is to be understood that the term "comprises" or "having" does not preclude the existence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

The term "at least one" should be understood to include all combinations which can be presented from one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also of the first item, the second item, and the third item. A combination of all items that can be presented from two or more.

In describing an embodiment of the present invention, when a structure (electrode, line, wiring, layer, contact) is described as being formed 'on or on' and 'under or under' another structure, such a description may be used. It should be construed to include not only when they are in contact with each other but also when a third structure is interposed between these structures.

Liquid crystal display devices have been developed in various ways, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, and fringe field switching (FFS) mode.

Among these, the IPS mode and the FFS mode are horizontal electric fields in which the pixel electrode Pixel ITO and the common electrode Vcom are disposed on the lower substrate to adjust the arrangement of the liquid crystal layer by the electric field between the pixel electrode and the common electrode. . The liquid crystal display device according to the embodiment of the present invention can be applied regardless of the mode.

Hereinafter, a liquid crystal display and a driving method thereof according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

The present invention mainly improves the waveform of the gay signal of the liquid crystal display device, and prevents malfunction due to signal delay. Therefore, detailed descriptions and drawings of the backlight unit for supplying light to the apparatus and the liquid crystal panel which are not related to the main contents of the present invention may be omitted.

2 is a diagram schematically illustrating a liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating a pixel structure of a liquid crystal display apparatus according to an exemplary embodiment of the present invention.

2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 100 in which a plurality of pixels are arranged in a matrix form, a driving circuit unit for driving the liquid crystal panel 100, and a liquid crystal panel. It includes a backlight unit (not shown) for supplying light to the liquid crystal panel 100 and a bezel and an outer case (not shown) formed to surround the driving circuit.

The driving circuit unit includes a gate driving circuit 200, a data driving circuit, a control unit for driving the gate driving circuit 200 and the data driving circuit, and a printed circuit board 300 having a power supply unit generating driving power. .

2 illustrates an example in which the gate driving circuit 200 is formed on the lower substrate of the liquid crystal panel 100 in a GIP manner and formed on the left and right sides of the liquid crystal panel 100. However, the present invention is not limited thereto, and the gate driving circuit may be configured as a separate drive IC and disposed on the side of the liquid crystal panel 100.

The data driving circuit includes a plurality of data drive ICs 500, and the plurality of data drive ICs 500 may be formed by a chip on glass (COG) or chip on flexible printed circuit (chip on film) method. The liquid crystal panel 100 may be disposed above or below the liquid crystal panel 100.

Referring to FIG. 3, a plurality of gate lines GL formed in a horizontal direction and a plurality of data lines DL formed in a vertical direction are formed on a lower substrate (TFT array substrate) of the liquid crystal panel 100. The plurality of gate lines and the plurality of data lines intersect to define a plurality of pixels. In FIG. 3, the upper substrate on which the color filter is formed is not shown.

3 illustrates an example in which the pixels are formed short in the horizontal direction and long in the vertical direction, and have red, green, and blue pixels alternately arranged in the horizontal direction.

A TFT is formed as a common electrode to which the common voltage Vcom is applied, a pixel electrode to which the data voltage Vdata is applied, a storage capacitor Cst, and a switching element to each of the plurality of pixels.

The active layer of the TFT may be formed of amorphous silicon (a-Si), low temperature polysilicon (LTPS), or indium gallium zinc oxide (IGZO) material.

The liquid crystal display device having the above-described configuration changes an arrangement state of liquid crystals for each pixel according to an electric field formed between the pixel electrode and the common electrode, and displays an image by adjusting the transmittance of light supplied from the backlight unit through the arrangement of liquid crystals. do.

Here, the larger the resistance of the line and the parasitic capacitor, the lower the accuracy of the applied signal, because a delay occurs in the signal due to the load of the line.

When the liquid crystal panel 100 is enlarged, the gate line GL may also be lengthened, and the load of the gate line may increase to delay the gate signal beyond the normal operating level. In particular, as the delay of the gate signal supplied to the liquid crystal panel 100 in the gate driving circuit 200 increases, the charging ratio of the pixel voltage decreases, and the adjacent pixels may mix data to generate flicker.

In the present invention, as shown in FIG. 4, the gate signal is improved to prevent the delay of the gate signal due to the enlargement of the liquid crystal panel.

FIG. 4 is a diagram illustrating a method of driving a liquid crystal display device according to an exemplary embodiment of the present invention, and illustrates waveforms of a gay signal applied to a gate line and a data voltage applied to a pixel.

Referring to FIG. 4, a gate signal supplied to a pixel of a liquid crystal display according to an exemplary embodiment of the present invention is a first gate high voltage VGH1 and a second gate high voltage VGH2 at a level lower than the first gate high voltage. ) Is generated as a scan pulse having a first gate low voltage VGL1 of negative polarity and a second gate low voltage VGL2 lower than the first gate low voltage.

Specifically, the gate signal rises from the first gate low voltage VGL1 of negative polarity, eg, -5V, to the first gate high voltage VGH1, eg, + 35V, in the first period. In this case, the first gate high voltage VGH1 is generated with a conventional gate high voltage VGH, for example, a voltage value Vgh1> Vgh_ref higher than + 28V, thereby reducing the rising time of the gate signal and turning the TFT of the pixel. Allow the on-speed to occur.

Next, in the second period, the first gate high voltage VGH1 is maintained. In this case, the time for which the first gate high voltage VGH1 is maintained may be shorter than the gate high voltage VGH of the prior art, but the first gate high voltage VGH1 of the present invention is higher than the gate high voltage VGH of the prior art. This high voltage value can reduce the charging time of the pixel voltage.

Specifically, the first gate high voltage VGH1 allows a large amount of current to flow compared to the prior art so that the pixel voltage can be sufficiently charged even in a short time. That is, the charging ratio of the pixels can be increased. On the other hand, if the charging ratio is set to the same level as the prior art, the charging time for charging the pixel voltage can be reduced.

Subsequently, in the third period, gate pulse modulation (GPM) is applied to reduce the voltage of the gate signal to a second gate high voltage VGH2, for example, + 20V, which is lower than the first gate high voltage. Lower.

In this case, the second gate high voltage VGH2 has a voltage value higher than the turn-on voltage value of the gate of the TFT formed in the pixel of the liquid crystal panel. Lowering the first gate high voltage VGH1 to the second gate high voltage VGH2 by applying the gate pulse modulation GPM is to reduce the polling time of the gate signal.

In detail, the charging time of the pixel voltage is shortened by the first gate high voltage VGH1 to secure an extra charging time. The gate pulse modulation GPM is applied during the spare charging time thus secured to lower the peak voltage of the gate signal from the first gate high voltage VGH1 to an arbitrary second gate high voltage VGH2 (Vgh2 < Vgh1).

Here, the polling time of the gate signal may be reduced by lowering the voltage value of the gate signal to the second gate high voltage VGH2 having a low voltage value before turning the TFT off of the pixel.

Here, as the second gate high voltage VGH2 is lower, the polling time of the gate signal can be reduced, but at least the second gate high voltage VGH2 is higher than the maximum value V_data of the data voltage applied to the data line. Have (Vgh2> V_data).

If the second gate high voltage VGH2 has the same or lower voltage value Vgh2 ≤ V_data as the pixel voltage V_data, a reverse current flows in the pixel, thereby insufficient charging of the pixel voltage. In order to prevent this, the second gate high voltage VGH2 has a voltage value Vgh2> V_data higher than the maximum value V_data of the data voltage applied to the data line.

Subsequently, in the fourth period, the voltage of the gate signal is lowered to the second gate low voltage VGL2, for example, −15 V, having a voltage value lower than the first gate low voltage VGL1, which is an initial voltage value.

That is, the voltage of the gate signal is lowered to the second gate low voltage VGL2 of −15 V having a voltage value lower than −5 V as an example of the gate low voltage VGL of the prior art by applying under driving driving. .

Here, in order to turn off the TFT of the pixel, the voltage value of the gate signal is lowered from the high voltage to the low voltage, and the voltage of the gate signal is reduced to the second gate low voltage VGL2 of -15V lower than that of the prior art for a short time. Lowering can reduce the polling time of the gate signal.

That is, the polling characteristic of the gate can be improved by turning off the TFT of the pixel with the second gate low voltage VGL2 having a lower voltage value than the conventional one.

Thereafter, the second gate low voltage VGL2 is raised to the first gate low voltage VGL1 again so that the TFT of the pixel is kept in an off state.

5 is a diagram illustrating an effect of improving the deviation of the pixel voltage.

Referring to Tables 1 and 5, the prior art and the present invention showed the same level as the charging ratio of the pixel voltage is 97.0 ~ 99.4%. In the case where the charging ratio of the pixel voltage is the same, the conventional technique requires the polling time of the gate signal to be 4.64us, while the present invention has an effect of reducing the polling time of the gate signal by 54% compared to the prior art as 2.53us.

As described above, unlike the prior art, two gate high voltages VGH1 and VGH2 and two gate low voltages VGL1 and VGL2 are used, that is, a total of four voltages VGL1, VGL2, VGH1 and VGH2. By generating the gate signal, it is possible to prevent the charge ratio of the pixel voltage due to the delay of the gate signal generated due to the enlargement of the liquid crystal panel. In addition, due to the delay of the gate signal, data of adjacent pixels may be overlapped to prevent generation of flicker.

On the other hand, as shown in Figure 2, by applying the gate driving circuit 200 of the GIP method can reduce the manufacturing cost, volume and weight of the liquid crystal display device, but the bezel (left and right of the liquid crystal panel) bezel) has the disadvantage of increasing size.

Since the lines of the GIP cannot be deleted, it is difficult to implement an ideal narrow bezel, and furthermore, it is impossible to implement a borderless panel. In order to improve this problem, as shown in Figs. 6 and 7, the arrangement position of the drive IC in the liquid crystal display device is changed, and as shown in Fig. 8, the pixel structure is changed.

FIG. 6 is a view schematically illustrating a liquid crystal display device according to another embodiment of the present invention, and FIG. 7 is a view illustrating a drive IC of the liquid crystal display device according to another embodiment of the present invention.

6 and 7, a liquid crystal display device according to another exemplary embodiment of the present invention may include a liquid crystal panel 100 in which a plurality of pixels are arranged in a matrix, and a plurality of liquid crystal panels 100 for driving the liquid crystal panel 100. Drive IC 400, a control unit for supplying control signals for driving the plurality of drive ICs 400, and a printed circuit board 300 (PCB) and a liquid crystal panel 100 mounted with a power supply unit for generating driving power. It includes a backlight unit (not shown) for supplying light, a bezel and an outer case (not shown) formed to surround the liquid crystal panel 100 and the driving circuit.

7 illustrates one drive IC 400 among a plurality of drive ICs 400. The plurality of drive ICs 400 may be formed by a chip on glass (COG) or a chip on flexible printed circuit (chip on film) method.

Referring to FIG. 7A, the drive IC 400 of the liquid crystal display according to the exemplary embodiment of the present invention is formed by merging gate driver logic and data driver logic into one chip. .

Meanwhile, referring to FIG. 7B, in the drive IC 400 of the liquid crystal display according to the exemplary embodiment, the data drive IC 420 and the gate drive IC 430 are integrated into one chip.

The data drive logic or data drive IC 420 generates an analog data voltage supplied to the pixels using data control signals and digital image data applied from a controller mounted on the printed circuit board 300.

The gate drive logic or gate drive IC 430 generates a gate signal (scan signal) for switching the TFTs formed in the pixels by using a gate control signal applied from a controller mounted on the printed circuit board 300. .

A plurality of link lines 410 are formed at both sides of the drive IC 400. Here, the plurality of link lines 410 includes a plurality of gate link lines 412 and a plurality of data link lines 414.

The drive IC 400 receives a gate signal from the controller through the plurality of gate link lines 412, and supplies the generated gate signal to the pixels formed in the liquid crystal panel.

In addition, the drive IC 400 receives a data control signal and digital image data from a controller through a plurality of data link lines 414 and converts the analog data voltage generated according to the digital image data into pixels formed in the liquid crystal panel. Supply.

Since the data lines DL and the plurality of first gate lines VGL (vertical gate lines) formed in the liquid crystal panel 100 are not the same number, the gate link lines 412 and the plurality of data link lines 414 are not necessarily the same number. The same number is not formed alternately. Depending on the pitch and resolution of the pixel, the gate link line 412 and the two data link lines 414 may be formed.

Hereinafter, the structure of the liquid crystal panel 100 of the present invention will be described in detail with reference to FIG. 8. 8 is a diagram illustrating a pixel structure of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 8, a lower substrate (TFT array substrate) of a liquid crystal panel includes a plurality of first gate lines VGL, vertical gate lines, a plurality of second gate lines HGL, and horizontal data lines. DL) is formed.

A plurality of pixels is defined by the plurality of first gate lines VGL, the plurality of second gate lines HGL, and the plurality of data lines DL. A TFT is provided as a common electrode (not shown) to which a common voltage Vcom is applied to a plurality of pixels, a pixel electrode (not shown) to which a data voltage Vdata is applied, a storage capacitor Cst (not shown), and a switching element. Formed.

The active layer of the TFT may be formed of amorphous silicon (a-Si), low temperature polysilicon (LTPS), or indium gallium zinc oxide (IGZO) material.

6 and 7, the drive IC 400 in which the gate drive IC (or gate drive logic) and the data drive IC (or data drive logic) are integrated into one chip includes a liquid crystal panel ( It is formed above 100). For this reason, in the present invention, a new gate line structure is applied to supply gate signals to the pixels of the liquid crystal panel 100. 6 illustrates that the drive IC 400 is disposed above the liquid crystal panel 100, the present invention is not limited thereto, and the drive IC 400 may be disposed below the liquid crystal panel 100.

As illustrated in FIG. 8, the plurality of first gate lines VGL and the plurality of data lines DL are formed side by side in the vertical direction in the liquid crystal panel 100. That is, the plurality of first gate lines VGL is formed in parallel with the plurality of data lines DL in the same direction.

The plurality of second gate lines HGL is formed to intersect the plurality of first gate lines VGL and the plurality of data lines DL. That is, the plurality of gate lines HGL are formed in the horizontal direction.

In other words, the plurality of first gate lines VGL and the plurality of data lines are formed from the upper side to the lower side in the vertical direction so as to cross the short axis direction of the liquid crystal panel 100.

The plurality of second gate lines HGL is formed from the left to the right (or from the right to the left) in the horizontal direction so as to cross the long axis direction of the liquid crystal panel 100.

Here, the plurality of first gate lines VGL formed in the vertical direction and the plurality of second gate lines HGL formed in the horizontal direction have the same number and are formed to correspond 1: 1.

The plurality of second gate lines HGL formed in the horizontal direction are formed in the first layer, and the plurality of first gate lines VGL and the plurality of data lines DL formed in the vertical direction are formed in the second layer. .

Although the plurality of first gate lines VGL and the plurality of second gate lines HGL formed in the vertical direction are formed in different layers with an insulating layer interposed therebetween, the plurality of first gate lines VGL and the plurality of first gate lines VGL are formed. The second gate line HGL is selectively contacted through the contact CNT in a region overlapping each other. That is, the plurality of first gate lines VGL and the plurality of second gate lines HGL are electrically connected through the contact CNT in pairs one by one in a region overlapping each other.

In detail, the first first gate line VGL1 formed in the vertical direction and the first second gate line HGL1 formed in the horizontal direction are electrically connected to each other through the first contact CNT1 in a region overlapping each other. As such, the pair of vertical gate lines and the horizontal gate lines, that is, the first vertical gate line VGL1 and the first horizontal gate line HGL1 are electrically connected to each other through the first contact CNT1.

The second first gate line VGL2 formed in the vertical direction and the second second gate line HGL2 formed in the horizontal direction are electrically connected to each other through the second contact CNT2 in a region overlapping each other. As such, the pair of vertical gate lines and the horizontal gate lines, that is, the second vertical gate line VGL2 and the second horizontal gate line HGL2 are electrically connected through the second contact CNT2.

The third first gate line VGL3 formed in the vertical direction and the third second gate line HGL3 formed in the horizontal direction are electrically connected to each other through the third contact CNT2 in a region overlapping each other. In this way, the pair of vertical gate lines and the horizontal gate lines, that is, the third vertical gate line VGL3 and the third horizontal gate line HGL3 are electrically connected through the third contact CNT3.

With the same structure as described above, each of the n first gate lines VGL and the n second gate lines HGL are paired and electrically connected to each other through a contact.

The first, second, and third representations described in the foregoing description are for explaining the order and relationship between the plurality of lines, and do not indicate that the first representation is the first of all the lines, and refer to the drawings. By way of example to illustrate the invention. Hereinafter, the meanings of the first, second and third expressions apply equally to the contents of the specification.

The plurality of first gate lines VGL formed in the vertical direction are connected to the plurality of gate link lines 412 shown in FIG. 7, respectively. Through this, the gate signal output from the drive IC 400 is applied to the plurality of first gate lines VGL.

The gate signal is supplied to the TFTs of the plurality of pixels formed in the liquid crystal panel 100 via the plurality of second gate lines HGL connected to the plurality of first gate lines VGL to turn on the TFTs. turn-on). In this case, the gate signal is supplied to all pixels of the liquid crystal panel, and is sequentially supplied in units of one horizontal line.

Meanwhile, the plurality of data lines DL formed in the vertical direction are connected to the plurality of data link lines 414 shown in FIG. 7, respectively. Through this, the data voltage Vdata output from the drive IC 400 is applied to the plurality of data lines DL.

The data voltage Vdata is supplied to the source electrode of the TFT formed in the liquid crystal panel 100 via the data line DL, and when the TFT is turned on, the data voltage Vdata supplied to the source electrode causes the drain electrode. It is supplied to the pixel electrode via.

In the liquid crystal display according to the exemplary embodiment of the present invention, the scan signal is applied to the pixel through the first gate line formed in the vertical direction, and the data voltage Vdata is applied to the pixel through the data line formed in the vertical direction. In the prior art, the link lines and the GIP logic formed in the non-display areas on the left and right sides of the liquid crystal panel can be deleted.

As a result, only the common voltage link region and the ground link region may be formed in the left and right non-display regions of the liquid crystal panel 100 to reduce the bezel width to 1.0 mm to 1.6 mm.

6 to 8, in order to reduce the left and right bezel sizes of the liquid crystal panel 100, when the vertical gate line is additionally formed, the total length of the gate line is longer than before, so that the load increases and the Delays can be intensified.

However, in the liquid crystal display according to the exemplary embodiment of the present invention, the gate signal supplied to the pixel may be lower than the first gate high voltage VGH1 and the first gate high voltage as described with reference to FIGS. 4 and 5. Delaying the gate signal by generating a scan pulse having a second gate high voltage VGH2 of a level, a first gate low voltage VGL1 of negative polarity, and a second gate low voltage VGL2 that is lower than the first gate low voltage. This can improve the problem.

As described above, a gate signal is generated using two gate high voltages VGH1 and VGH2 and two gate low voltages VGL1 and VGL2, that is, a total of four voltages VGL1, VGL2, VGH1, and VGH2. As a result, it is possible to prevent the charge ratio of the pixel voltage due to the delay of the gate signal generated due to the enlargement of the liquid crystal panel. In addition, due to the delay of the gate signal, data of adjacent pixels may be overlapped to prevent generation of flicker.

Referring to Table 1 and FIG. 5, as shown in FIG. 8, when a gate signal of the prior art is applied to a pixel structure in which a vertical gate line is additionally formed, the gate signal supplied to the first gate line is turned on. The deviation ΔVp1 of the pixel voltage charged in the on pixels is 0.539V, and the deviation ΔVp2 0.422V of the pixel voltage charged in the pixels turned on by the gate signal supplied to the last gate line. Accordingly, the value obtained by subtracting ΔVp2 from ΔVp1 (ΔVp1 to ΔVp2), that is, the deviation of the pixel voltage charged in all the pixels is 0.117V.

On the other hand, as shown in FIG. 8, when the gate signal of the present invention shown in FIG. 4 is applied to a pixel structure in which a vertical gate line is additionally formed, the pixels turned on by the gate signal supplied to the first gate line. The deviation ΔVp1 of the pixel voltage charged at is 0.390V, and the deviation ΔVp2 0.397V of the pixel voltage charged at the pixels turned on by the gate signal supplied to the last gate line. Accordingly, the value obtained by subtracting ΔVp2 from ΔVp (ΔVp1 to ΔVp2), that is, the deviation of the pixel voltage charged in all the pixels becomes 0.011V.

In this way, the vertical gate line is applied to reduce the size of the left and right bezels of the liquid crystal panel to increase the design aesthetics of the liquid crystal display device, and the gate signal of the gate signal lengthened by applying the gate signal of the present invention shown in FIG. The occurrence of problems due to delay can be prevented.

Those skilled in the art to which the present invention pertains will understand that the above-described present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: liquid crystal panel 200: gate drive circuit
300: printed circuit board 400: drive IC
500: data drive IC VGH1: first gate high voltage
VGH2: second gate high voltage VGL1: first gate low voltage
VGL2: second gate low voltage

Claims (9)

A plurality of data lines and a plurality of first gate lines formed parallel to each other in the liquid crystal panel, and a plurality of second gate lines formed in the liquid crystal panel in a horizontal direction and one-to-one contact with each of the plurality of first gate lines; And a plurality of pixels defined by the plurality of data lines, the plurality of first gate lines, and the plurality of second gate lines.
A first gate high voltage for turning on TFTs formed in the plurality of pixels;
A second gate high voltage having a voltage value lower than the first gate high voltage;
A first gate low voltage for maintaining a turn-off state of the TFT; And
Generate a gate signal formed of a second gate low voltage for turning off the TFT to a voltage value lower than the first gate low voltage,
And supplying the gate signal to the plurality of first gate lines to switch TFTs of each of the plurality of pixels connected to each of the plurality of second gate lines in one-to-one contact with the plurality of first gate lines. Method of driving. The method of claim 1,
And the gate signal is raised from the first gate low voltage of negative polarity to the first gate high voltage in a first period of turning on the TFT. The method of claim 1,
And the gate signal is maintained at the first gate high voltage in a second period of maintaining the turn-on of the TFT. The method of claim 1,
The gate signal is applied from the first gate high voltage to the second gate high voltage by applying a gate pulse modulation in a third period for reducing the polling time of the signal. . The method of claim 1,
And the gate signal is lowered to the second gate low voltage lower than the first gate low voltage in a fourth period of turning off the TFT. The method of claim 5,
And applying under driving driving to lower the voltage value of the gate signal from the second gate high voltage to the second gate low voltage. The method of claim 5,
And the gate signal rises from the second gate low voltage to the first gate low voltage after the fourth period to maintain the off state of the TFT. The method of claim 1,
Wherein the first gate high voltage is + 35V, the second gate high voltage is + 20V, the first gate low voltage is -5V, and the second gate low voltage is -15V. The method of claim 1,
And the second gate high voltage is a voltage value higher than a maximum value of a data voltage.

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