KR101979403B1 - Method for controlling radar output frequency and radar system implementing the method - Google Patents

Abstract

Provided is a radar system, which comprises: a frequency counter receiving a first signal where an output frequency of a radar transceiver is divided by a first division ratio or a second signal where the first signal is divided by a second division ratio, counting a high value of an input signal to a clock of a specific frequency, and then outputting a count value accumulated during a time corresponding to the number of count cycles of the input signal; and a controller calculating an estimated frequency corresponding to the count value based on the frequency of the clock, the number of count cycles, and a total division ratio for dividing the output frequency by the input signal, and comparing the estimated frequency with a reference frequency range to correct an output frequency of the radar transceiver.

Description

TECHNICAL FIELD [0001] The present invention relates to a radar output frequency control method, a radar output frequency control method, and a radar system implementing the radar output frequency control method.

The present invention relates to radar output frequency control.

A radar is a technique of transmitting an electromagnetic wave to receive a signal reflected from a target to obtain target information. Radar is used as a main sensor for ADAS (Advanced Driver Assistance System) and ITS (Intelligent Transport Systems) implementation. It is also used as a sensor in various fields requiring motion detection, speed, direction and distance measurement. Radar uses high frequencies such as 24GHz and 77GHz, and high frequency radar has the advantage of increasing performance and reducing antenna size.

The radar transceiver chip may be a monolithic microwave integrated circuit (MMIC) with a highly integrated Rx / Tx module. The radar MMIC integrates Voltage Controlled Oscillator (VCO), Power Amplifier (PA), Low Noise Amplifier (LNA), and Mixer.

Radar MMICs that implement various RF devices on silicon wafers may have different output characteristics depending on temperature. In particular, referring to FIG. 1, even if the radar MMIC applies the same voltage to the VCO, the VCO frequency varies depending on the temperature. If the output frequency of the radar MMIC changes, the antenna matching may deviate and violate the radio wave method beyond the specified frequency range.

There is a method of using a look-up table as a method of correcting a frequency deviation according to temperature, but there is a limit to control the frequency depending on a look-up table without knowing the current output frequency.

A PLL (Phase-Locked Loop) circuit outside the radar MMIC can be configured to output a fixed VCO frequency regardless of temperature changes. However, expensive PLL chips have to be added, which increases circuit design complexity.

A problem to be solved by the present invention is to provide a method of calculating an output frequency of a radar MMIC and controlling an output frequency of the radar MMIC without using a PLL circuit, and a radar system implementing the method.

A radar system according to an embodiment is a radar system according to an embodiment of the present invention, in which a first signal whose output frequency of a radar transceiver is divided by a first division ratio or a second signal whose first signal is divided by a second division ratio is input, A frequency counter for counting a high value of the clock signal and outputting a count value accumulated during a time corresponding to the count period of the input signal, And a controller for calculating an estimated frequency corresponding to the count value based on the frequency dividing ratio and comparing the estimated frequency with a reference frequency range to correct an output frequency of the radar transceiver.

The controller may transmit a control signal for correcting the output frequency of the radar transceiver to the radar transceiver when the estimated frequency is out of the reference frequency range.

The control signal may be an output value of a DAC (Digital Analog Converter). The controller may change an output value of the DAC to correct a frequency of a VCO (Voltage Controlled Oscillator) of the radar transceiver.

The radar system may further include an oscillator for providing the clock.

The frequency counter detects a time point at which the waveform of the input signal rises from a low level to a high level or a time point from a high level to a low level as a period start, A high value can be counted.

Wherein the frequency counter receives the second signal from a frequency dividing flip-flop, the flip-flop outputs the second signal obtained by dividing the first signal by the second dividing ratio, and the frequency counter and the flip- Can be implemented in a designable logic block device.

There is provided a method of controlling an output frequency of a radar system, the method comprising: receiving a signal output from a VCO (Voltage Controlled Oscillator) of a radar transceiver at a predetermined frequency division ratio; The method comprising the steps of: accumulating a count value obtained by counting a high value of the input signal with a clock of a specific frequency, determining whether the frequency of the VCO is within a reference frequency range using the count value, And generating a control signal for correcting the frequency of the VCO when the frequency is out of the reference frequency range.

Wherein the step of determining whether the frequency of the VCO is within the reference frequency range includes calculating an estimated frequency corresponding to the count value based on the frequency of the clock, the number of count cycles, and the total frequency division ratio of the frequency of the VCO to the input signal. And compare the estimated frequency with the reference frequency range.

The step of generating the control signal may generate an output value of a DAC (Digital Analog Converter) that changes the frequency of the VCO.

The step of accumulating the count value may include detecting a time point at which the waveform of the input signal goes from a low level to a high level or a time point when the waveform goes down from a high level to a low level, Can be calculated.

The input signal may be a first signal divided by a first division ratio set in the radar transceiver or a second signal divided by a second division ratio.

According to the embodiment, the output frequency of the radar transceiver MMIC can be controlled by using an FPGA frequency counter which is inexpensive and simple in circuit design instead of an expensive complicated PLL circuit.

According to the embodiment, the output frequency of the current radar transceiver MMIC can be calculated using the frequency count value, so that the output frequency can be accurately corrected to the reference frequency range, and it is possible to immediately check whether the radar transceiver MMIC is abnormal.

According to the embodiment, the controller 300 can control the output frequency by using the frequency count value, which is a digital value, so that it is possible to reduce the process occupation rate for the frequency control and perform the other-purpose calculation processing.

1 is a graph of VCO frequency change with temperature.
2 is a diagram for explaining a frequency stabilization method using a PLL.
3 is a block diagram of a radar system according to one embodiment.
4 is a view for explaining an output frequency counting method of a radar transceiver MMIC according to an embodiment.
5 is a flowchart of a radar output frequency control method for an FPGA and a controller according to an embodiment.
6 is a flowchart of a radar output frequency control method of a radar system according to an embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when an element is referred to as " comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise. Also, the terms " part, " " module, " and " module ", etc. in the specification mean a unit for processing at least one function or operation and may be implemented by hardware or software or a combination of hardware and software have.

2 is a diagram for explaining a frequency stabilization method using a PLL.

Referring to FIG. 2, the VCO frequency of the radar MMIC may vary depending on the temperature. If the output frequency of the radar MMIC is changed, the antenna matching may deviate and may deviate from the prescribed frequency range, so that frequency stabilization according to temperature is required.

The frequency can be corrected by constructing a PLL (Phase-Locked Loop) circuit outside the radar MMIC by outputting the fixed VCO frequency irrespective of the temperature change. However, there is a limitation in that an expensive PLL chip must be added, thereby increasing circuit design complexity.

Next, a method of controlling the output frequency of a radar transceiver MMIC which is less expensive than a PLL circuit using a designable logic block device and is simple in circuit design will be described. In the present invention, a field programmable gate array (FPGA) is described as a designable logic block device. However, the present invention is not limited thereto, and a circuit capable of implementing the frequency counter and the frequency dividing flip-flop described in the present invention is sufficient.

FIG. 3 is a block diagram of a radar system according to an embodiment, and FIG. 4 is a view for explaining an output frequency counting method of a radar transceiver MMIC according to an embodiment.

3, the radar system 10 includes a radar transceiver MMIC 100 having a highly integrated RF transceiver module, an FPGA 200 as a designable logic block device, a microcontroller unit (MCU) 300, a synchronous clock (Not shown). The controller 300 multiplies the clock input from the oscillator 400 and uses the clock to input the clock inputted from the oscillator 400 to the FPGA 200 to synchronize with the FPGA 200.

The radar transceiver MMIC 100 includes a transmit (Tx) module for transmitting an RF signal to a transmit antenna and a receive (Rx) module for receiving an RF signal via the receive antenna. The radar transceiver MMIC 100 has integrated RF elements such as a voltage controlled oscillator (VCO), a power amplifier (PA), a low noise amplifier (LNA), and a mixer.

The transmitter module may include a VCO 110, a PA 130, and a frequency divider 150, which are necessary for the description of the present invention, while the inside of the radar transceiver MMIC 100 may be variously designed by the manufacturer. , Their connection relations can be various and complex, but they are simply indicated in the drawings. Since the VCO 110, the PA 130, and the frequency divider 150 are already known RF elements, their description of their operation is omitted.

The radar transceiver MMIC 100 outputs to the FPGA 200 a signal obtained by dividing the output frequency of the VCO 110 by 1 / N. The output frequency of the VCO 110 may be frequency divided by the frequency divider 150. For example, the division ratio (N1) of the Infineon BGT24LTR11 MMIC is 8192, and when the VCO output frequency is 24 GHz, a square wave of 2.9296 MHz (= 24 GHz / 8192) is output from the BGT24LTR11 MMIC.

The FPGA 200 includes a frequency counter 210. The FPGA 200 may further include a flip-flop 230 for frequency distribution.

The frequency counter 210 counts a high value of the input signal in synchronization with the frequency clock of the oscillator 400. At this time, the frequency counter 210 counts a high value of the input signal while the cycle of the input signal is repeated a specified number of times (T _count ). The frequency counter 210 detects a rising edge of a waveform of the input signal from a low level to a high level or a falling edge of falling from a high level to a low level . The FPGA 200 can receive the frequency clock provided from the oscillator 400 from the controller 300. [

The frequency counter 210 transmits the counted number of count cycles of the input signal (for example, T _count is 300 cycles) to the controller 300.

If the frequency counter 210 is able to count the frequency signal output from the radar transceiver MMIC 100, the flip-flop 230 may be omitted. However, when the frequency of the signal output from the radar transceiver MMIC 100 is high, the frequency counter 210 can not count the high value of the input signal through the clock. In this case, the FPGA 200 may be configured such that a signal received from the radar transceiver MMIC 100 is divided into low frequency bands through the flip-flop 230. That is, the flip-flop 230 receives the frequency signal from the radar transceiver MMIC 100 and lowers the input frequency signal to a frequency band that can be counted by the frequency counter 210.

4, when the frequency division ratio N2 of the flip-flop 230 is 8, the frequency of the frequency division signal (square wave) output from the flip-flop 230 is 0.3662 MHz (= 2.9296 MHz / 8).

The frequency counter 210 counts the high value of the signal output from the flip-flop 230 in accordance with the clock provided by the oscillator 400. [ The value counted high by the 32 MHz clock in one period of the output signal (0.3662 MHz) of the flip-flop 230 is 43.6919 times (= (32 MHz / 2) /0.3662 MHz) when the frequency provided by the oscillator 400 is 32 MHz ]to be.

The frequency counter 210 transmits the count value during the count period to the controller 300. When the count period is 366 periods corresponding to about 1 ms, the frequency counter 210 counts 15991, (300). The frequency dividing signal (0.3662 MHz) output from the flip-flop 230 has a period of 2.7307 * 10 ^-6 sec. Since the value counted in one period is 43.6919, it is counted 15991 times for 1 ms (corresponding to 366 cycles).

The controller 300 receives a count value (frequency count value) for the output frequency of the radar transceiver MMIC 100 from the frequency counter 210.

The controller 300 may calculate (estimate) the output frequency f _{o_estimated} of the radar transceiver MMIC 100 using the frequency count value C _f and various parameters, as shown in Equation (1).

In Equation (1), f _{counter_clock} may be provided in the oscillator 400 as the clock frequency of the frequency counter 210. C _f is the frequency count value received from the frequency counter 210. T _count is the number of cycles (the number of count cycles) of the input signal that counts the high value in the frequency counter 210. For example, if T _count is 300, the frequency counter 210 counts a high value for 300 periods of the input signal. N _{f_} divider is the total division ratio of the VCO output frequency and may be a product of the frequency division ratio N ₁ of the radar transceiver MMIC 100 and the frequency division ratio N ₂ of the flip flop 230.

The controller 300 determines whether the output frequency f _{o_estimated} of the radar transceiver MMIC 100 is in the reference frequency range. The controller 300 transmits a control signal for frequency correction of the VCO 110 to the radar transceiver MMIC 100 when the output frequency is out of the reference frequency range. The controller 300 may periodically perform frequency correction.

 When the calculated output frequency differs from the reference frequency range, the controller 300 controls an output value of a DAC (Digital Analog Converter) input to the VCO 110 to correct the output frequency of the VCO 110. When the calculated output frequency is within the reference frequency range, the controller 300 maintains the output value of the DAC input to the VCO 110 as it is.

5 is a flowchart of a radar output frequency control method for an FPGA and a controller according to an embodiment.

Referring to FIG. 5, the FPGA 200 receives an output frequency signal from the radar transceiver MMIC 100 (S110). The output frequency signal f _{mmic_out} is _divided and output by the dividing ratio N1 determined by the radar transceiver MMIC 100.

The FPGA 200 counts a high value of the input signal at a clock frequency (f _{counter_clock} ) for a predetermined time (S120). The time is a time corresponding to the number of count cycles (T _count , for example, 300 cycles) of the input signal. The FPGA 200 controls the timing at which the waveform of the input signal rises from a low level to a high level, The point of view can be detected as the start of the cycle. At this time, the FPGA 200 is designed to count a high value of the output frequency signal of the radar transceiver MMIC 100, or to divide the output frequency signal of the radar transceiver MMIC 100 into a predetermined frequency division ratio N2, Can be designed to count the high value of the signal. For this purpose, the FPGA 200 may implement a flip-flop 230 for frequency division together with the frequency counter 210.

The FPGA 200 transmits the frequency high value count value C _f of the input signal accumulated for a predetermined time (time corresponding to the T _count cycle) to the controller 300 (S 130).

Controller 300 includes a FPGA (200) the clock frequency (f _{counter_clock),} the count period of the FPGA (200) (T _count), and the frequency count value on the basis of the total frequency division ratio (N _{f_divider)} of the VCO output frequency (C of It estimates the output frequency (f _{o_estimated)} corresponding to _f) (S140).

The controller 300 determines whether the estimated output frequency _{fo_estimated} is within the reference frequency range (S150).

The controller 300 transmits a control signal for frequency correction of the VCO 110 to the radar transceiver MMIC 100 when the estimated output frequency is out of the reference frequency range (S160). The controller 300 may control a DAC output value input to the VCO 110 to correct the output frequency of the VCO 110.

If the estimated output frequency is within the reference frequency range, the controller 300 maintains the currently set value (S170). The controller 300 maintains the output value of the DAC input to the VCO 110 as it is.

The controller 300 may periodically perform frequency correction.

According to another embodiment, the controller 300 can recognize the deviation of the output frequency by the frequency count value C _f , so that the controller 300 can calculate the frequency count value C _f and the count value of the reference frequency (for example, The output frequency of the radar transceiver MMIC 100 can be controlled.

6 is a flowchart of a radar output frequency control method of a radar system according to an embodiment.

Referring to FIG. 6, the radar system 10 receives a signal output from the VCO of the radar transceiver MMIC 100 divided by a certain frequency division ratio (S210). The radar system 10 may be a signal divided by a division ratio set in the radar transceiver MMIC, or a signal output from the flip-flop 230.

The radar system 10 accumulates a count value obtained by counting a high value of the input signal with a clock of a specific frequency for a time corresponding to the count period of the input signal (S220). At this time, the radar system 10 detects a time point at which the waveform of the input signal goes from a low level to a high level or a time point from a high level to a low level as a cycle start, Time can be calculated.

The radar system 10 uses the count value to determine whether the frequency of the VCO is within the reference frequency range (S230). The radar system 10 calculates a frequency corresponding to the count value based on the frequency of the clock, the number of count cycles, and the frequency of the VCO as the input signal, and estimates the output frequency of the VCO. Compare the reference frequency range.

The radar system 10 generates a control signal for correcting the frequency of the VCO when the frequency of the VCO is out of the reference frequency range (S240). The radar system 10 may generate an output value of the DAC that changes the frequency of the VCO.

According to the embodiment, the output frequency of the radar transceiver MMIC can be controlled by using an FPGA frequency counter which is inexpensive and simple in circuit design instead of an expensive complicated PLL circuit.

According to the embodiment, the output frequency of the current radar transceiver MMIC can be calculated using the frequency count value, so that the output frequency can be accurately corrected to the reference frequency range, and it is possible to immediately check whether the radar transceiver MMIC is abnormal.

According to the embodiment, the controller 300 can control the output frequency by using the frequency count value, which is a digital value, so that it is possible to reduce the process occupation rate for the frequency control and perform the other-purpose calculation processing.

The embodiments of the present invention described above are not implemented only by the apparatus and method, but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (11)

As a radar system,
A first signal whose output frequency of the radar transceiver is divided by a first division ratio or a second signal whose first signal is divided by a second division ratio is received and the number of clocks at a high value of the input signal is counted by a clock of a specific frequency A frequency counter for outputting a count value accumulated during a time corresponding to the count period of the input signal,
Estimating an output frequency of the radar transceiver based on the frequency of the clock, the number of count cycles, the total division ratio for dividing the output frequency into the input signal, and the count value, And a controller for transmitting a control signal for correcting an output frequency of the radar transceiver to the radar transceiver when the estimated output frequency is out of the reference frequency range,
And a radar system. delete The method of claim 1,
The control signal is an output value of a DAC (Digital Analog Converter)
The controller
And modifies the frequency of a VCO (Voltage Controlled Oscillator) of the radar transceiver by changing an output value of the DAC. The method of claim 1,
Further comprising an oscillator providing said clock. The method of claim 1,
The frequency counter
A time point when the waveform of the input signal rises from a low level to a high level or a time point from a high level to a low level is detected as a period beginning and a high value is counted for a time corresponding to the count period number Radar system. The method of claim 1,
The frequency counter receives the second signal from the frequency dividing flip-flop,
The flip-flop outputs the second signal obtained by dividing the first signal by the second division ratio,
Wherein the frequency counter and the flip-flop are implemented in a designable logic block device. A method of controlling an output frequency of a radar system,
Receiving a signal output from a VCO (Voltage Controlled Oscillator) of a radar transceiver, the signal being divided by a predetermined frequency division ratio;
Accumulating a count value obtained by counting the number of clocks at a high value of the input signal with a clock of a specific frequency for a time corresponding to the number of count cycles of the input signal;
Estimating an output frequency of the VCO based on the frequency of the clock, the number of count cycles, the total division ratio for dividing the output frequency by the input signal, and the count value,
Determining whether the estimated output frequency is within a reference frequency range of the radar transceiver,
Generating a control signal for correcting the estimated output frequency when the estimated output frequency is out of the reference frequency range, and
Transmitting the control signal to the radar transceiver
/ RTI > delete 8. The method of claim 7,
The step of generating the control signal
And generating an output value of a DAC (Digital Analog Converter) that changes the frequency of the VCO. 8. The method of claim 7,
The step of accumulating the count value
A time point at which the waveform of the input signal rises from a low level to a high level or a time point from a high level to a low level is detected as a cycle start to calculate a time corresponding to the count period number, Output frequency control method. 8. The method of claim 7,
The input signal
Wherein the signal output from the VCO is a first signal divided by a first division ratio set in the radar transceiver or the first signal is a second signal divided by a second division ratio.

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