KR101958421B1 - Integrated circuit, Semiconductor device based on the integrated circuit and Standard cell library - Google Patents

Abstract

The present disclosure relates to an integrated circuit comprising at least one cell wherein at least one cell comprises a plurality of conductive lines extending in a first direction and arranged parallel to each other along a second direction perpendicular to the first direction, A plurality of first conductors disposed on both sides of at least one of the plurality of conductive lines and first contacts disposed on both sides of the at least one conductive line and at least one conductive line and first contacts, Lt; RTI ID = 0.0 > a < / RTI > node.

Description

[0001] The present invention relates to an integrated circuit, a semiconductor device based on the integrated circuit, and a standard cell library,

The technical idea of the present invention relates to an integrated circuit, and more particularly to an integrated circuit including at least one cell, a semiconductor device implemented according to the integrated circuit, and a standard cell for storing information about the at least one cell Library.

Due to the miniaturization of transistors due to the development of semiconductor processing technology, a larger number of transistors are being integrated in semiconductor devices. For example, a system-on-chip (SOC), which refers to an integrated circuit (IC) that integrates all the components of a computer or other electronic system on a single chip, As the performance of an application is improved, a semiconductor device including more components is required.

It is an object of the technical idea of the present invention to provide an integrated circuit including at least one cell capable of reducing operational errors due to shorts or the like between conductive lines, a semiconductor device implemented according to the integrated circuit, In which the information on the cell of the cell is stored.

An integrated circuit according to the technical aspects of the present invention comprises at least one cell, said at least one cell comprising a plurality of cells arranged in parallel in a second direction extending in a first direction and perpendicular to the first direction Conductive lines, first contacts disposed on both sides of at least one conductive line of the plurality of conductive lines, and first contacts disposed on top of the at least one conductive line and the first contacts, A conductive line and a second contact electrically connected to the first contacts to form a node.

In some embodiments, the first contacts extend in the first direction, and the second contacts extend in the second direction.

In some embodiments, the second contact may be disposed in a direction perpendicular to the first contacts.

In some embodiments, the at least one cell further comprises first and second active regions having different conductivity types, and the second contact comprises at least one of the first active region and the second active region, Can be placed on one.

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first transistors formed on the first active region may be greater than the number of first transistors formed on the second active region, Lt; / RTI >

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first transistors formed on the first active region may be greater than the number of first transistors formed on the second active region, May be greater than or equal to the number of < / RTI >

In some embodiments, the at least one cell may further include a plurality of pins extending in the second direction on the first and second active areas and disposed parallel to each other along the first direction have.

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first pin transistors formed on the first active region may be greater than the number of second pin transistors formed on the second active region, May be less than the number of pin transistors.

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first pin transistors formed on the first active region may be greater than the number of second pin transistors formed on the second active region, May be greater than or equal to the number of pin transistors.

In some embodiments, the at least one cell is disposed between the first and second active regions, wherein the at least one cell comprises a cut region that isolates the at least one conductive line on the second active region from the one node, As shown in FIG.

In some embodiments, the at least one conductive line includes a first conductive line and a second conductive line disposed to the right of the first conductive line, wherein the first contacts are located on the left side of the first conductive line A first left contact disposed in the first housing; And a first right contact disposed on the right side of the second conductive line.

In some embodiments, the second contact is disposed on top of the first left contact, the first right contact, the first conductive line, and the second conductive line, and the first left contact, the first contact, The right contact, the first conductive line, and the second conductive lines.

In some embodiments, the first contacts may further comprise a first central contact disposed between the first conductive line and the second conductive line.

In some embodiments, the second contact is disposed on top of the first left contact, the first right contact, the first center contact, the first conductive line, and the second conductive line, Left contact, the first right contact, the first center contact, the first conductive line, and the second conductive line.

In some embodiments, the plurality of conductive lines include first through third conductive lines disposed adjacent to each other, and the first contacts are arranged between the first conductive line and the second conductive line, A first left contact and a first right contact disposed between the second conductive line and the third conductive line, the length of the second contact along the second direction being greater than the length of the first left contact, 1 < / RTI > right contact, and may be less than the distance between the first conductive line and the third conductive line.

In some embodiments, the length of each of the first contacts along the second direction may be less than the space between two adjacent ones of the plurality of conductive lines.

In some embodiments, the lengths of the first contacts along the first direction are identical to each other, and the first contacts and the second contact may form an H-shaped jumper.

In some embodiments, the lengths of the first contacts along the first direction are different, and the first contacts and the second contact may form an L-shaped jumper.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate having first and second active regions having different conductivity types; a first electrode formed on an upper portion of the substrate, A plurality of conductive lines arranged parallel to each other along two directions, first contacts disposed on both sides of at least one conductive line of the plurality of conductive lines, respectively, and first and second contacts, A second contact disposed over the at least one conductive line and the first contacts and electrically connected to the at least one conductive line and the first contacts to form a node, .

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first transistors formed on the first active region may be greater than the number of first transistors formed on the second active region, Lt; / RTI >

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first transistors formed on the first active region may be greater than the number of first transistors formed on the second active region, May be greater than or equal to the number of < / RTI >

In some embodiments, the device further comprises a plurality of fins extending on the substrate in the second direction and disposed parallel to one another along the first direction, the plurality of conductive lines being arranged on the top of the plurality of pins .

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first pin transistors formed on the first active region may be greater than the number of second pin transistors formed on the second active region, May be less than the number of pin transistors.

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first pin transistors formed on the first active region may be greater than the number of second pin transistors formed on the second active region, May be greater than or equal to the number of pin transistors.

In some embodiments, the top level of the plurality of conductive lines and the first contacts may be substantially the same as each other.

According to another technical idea of the present invention, a standard cell library is a standard cell library including information on a plurality of standard cells and stored in a computer-readable storage medium, wherein at least one of the plurality of standard cells A plurality of fins arranged in parallel with each other on the first and second active regions, first and second active regions having different conductivity types, A plurality of conductive lines disposed parallel to each other along a second direction perpendicular to the one direction, first contacts disposed on both sides of at least one of the plurality of conductive lines, And at least one of the first contacts and the at least one second conductive region is electrically connected to the first contacts and the at least one conductive line on at least one of the first active region, Contacts.

In some embodiments, the plurality of pins may extend in the second direction.

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first pin transistors formed on the first active region may be greater than the number of second pin transistors formed on the second active region, May be less than the number of pin transistors.

In some embodiments, the plurality of conductive lines may correspond to a plurality of gate electrodes, respectively, and the number of first pin transistors formed on the first active region may be greater than the number of second pin transistors formed on the second active region, May be greater than or equal to the number of pin transistors.

SUMMARY OF THE INVENTION According to the technical idea of the present invention, there is provided an integrated circuit comprising: a conductive line in one cell included in an integrated circuit, first contacts disposed on both sides of the conductive line, By forming a node by electrically connecting the second contacts arranged vertically to the contacts, it is possible to design an integrated circuit in which the conductive line connected to the node is skipped. Accordingly, the integrated circuit can be easily designed even when the number of the PMOS transistors and the number of the NMOS transistors are different in one cell included in the integrated circuit.

1 is a layout for a portion of an integrated circuit according to one embodiment of the present disclosure;
2 is a layout for a portion of an integrated circuit according to another embodiment of the present disclosure;
3 is a cross-sectional view showing an example of a semiconductor element having the layout of FIG.
4 is a layout for a portion of an integrated circuit that is substantially equivalent to the embodiment of FIG.
5 is a layout for a portion of an integrated circuit according to another embodiment of the present disclosure;
6 is a cross-sectional view showing an example of a semiconductor element having the layout of FIG.
7 is a layout for a portion of an integrated circuit according to another embodiment of the present disclosure;
8 is a cross-sectional view showing an example of a semiconductor element having the layout of FIG.
Figure 9 is a layout for a portion of an integrated circuit substantially equivalent to the embodiment of Figure 5;
10 is a layout for an integrated circuit according to another embodiment of the present disclosure;
Figure 11 is a layout for an integrated circuit substantially equivalent to the embodiment of Figure 10;
FIG. 12 is a perspective view showing an example of a semiconductor element having the layout of FIG. 10; FIG.
13 is a sectional view taken along the line XII-XII 'in Fig.
14 is a perspective view showing another example of a semiconductor element having the layout of Fig.
15 is a cross-sectional view taken along line XIV-XIV 'of Fig.
16 is a cross-sectional view taken along the line XVI-XVI 'in FIG.
17 is a layout for an integrated circuit according to another embodiment of the present disclosure;
Figure 18 is a layout for an integrated circuit substantially equivalent to the embodiment of Figure 17;
19 is a circuit diagram showing the integrated circuit of Fig.
20 is a circuit diagram showing the third node region of FIG. 19 in more detail.
21 is a layout for an integrated circuit according to another embodiment of the present disclosure;
Figure 22 is a layout for an integrated circuit substantially equivalent to the embodiment of Figure 21;
23 is a block diagram illustrating a storage medium according to one embodiment of the present disclosure;
24 is a block diagram illustrating a memory card including an integrated circuit according to one embodiment of the present disclosure;
25 is a block diagram illustrating a computing system including an integrated circuit according to one embodiment of the present disclosure;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, the terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Figure 1 is a layout for a portion of an integrated circuit 100A in accordance with one embodiment of the present disclosure.

Referring to FIG. 1, the integrated circuit 100A may include at least one cell (CELL) defined by a cell boundary indicated by a thick solid line. The cell CELL may include the first to third conductive lines 140a to 140c, the first contacts 150a and 150b, and the second contact 160a. Although not shown, a plurality of conductive lines, e.g., metal lines, may be further disposed on the cell (CELL).

In this embodiment, the cell CELL may be a standard cell. Such a standard cell-based layout design technique is designed such that elements such as OR gates or AND gates used repeatedly are preliminarily designed as standard cells and stored in a computer system, It is possible to shorten the time required for the layout design.

The first to third conductive lines 140a to 140c may extend in a first direction (e.g., the Y direction). In addition, the first to third conductive lines 140a to 140c may be arranged parallel to each other along a second direction (e.g., the X direction) substantially perpendicular to the first direction. At this time, the first to third conductive lines 140a to 140c may be made of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, or the like.

In one embodiment, the first through third conductive lines 140a through 140c may correspond to the gate electrodes. However, the present invention is not limited thereto, and the first to third conductive lines 140a to 140c may be traces having any conductivity. 1, the cell CELL includes the first through third conductive lines 140a through 140c. However, this is merely an example, and the cell CELL extends in the first direction, And four or more conductive lines arranged parallel to each other along two directions.

The first contacts 150a and 150b may extend in a first direction. Also, the first contacts 150a and 150b may be disposed parallel to each other along a second direction substantially perpendicular to the first direction. Here, the first contacts 150a and 150b may be made of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, or the like. Thus, the first contacts 150a and 150b may provide a power supply voltage or a ground voltage, for example, in a region disposed under the spaces between the first to third conductive lines 140a to 140c.

In this embodiment, the first contacts 150a and 150b may be disposed on both sides of the second conductive line 140b, respectively. Specifically, the first contacts 150a and 150b include a first left contact 150a disposed on the left side of the second conductive line 140b and a first right side contact 150b disposed on the right side of the second conductive line 140b 150b. In other words, the first left contact 150a is disposed between the first conductive line 140a and the second conductive line 140b, the first right contact 150b is disposed between the second conductive line 140b and the third conductive line 140b, Line 140c. ≪ / RTI >

The length W1a along the second direction of the first left contact 150a in this embodiment is smaller than the space S1 between the first conductive line 140a and the second conductive line 140b . The width W1b along the second direction of the first right contact 150b may be smaller than the space S1 between the second conductive line 140b and the third conductive line 140c. In one embodiment, the width W1a of the first left contact 150a and the width W1b of the first right contact 150b may be substantially equal to each other. However, the present invention is not limited to this. In another embodiment, the width W1a of the first left contact 150a and the width W1b of the first right contact 150b may be different from each other.

The second contact 160a is disposed on the second conductive line 140b and the first contacts 150a and 150b and is electrically connected to the second conductive line 140b and the first contacts 150a and 150b. Can be connected to form one node. In addition, the second contact 160a may extend in the second direction and thereby be disposed in a direction across the second conductive line 140b and the first contacts 150a and 150b. At this time, the second contact 160a may be made of any material having electrical conductivity, and may include, for example, polysilicon, metal, metal alloy, or the like. Thus, the second contact 160a may provide the same power supply voltage or ground voltage to the second conductive line 140b and the first contacts 150a and 150b, for example.

The length W1c along the second direction of the second contact 160a is greater than the distance D1a between the first left contact 150a and the first right contact 150b, May be less than the distance D1b between the first conductive line 140a and the third conductive line 140c. The second contact 160a can be electrically connected to the second conductive line 140b, the first left contact 150a and the first right contact 150b and the first and third conductive lines 140a, 140c, respectively.

In the present embodiment, the length along the first direction of the first left contact 150a, that is, the height H1a and the length along the first direction of the first right contact 150b, i.e., the height H1b, . ≪ / RTI > Thus, the first left contact 150a, the first right contact 150b, and the second contact 160a can form an H-shaped jumper. Here, the jumper is a conductor having a relatively short length for connecting any two points or two terminals in the integrated circuit 100A.

As described above, according to this embodiment, one node can be formed by electrically connecting the second conductive line 140b, the first contacts 150a and 150b, and the second contact 160a. Thus, the integrated circuit 100A implemented according to the layout illustrated in FIG. 1 may have a skp or screened configuration of the second conductive line 140b. Therefore, the j-shaped jumper according to the present embodiment can be referred to as a skip device.

As described above, according to this embodiment, since the second conductive line 140b, the first contacts 150a and 150b, and the second contact 160a are electrically connected from the beginning, the second conductive line 140b is skipped Cell can be designed. This eliminates the possibility of electrical shorts that may occur when the first contacts 150a and 150b and the second contact 160a are disposed to be spaced apart from the second conductive line 140b to form a jumper

The above-described layout information for the standard cell can be stored in the standard cell library. Specifically, the standard cell library includes information about a plurality of standard cells and can be stored in a computer-readable storage medium. The standard cell corresponding to the information contained in the standard cell library refers to a unit of an integrated circuit whose size satisfies a predetermined rule. For example, the height of the layout of standard cells (e.g., the length in the Y direction in FIG. 1) And the width of the standard cell (e.g., the length in the X direction in FIG. 1) may vary depending on the standard cell. The standard cell can include an input pin and an output pin, and can process an input signal received at an input pin and output an output signal at an output pin.

The integrated circuit may be defined as a plurality of standard cells, and the tool for designing the integrated circuit may be implemented by designing the integrated circuit using a standard cell library containing information on a plurality of standard cells, . A tool for designing an integrated circuit includes a pattern formed in a layer formed after pins of a standard cell are formed in a semiconductor process by arranging vias in the pins (i.e., input pin and output pin) included in the standard cell You can connect. That is, the input signal or the output signal of the standard cell can be moved by disposing the via in the pin of the standard cell.

Figure 2 is a layout for a portion of an integrated circuit 100B in accordance with another embodiment of the present disclosure.

Referring to FIG. 2, the integrated circuit 100B may include first to third conductive lines 140a to 140c, first contacts 150a and 150b ', and a second contact 160a. The integrated circuit 100B according to the present embodiment is an alternative embodiment to the integrated circuit 100A illustrated in Fig. 1, and the contents described above with reference to Fig. 1 can also be applied to this embodiment. Therefore, redundant description will be omitted below.

In the present embodiment, the length of the first left contact 150a along the first direction, that is, the height H1a and the length along the first direction of the first right contact 150b ', that is, the height H1b' . ≪ / RTI > Thus, the first left contact 150a, the first right contact 150b ', and the second contact 160a can form an L-shaped jumper.

In one embodiment, the height H1b 'of the first right contact 150b' may be greater than the height H1a of the first left contact 150a. In another embodiment, the height H1a of the first left contact 150a may be greater than the height H1b 'of the first right contact 150b'. As described above, according to the embodiments, the height H1a of the first left contact 150a and the height H1b 'of the first right contact 150b' can be variously changed.

3 is a cross-sectional view taken along a line III-III 'of an example 100a of a semiconductor device having the layout of FIG.

Referring to FIG. 3, the semiconductor device 100a may include a substrate 110, a second conductive line 140b, first contacts 150a and 150b, and a second contact 160a. Although not shown, a voltage terminal or the like for providing a power supply voltage or a ground voltage may be further disposed on the second contact 160a, for example.

The substrate 110 may be a semiconductor substrate, for example, a silicon substrate, a silicon-on-insulator (SOI), a silicon-on-sapphire, Silicon-germanium, and gallium-arsenide. For example, the substrate 110 may be a P-type substrate. Further, although not shown, the substrate 110 may include an active region doped with an impurity.

The second conductive line 140b may be disposed on the substrate 110. [ In one embodiment, the second conductive line 140b may be used as a gate electrode, in which case a gate insulating layer may be further disposed between the second conductive line 140b and the active region in the substrate 110 .

The first contacts 150a, 150b may be disposed on the substrate 110. As such, the first contacts 150a, 150b may provide, for example, a power supply voltage or a ground voltage to the active region within the substrate 110. [ In this embodiment, the first contacts 150a and 150b may be disposed on both sides of the second conductive line 140b, respectively. In this embodiment, the upper levels of the first contacts 150a, 150b and the second conductive line 140b may be substantially identical to each other.

The second contact 160a may be disposed on the second conductive line 140b and the first contacts 150a and 150b and electrically connected to the second conductive line 140b and the first contacts 150a and 150b, . Thus, the second conductive line 140b, the first contacts 150a and 150b, and the second contact 160a may form one node.

4 is a layout for a portion of an integrated circuit 100A 'that is substantially equivalent to the embodiment of FIG.

Referring to FIG. 4, the integrated circuit 100A 'may include first and third conductive lines 140a and 140c and first contacts 150a and 150b. Here, the first contacts 150a and 150b may be connected to the same metal line disposed on the upper side. In other embodiments, the integrated circuit 100A 'may include only one of the first contacts 150a, 150b.

The first contacts 150a. 150b and the second contact 160a included in the layout illustrated in Fig. 1 form an H-shaped jumper, so that the actually implemented integrated circuit 100A has the layout shown in Fig. 4 May be substantially the same as the corresponding integrated circuit 100A '. In other words, the second conductive line 140b may be skipped due to the j-shaped jumper included in the layout illustrated in Fig.

Likewise, the first contacts 150a and 150b 'included in the layout illustrated in FIG. 2 and the second contact 160a form an L-shaped jumper, so that the actually implemented integrated circuit 100B is shown in FIG. May be substantially the same as the integrated circuit 100A 'corresponding to the layout. In other words, the second conductive line 140b may be skipped due to the L-shaped jumper included in the layout illustrated in Fig.

5 is a layout for a portion of an integrated circuit 100C in accordance with another embodiment of the present disclosure.

Referring to Fig. 5, the integrated circuit 100C may include at least one cell defined by a cell boundary indicated by a bold solid line. The cell may include first through fourth conductive lines 140e through 140h, first contacts 150c and 150d, and second contact 160b.

The first to fourth conductive lines 140e to 140h may extend in a first direction (e.g., the Y direction). In addition, the first to fourth conductive lines 140e to 140h may be arranged parallel to each other along a second direction (e.g., the X direction) substantially perpendicular to the first direction. At this time, the first to fourth conductive lines 140e to 140h may be made of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, or the like.

In one embodiment, the first through fourth conductive lines 140e through 140h may correspond to the gate electrodes. However, the present invention is not limited thereto, and the first to fourth conductive lines 140e to 140h may be traces having any conductivity or the like. 5, the integrated circuit 100C is shown as including the first to fourth conductive lines 140e to 140h, but this is merely an example, and the integrated circuit 100C may be extended in the first direction And at least five conductive lines disposed parallel to each other along the second direction.

The first contacts 150c and 150d may extend in a first direction. Further, the first contacts 150c and 150d may be arranged parallel to each other along a second direction substantially perpendicular to the first direction. At this time, the first contacts 150c and 150d may be made of any material having electrical conductivity, and may include, for example, polysilicon, metal, metal alloy, or the like. Thus, the first contacts 150c and 150d can provide a power supply voltage or a ground voltage in a region disposed under the spaces between the first to fourth conductive lines 140e to 140h, for example.

The first contacts 150c and 150d are connected to the first left contact 150c disposed on the left side of the second conductive line 140f and the first left side contact 150c disposed on the right side of the third conductive line 140g, Contact 150d. In other words, the first left contact 150c is disposed between the first conductive line 140e and the second conductive line 140f, the first right contact 150d is disposed between the third conductive line 140g and the fourth conductive line 140f, Line 140h. ≪ / RTI >

The length W2a along the second direction of the first left contact 150c in this embodiment is smaller than the space S2 between the first conductive line 140e and the second conductive line 140f . Similarly, the length W2b along the second direction of the first right-side contact 150d may be smaller than the space S2 between the third conductive line 140g and the fourth conductive line 140h. In one embodiment, the width W2a of the first left contact 150c and the width W2b of the first right contact 150d may be substantially equal to each other. However, the present invention is not limited to this. In another embodiment, the width W2a of the first left contact 150c and the width W2b of the first right contact 150d may be different from each other.

The second contact 160b is disposed on the second and third conductive lines 140f and 140g and the first contacts 150c and 150d and the second and third conductive lines 140f and 140g and And may be electrically connected to the first contacts 150c and 150d to form one node. The second contact 160b may also extend in the second direction so that it is disposed in a direction across the second and third conductive lines 140f and 140g and the first contacts 150c and 150d . At this time, the second contact 160b may be made of any material having electrical conductivity, and may include, for example, polysilicon, metal, metal alloy, or the like. The second contact 160b may thereby provide the same power supply voltage or ground voltage to the second and third conductive lines 140f and 140g and the first contacts 150c and 150d, for example.

The length W2c along the second direction of the second contact 160b is larger than the distance D2a between the first left contact 150c and the first right contact 150d, May be less than the distance D2b between the first conductive line 140e and the fourth conductive line 140h. As a result, the second contact 160b can be electrically connected to the second and third conductive lines 140f and 140g, the first left contact 150c and the first right contact 150d, and the first and fourth And may not be electrically connected to the conductive lines 140e and 140h.

In the present embodiment, the length along the first direction of the first left contact 150c, that is, the height H2a and the length along the first direction of the first right contact 150d, i.e., the height H2b, . ≪ / RTI > Thus, the first left contact 150c, the first right contact 150d, and the second contact 160b can form an H-shaped jumper. Here, the jumper is a conductor having a relatively short length for connecting any two points or two terminals in the integrated circuit 100C.

Although not shown, in another embodiment, the length along the first direction of the first left contact 150c, that is, the height H2a and the length along the first direction of the first right contact 150d, that is, the height H2b may differ from one another. Thus, the first left contact 150c, the first right contact 150d, and the second contact 160b can form an L-shaped jumper.

As described above, according to this embodiment, the second and third conductive lines 140f and 140g, the first contacts 150c and 150d, and the second contact 160b are electrically shorted to form one node . Accordingly, the integrated circuit 100C implemented according to the layout illustrated in Fig. 5 may have a configuration in which the second and third conductive lines 140f and 140g are skipped. Therefore, the j-shaped jumper according to the present embodiment can be referred to as a skip device.

FIG. 6 is a cross-sectional view taken along the line VI-VI 'of an example 100c of a semiconductor device having the layout of FIG.

6, the semiconductor device 100c includes a substrate 110, second and third conductive lines 140f and 140g, first contacts 150c and 150d, and a second contact 160b. . Although not shown, a voltage terminal or the like for providing a power supply voltage or a ground voltage may be further disposed on the second contact 160b, for example.

The substrate 110 may be a semiconductor substrate, for example, the semiconductor substrate may comprise any one of silicon, silicon-on-insulator, silicon-on-sapphire, germanium, silicon-germanium and gallium arsenide. For example, the substrate 110 may be a P-type substrate. Further, although not shown, the substrate 110 may include an active region doped with an impurity.

The second and third conductive lines 140f and 140g may be disposed on the substrate 110. In one embodiment, the second and third conductive lines 140f and 140g may be used as gate electrodes, in which case the second and third conductive lines 140f and 140g and the active A gate insulating layer may be further disposed between the regions.

The first contacts 150c and 150d may be disposed on the substrate 110. As such, the first contacts 150c and 150d may provide, for example, a power supply voltage or a ground voltage to the active area within the substrate 110. [ In this embodiment, the first contacts 150c and 150d may be disposed on the left side of the second conductive line 140f and on the right side of the third conductive line 140g, respectively. In this embodiment, the upper levels of the first contacts 150c and 150d and the second and third conductive lines 140f and 140g may be substantially identical to each other.

The second contact 160b may be disposed on the second and third conductive lines 140f and 140g and the first contacts 150c and 150d and may be disposed on the second and third conductive lines 140f and first And may be electrically connected to the contacts 150c and 150d. Thus, the second and third conductive lines 140f and 140g, the first contacts 150c and 150d, and the second contact 160b can form one node.

Figure 7 is a layout for a portion of an integrated circuit 100D in accordance with another embodiment of the present disclosure.

Referring to FIG. 7, the integrated circuit 100D may include at least one cell defined by a cell boundary indicated by a bold solid line. The cell may include first through fourth conductive lines 140e through 140h, first contacts 150c, 150d, and 150e, and a second contact 160c. The integrated circuit 100D according to the present embodiment is an alternative embodiment to the integrated circuit 100C illustrated in Fig. 5, and the contents described above with reference to Fig. 5 can also be applied to this embodiment. Therefore, redundant description will be omitted below.

The integrated circuit 100D according to this embodiment may further include a first center contact 150e as compared to the integrated circuit 100C illustrated in Fig. The first center contact 150e may be disposed between the second conductive line 140f and the third conductive line 140g. In this embodiment, the second contact 160c may be electrically connected to the second and third conductive lines 140f and 140g and the first contacts 150c, 150d and 150e to form one node .

FIG. 8 is a cross-sectional view taken along the line VIII-VIII 'of an example of the semiconductor device 100d having the layout of FIG.

8, the semiconductor device 100d includes a substrate 110, second and third conductive lines 140f and 140g, first contacts 150c, 150d and 150e, and a second contact 160c. . The semiconductor device 100d according to the present embodiment is an alternative embodiment to the semiconductor device 100c exemplified in Fig. 6, and the contents described above with reference to Fig. 6 can also be applied to this embodiment. Therefore, redundant description will be omitted.

The first contacts 150c, 150d, 150e may be disposed on the substrate 110. [ Thus, the first contacts 150c, 150d, and 150e can provide, for example, a power supply voltage or a ground voltage to the active region in the substrate 110. [ In this embodiment, the first center contact 150e may be disposed between the second and third conductive lines 140f and 140g. In this embodiment, the upper levels of the first contacts 150c, 150d, 150e and the second and third conductive lines 140f, 140g may be substantially identical to each other.

The second contact 160c may be disposed on the second and third conductive lines 140f and 140g and the first contacts 150c and 150d and 150e and the second and third conductive lines 140f, 140g and the first contacts 150c, 150d, 150e. Thus, the second and third conductive lines 140f and 140g, the first contacts 150c, 150d and 150e, and the second contact 160b can form one node.

Figure 9 is a layout for a portion of an integrated circuit 100C 'that is substantially equivalent to the embodiment of Figure 5.

Referring to FIG. 9, the integrated circuit 100C 'may include first and fourth conductive lines 140e and 140h and first contacts 150c and 150d. Here, the first contacts 150c and 150d may be connected to the same metal line disposed on the upper side. In another embodiment, the integrated circuit 100C 'may include only one of the first contacts 150c and 150d.

The first contacts 150c and 150d and the second contact 160b included in the layout illustrated in Fig. 5 form the j-shaped jumper, so that the actually implemented integrated circuit 100C is not limited to the layout illustrated in Fig. 9 May be substantially the same as the corresponding integrated circuit 100C '. In other words, due to the j-shaped jumper included in the layout illustrated in Fig. 5, the second and third conductive lines 140f and 140g can be skipped.

Similarly, the first contacts 150c, 150d, and 150e included in the layout illustrated in FIG. 7 and the second contact 160c form a jumper, so that the actually implemented integrated circuit 100D includes the layout illustrated in FIG. 9 May be substantially the same as the integrated circuit 100C 'corresponding to the integrated circuit 100C'. In other words, due to the jumper included in the layout illustrated in FIG. 7, the second and third conductive lines 140f and 140g may be skipped.

10 is a layout for an integrated circuit 200 according to another embodiment of the present disclosure.

Referring to FIG. 10, the integrated circuit 200 may include at least one cell defined by a cell boundary indicated by a thick solid line. Specifically, FIG. 10 shows an example of a standard cell included in the integrated circuit 200. The standard cell includes first and second active regions 220a and 220b, a plurality of pins 230, a plurality of conductive lines 240, first contacts 250a through 250d, a second contact 260, And may include a cut region 270. In this embodiment, the plurality of fins 230 includes first through sixth pins 230a through 230f, and the plurality of conductive lines 240 includes first through third conductive lines 240a through 240c But the present invention is not limited thereto. In another embodiment, the number of pins included in the plurality of pins 230 and the number of conductive lines included in the plurality of conductive lines 240 may be variously changed.

The first active region 220a may be an NMOS-confined region, for example, an area where the first to third fins 230a to 230c are disposed. For example, the first active region 220a may be any region within the P-type substrate. The second active region 220b is an area where the fourth to sixth pins 230d to 230f are disposed, for example, a PMOS confined layer. For example, the second active region 220b may be an N well region. Although not shown, an element isolation region may be disposed between the first active region 220a and the second active region 220b.

The first to sixth pins 230a to 230f may be arranged parallel to each other along a first direction (e.g., the Y direction) and may be arranged in a second direction (e.g., X Direction). In this embodiment, the first to sixth pins 230a to 230f may be active fins. The overall channel width of the pin transistor implemented with these pins may increase in proportion to the number of active pins, thereby increasing the amount of current flowing through the pin transistor. Although not shown, the integrated circuit 200 may further include a dummy fin disposed on the element isolation region.

According to the present embodiment, the length, i.e., the width, of each of the first to sixth pins 230a to 230f in the first direction in the layout for the integrated circuit 200 can be determined to be the same. At this time, the width of each of the first to sixth pins 230a to 230f represents the width shown in the two-dimensional layout shown in Fig. 10 is a two-dimensional layout, the height information of the first to sixth pins 230a to 230f is not displayed.

The first through third conductive lines 240a through 240c may extend in a first direction (e.g., the Y direction). In addition, the first to third conductive lines 240a to 240c may be arranged parallel to each other along a second direction (e.g., the X direction) substantially perpendicular to the first direction. At this time, the first to third conductive lines 240a to 240c may be made of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, or the like. In this embodiment, the first to third conductive lines 240a to 240c may correspond to the gate electrodes.

The first contacts 250a through 250d may extend in a first direction (e.g., the Y direction). Also, the first contacts 250a to 250d may be arranged parallel to each other along a second direction (e.g., the X direction) substantially perpendicular to the first direction. At this time, the first contacts 250a to 250d may be made of any material having electrical conductivity, and may include, for example, polysilicon, metal, metal alloy, or the like.

In this embodiment, the first contacts 250a-250d are connected to the first lower contacts 250a and 250b on the first active area 220a and the first upper contacts 250c and 250d on the second active area 220b. 250d. The first lower contacts 250a, 250b may be contacts for the first active region 220a, e.g., source / drain contacts. Thus, the first lower contacts 250a and 250b may provide a power supply voltage or a ground voltage to the first active region 220a, for example. The first top contacts 250c, 250d may be contacts for the second active region 220b, e.g., source / drain contacts. Hereby, the first top contacts 250c and 250d may provide a power supply voltage or a ground voltage, for example, to the second active region 220b.

In this embodiment, the first lower contacts 250a and 250b may be disposed on both sides of the second conductive line 240b, respectively. The first lower contacts 250a and 250b are electrically connected to the first lower left contact 250a disposed on the left side of the second conductive line 240b and the first lower left contact 250b disposed on the right side of the second conductive line 240b. And a right contact 250b. In other words, the first lower left contact 250a is disposed between the first conductive line 240a and the second conductive line 240b, the first lower right contact 250b is disposed between the second conductive line 240b and the second conductive line 240b, 3 conductive line 240c.

The second contact 260 is disposed on the second conductive line 240b and the first lower contacts 250a and 250b and includes a second conductive line 240b and first lower contacts 250a and 250b, And may be electrically connected to form one node. Also, the second contact 260 may extend in a second direction, thereby being disposed in a direction across the second conductive line 240b and the first lower contacts 250a, 250b. At this time, the second contact 260 may be made of any material having electrical conductivity, and may include, for example, polysilicon, a metal, a metal alloy, or the like. The second contact 260 may thereby provide the same power voltage or ground voltage to the second conductive line 240b and the first lower contacts 250a and 250b, for example.

In the present embodiment, the first to third conductive lines 240a to 240c, the first lower contacts 250a and 250b, and the second contact 260 disposed on the first active region 220a are formed in the same manner as in FIG. 1 May be substantially the same as the integrated circuit 100A illustrated in Fig. Therefore, the above description with reference to FIG. 1 can also be applied to this embodiment, and thus a duplicated description will be omitted.

As described above, according to this embodiment, the second conductive line 240b, the first lower contacts 250a and 250b, and the second contact 260 are electrically short-circuited on the first active region 220a, Can be formed. Thus, the integrated circuit 200 implemented according to the layout illustrated in FIG. 10 may be configured such that the second conductive line 240b is skipped in the first active area 220a and the second conductive line 240b is skipped in the second active area 220b, 240b are not skipped. Thus, the integrated circuit 200 may include two transistors, for example, two NMOS pin transistors, on the first active region 220a, three transistors on the second active region 220b, For example, three PMOS pin transistors.

Although FIG. 10 illustrates an embodiment in which the second contact 260 is disposed on the first active region 220a, the present invention is not limited thereto. In another embodiment, the second contact 260 may be disposed on both the first and second active regions 220a, 220b. Accordingly, the number of transistors disposed on the first active region 220a may be equal to the number of transistors disposed on the second active region 220b. In another embodiment, the second contact 260 may be disposed only on the second active region 220b. Accordingly, the number of transistors disposed on the first active region 220a may be greater than the number of transistors disposed on the second active region 220b.

11 is a layout for an integrated circuit 200 'that is substantially equivalent to the embodiment of FIG.

Referring to FIG. 11, the integrated circuit 200 'may include first and third conductive lines 240a through 240c and first contacts 250a through 250d. Here, the first lower contacts 250a and 250b on the first active region 220a may be connected to the same metal line disposed on the upper portion. In other embodiments, the integrated circuit 200 'may include only one of the first lower contacts 250a, 250b.

The first lower contacts 250a and 250b and the second contact 260 included in the layout illustrated in Figure 10 form an H-shaped jumper so that the actual implemented integrated circuit 200 has the layout illustrated in Figure 11 May be substantially the same as the integrated circuit 200 'corresponding to FIG. In other words, the second conductive line 240b on the first active area 220a may be skipped due to the j-shaped jumper included in the layout illustrated in Fig. As such, the integrated circuit 200 may include two NMOS pin transistors on the first active region 220a and three PMOS pin transistors on the second active region 220b.

12 is a perspective view showing an example of a semiconductor device 200A having the layout of FIG. 13 is a sectional view taken along the line XII-XII 'in Fig.

12 and 13, the semiconductor device 200A may be a bulk type pin transistor. The semiconductor device 200A includes a substrate 210, a first insulating layer 233, a second insulating layer 236, first to third pins 230a to 230c, and a first conductive line Quot;) < / RTI > 240a.

The substrate 210 can be a semiconductor substrate, for example, the semiconductor substrate can include any one of silicon, silicon-on-insulator, silicon-on-sapphire, germanium, silicon-germanium and gallium arsenide. Here, the substrate 210 may be a P-type substrate and may be used as the first active region 220a.

The first to third pins 230a to 230c may be disposed to be connected to the substrate 210. In one embodiment, the first to third fins 230a to 230c may be active regions doped with n + or p + portions protruding from the substrate 210 to the vertical portion.

The first and second insulating layers 233 and 236 may include an insulating material. For example, the insulating material may include an oxide layer, a nitride layer, or an oxynitride layer. The first insulating layer 233 may be disposed on the first to third fins 230a to 230c. The first insulating layer 233 is disposed between the first to third fins 230a to 230c and the gate electrode 240a, thereby being used as a gate insulating film. The second insulating layer 236 may be disposed to have a predetermined height in a space between the first to third fins 230a to 230c. The second insulating layer 236 is disposed between the first to third fins 230a to 230c, so that it can be used as a device isolation film.

The gate electrode 240a may be disposed on top of the first and second insulating layers 233 and 236. Thus, the gate electrode 240a may have a structure surrounding the first to third pins 230a to 230c, the first insulating layer 233, and the second insulating layer 236. In other words, the first to third fins 230a to 230c may have a structure disposed inside the gate electrode 240a. The gate electrode 240a may include a metal material such as W, Ta, etc., a nitride thereof, a silicide thereof, a doped polysilicon, or the like, and may be formed using a deposition process.

14 is a perspective view showing another example (200B) of a semiconductor element having the layout of Fig. 15 is a cross-sectional view taken along line XIV-XIV 'of Fig.

14 and 15, the semiconductor device 200B may be an SOI type pin transistor. The semiconductor device 200B includes a substrate 210 ', a first insulating layer 215, a second insulating layer 233', first to third pins 230a 'to 230c', and a first conductive line Quot; gate electrode ") 240a '. Since the semiconductor device 200B according to the present embodiment is a modified embodiment of the semiconductor device 200A shown in Figs. 12 and 13, the following description will focus on the difference from the semiconductor device 200A, The description of which will be omitted.

The first insulating layer 215 may be disposed on the substrate 210 '. The second insulating layer 233 'is disposed between the first to third fins 230a' to 230c 'and the gate electrode 240a', so that the second insulating layer 233 'can be used as a gate insulating film. The first to third fins 230a 'to 230c' may be a semiconductor material, for example, silicon or doped silicon.

The gate electrode 240a 'may be disposed on the second insulating layer 233'. Thus, the gate electrode 240a 'may have a structure surrounding the first to third pins 230a' to 230c 'and the second insulating layer 233'. In other words, the first and second fins 230a 'to 230c' may have a structure disposed inside the gate electrode 240a '.

16 is a cross-sectional view taken along line XVI-XVI 'of an example of a semiconductor device 200a having the layout of FIG.

Referring to FIG. 16, the semiconductor device 200a may include a second fin 230b, a second conductive line 240b, first lower contacts 250a and 250b, and a second contact 260. Referring to FIG. Although not shown, a voltage terminal or the like for providing a power supply voltage or a ground voltage may be further disposed on the second contact 260, for example.

And the second conductive line 240b may be disposed on the second fin 230b. In this embodiment, the second conductive line 240b may be used as a gate electrode, and a gate insulating layer may be further disposed between the second conductive line 240b and the second fin 230b.

The first lower contacts 250a and 250b may be disposed on the second fin 230b. Thus, the first lower contacts 250a and 250b may provide a power supply voltage or a ground voltage to the second fin 230b, for example. In this embodiment, the first lower contacts 250a and 250b may be disposed on both sides of the second conductive line 240b, respectively. In this embodiment, the upper levels of the first lower contacts 250a, 250b and the second conductive line 240b may be substantially the same as each other.

The second contact 260 can be disposed on the second conductive line 240b and the first lower contacts 250a and 250b and the second conductive line 240b and the first lower contacts 250a and 250b, As shown in FIG. Thus, the second conductive line 240b, the first lower contacts 250a and 250b, and the second contact 260 may form one node.

17 is a layout for an integrated circuit 300 according to another embodiment of the present disclosure.

Referring to FIG. 17, the integrated circuit 300 may include at least one cell defined by a cell boundary indicated by a thick solid line. Specifically, FIG. 17 shows an example of a standard cell included in the integrated circuit 300. The standard cell includes first and second active regions 220a and 220b, a plurality of fins 230, a plurality of conductive lines 240, first contacts 250a through 250d, a second contact 260, A cut region 270 and third contacts 280a through 280c. The integrated circuit 300 according to the present embodiment is an alternative embodiment to the integrated circuit 200 illustrated in FIG. 10, and the description described above with reference to FIG. 10 can also be applied to this embodiment. Therefore, redundant description will be omitted.

Compared to the integrated circuit 200 illustrated in FIG. 10, the integrated circuit 300 according to the present embodiment may further include third contacts 280a through 280c. The third contact 280a may be disposed on the first conductive line 240a and may be electrically connected to the first conductive line 240a. The third contact 280c may be disposed on the third conductive line 240c and electrically connected to the third conductive line 240c.

The third contact 280b may be disposed on the second conductive line 240b and may be electrically connected to the second conductive line 240b. The third contact 280b is electrically connected only to the second conductive line 240b on the second active region 220b and the third contact line 280b is electrically connected to the second conductive line 240b on the second active region 220b, And is not electrically connected to the second conductive line 240b on the first active region 220b.

According to the present embodiment, the second conductive line 240b, the first lower contacts 250a and 250b, and the second contact 260 are electrically short-circuited on the first active region 220a to form one node . Accordingly, the integrated circuit 300 implemented in accordance with the layout illustrated in FIG. 17 is formed by skipping the second conductive line 240b in the first active area 220a and the second conductive line 240b in the second active area 220b 240b are not skipped. Thus, the integrated circuit 300 may include two transistors, for example, two NMOS pin transistors, on the first active region 220a, three transistors on the second active region 220b, For example, three PMOS pin transistors.

Although FIG. 17 illustrates an embodiment in which the second contact 260 is disposed on the first active region 220a, the present invention is not limited thereto. In another embodiment, the second contact 260 may be disposed on both the first and second active regions 220a, 220b. Accordingly, the number of transistors disposed on the first active region 220a may be equal to the number of transistors disposed on the second active region 220b. In another embodiment, the second contact 260 may be disposed only on the second active region 220b. Accordingly, the number of transistors disposed on the first active region 220a may be greater than the number of transistors disposed on the second active region 220b.

FIG. 18 is a layout for an integrated circuit 300 'substantially equivalent to the embodiment of FIG.

18, the integrated circuit 300 'may include first and third conductive lines 240a through 240c, first contacts 250a through 250d, and third contacts 380a through 380c. have. Here, the first lower contacts 250a and 250b on the first active region 220a may be connected to the same metal line disposed on the upper portion. In other embodiments, the integrated circuit 300 'may include only one of the first lower contacts 250a, 250b.

The first lower contacts 250a and 250b and the second contact 260 included in the layout illustrated in Figure 17 form an H-shaped jumper so that the actual implemented integrated circuit 300 has the layout illustrated in Figure 18 May be substantially the same as the integrated circuit 300 'corresponding to FIG. In other words, the second conductive line 240b on the first active region 220a may be skipped due to the j-shaped jumper included in the layout illustrated in Fig. As such, the integrated circuit 200 may include two NMOS pin transistors on the first active region 220a and three PMOS pin transistors on the second active region 220b.

19 is a circuit diagram showing the integrated circuit 300 of FIG.

17 and 19, the integrated circuit 300 may include first through third PMOS pin transistors PM1 through PM3 and first and second NMOS pin transistors NM1 and NM2. The first to third PMOS pin transistors PM1 to PM3 are formed on the second active region 220b and the first and second NMOS pin transistors NM1 and NM2 are formed on the first active region 220a As shown in FIG.

The gates of the first PMOS pin transistor PM1 and the first NMOS pin transistor NM1 are commonly connected to the node A, and the node A can correspond to the third contact 380a. Further, the gate of the second PMOS pin transistor PM2 may be connected to the node B, and the node B may correspond to the third contact 380b. In addition, the gates of the third PMOS pin transistor PM3 and the second NMOS pin transistor NM2 may be commonly connected to the node C, and the node C may correspond to the third contact 380c.

Specifically, the gate of the first PMOS pin transistor PM1 is connected to the third contact 380a, the drain of the first PMOS pin transistor PM1 may be connected to the first node region NA1, Area NA1 may correspond to first left upper contact 250c. The gate of the second PMOS transistor PM2 may be connected to the third contact 380b and the drain of the second PMOS pin transistor PM2 may be connected to the second node region NA2 and the drain of the second PMOS transistor PM2 may be connected to the second node region NA2, May correspond to the first right upper contact 250d. And the gate of the third PMOS transistor PM3 may be connected to the third contact 380c.

The gate of the first NMOS pin transistor NM1 may be coupled to the third contact 380a and the gate of the second NMOS pin transistor NM2 may be coupled to the third contact 380c. The first and second NMOS pin transistors NM1 and NM2 may be connected to each other in the third node region NA3 and the third node region NA3 may be connected to the first lower contacts 250a and 250b and / And may correspond to a jumper formed in the second contact 260.

20 is a circuit diagram showing the third node region NA3 of FIG. 19 in more detail.

17 and 20, a first node N1 between the second pin 230b and the first lower left contact 250a, a first node N1 between the second pin 230b and the first lower right contact 250b, The third node N3 between the second node N2 and the second contact 260 and the second conductive line 240b are connected together to form one node region or the third node region NA3 .

21 is a layout for an integrated circuit 400 according to another embodiment of the present disclosure.

Referring to FIG. 21, the integrated circuit 400 may include at least one cell defined by a cell boundary indicated by a thick solid line. Specifically, FIG. 21 shows an example of a standard cell included in the integrated circuit 400. The standard cell includes first to tenth pins 430a to 430j, a plurality of gate electrodes 440b, 440c and 440d, a plurality of dummy gate electrodes 440a and 440e, a plurality of source / drain contacts 450a, 450b, a second contact 460, a cutout region 470, two input terminals 480, two input contacts 485, and an output terminal 490.

In this embodiment, the first, fifth, sixth, and tenth pins 430a, 430e, 430f, and 430j are dummy pins, and the second through fourth, seventh through ninth pins 430b through 430d, 430g, 430i may be an active pin. Specifically, the second to fourth pins 430b to 430d may be disposed in the first active region 420a, and the seventh to ninth pins 430g to 430i may be disposed in the second active region 420b . The first pin 430a is disposed in the first device isolation region 425a and the fifth and sixth pins 430e and 430f are disposed in the second device isolation region 425b. And may be disposed in the third element isolation region 425c.

First, the first to tenth pins 430a to 430j may be formed on a semiconductor substrate (not shown) through a single process. Gate electrodes including a plurality of gate electrodes 440b, 440c and 440d and a plurality of dummy gate electrodes 440a and 440e and a plurality of source / drain contacts 450a and 450b may be formed. have. A second contact 460 may then be formed over the gate electrode 440c and the source / drain contacts 450a and 450b. Then, two input terminals 480 and an output terminal 490 may be formed.

The first region R1 is similar to the layout shown in Fig. 1, and the embodiments described above with reference to Figs. 1 to 9 can be applied. The second region R2 is similar to the layout shown in Fig. 10, and the embodiments described above with reference to Figs. 10 to 20 can be applied. In the present embodiment, the second to fourth pins 430b to 430d constitute an NMOS transistor, and the seventh to ninth pins 430g to 430i may constitute a PMOS transistor.

Although FIG. 21 illustrates an embodiment in which the second contact 460 is disposed on the first active region 420a, the present invention is not limited thereto. In another embodiment, the second contact 460 may be disposed on both the first and second active regions 420a and 420b. Accordingly, the number of transistors disposed on the first active region 420a may be equal to the number of transistors disposed on the second active region 420b. In another embodiment, the second contact 460 may be disposed only on the second active region 420b. Accordingly, the number of transistors disposed on the first active region 220a may be greater than the number of transistors disposed on the second active region 220b.

Figure 22 is a layout for an integrated circuit 400 'that is substantially equivalent to the embodiment of Figure 21.

22, the integrated circuit 400 'includes first to 10th pins 430a to 430j, a plurality of gate electrodes 440b, 440c and 440d, a plurality of dummy gate electrodes 440a and 440e, And may include a plurality of source / drain contacts 450a and 450b, a second contact 460, two input terminals 480, two input contacts 485, and an output terminal 490. Here, the source / drain contacts 450a and 450b on the first active region 420a may be connected to the same metal line disposed on the top. In another embodiment, the integrated circuit 400 'may include only one of the source / drain contacts 450a and 450b on the first active region 420a.

The source / drain contacts 450a. 450b and the second contact 460 included in the layout illustrated in Fig. 21 form an H-shaped jumper, so that the actual implemented integrated circuit 400 has the layout May be substantially the same as the integrated circuit 400 'corresponding to FIG. In other words, the gate electrode 440c on the first active region 420a in Fig. 22 can be skipped due to the j-shaped jumper included in the layout illustrated in Fig. As such, the integrated circuit 400, 400 'may include two NMOS pin transistors on the first active region 420a and three PMOS pin transistors on the second active region 420b .

23 is a block diagram illustrating a storage medium 500 in accordance with one embodiment of the present disclosure.

23, storage medium 500 is a computer-readable storage medium and may include any storage medium that can be read by a computer while being used to provide instructions and / or data to the computer . For example, the computer-readable storage medium 500 may be a magnetic or optical medium such as a disk, a tape, a CD-ROM, a DVD-ROM, a CD-R, a CD-RW, a DVD- Volatile or nonvolatile memory such as ROM, flash memory, etc., nonvolatile memory accessible through a USB interface, and microelectromechanical systems (MEMS). The computer readable storage medium can be embedded in a computer, integrated into a computer, or coupled to a computer via a communication medium such as a network and / or a wireless link.

As shown in FIG. 23, a computer-readable storage medium 500 may include a location and routing program 510, a library 520, an analysis program 530, and a data structure 540. The location and routing program 510 may include a plurality of instructions to perform a method of using a standard cell library or a method of designing an integrated circuit according to an exemplary embodiment of the present invention. For example, the computer-readable storage medium 500 may store a location and routing program 510 that includes any instructions that perform some or all of the flowcharts shown in one or more of the preceding figures . The library 520 may include information on a standard cell that is a unit constituting an integrated circuit.

The analysis program 530 may include a plurality of instructions that perform a method of analyzing an integrated circuit based on data defining the integrated circuit. For example, the computer-readable storage medium 500 may be configured to analyze the timing characteristics of an integrated circuit based on resistance values of vias disposed in a first region (a high resistance region) and a second region (a low resistance region) (Not shown), and the like. The data structure 540 may be obtained by using the standard cell library included in the library 520 or by extracting the marker information from the general standard cell library included in the library 520 or by the analysis program 530 using the timing of the integrated circuit A storage space for managing data generated in the process of analyzing characteristics, and the like.

24 is a block diagram illustrating a memory card 1000 including an integrated circuit according to one embodiment of the present disclosure.

Referring to FIG. 24, the memory card 1000 may be arranged such that the controller 1100 and the memory 1200 exchange electrical signals. For example, when the controller 1100 issues a command, the memory 1200 can transmit data.

The controller 1100 and the memory 1200 may include an integrated circuit according to embodiments of the present invention. Specifically, in at least one semiconductor element of the plurality of semiconductor elements included in the controller 1100 and the memory 1200, the pin transistor included in the semiconductor element or the semiconductor element is in a first direction (e.g., the Y direction) At least two first contacts extending in a first direction, a second contact extending in a second direction (e.g., X direction) perpendicular to the first direction, and at least one conductive line extending in the first direction, Thereby forming a single node, so that at least one conductive line is skipped.

The memory card 1000 may include various types of cards such as a memory stick card, a smart media card (SM), a secure digital card (SD), a mini-secure digital card a mini-secure digital card (mini SD), and a multimedia card (MMC).

25 is a block diagram illustrating a computing system 2000 that includes an integrated circuit in accordance with one embodiment of the present disclosure.

25, a computing system 2000 may include a processor 2100, a memory device 2200, a storage device 2300, a power supply 2400, and an input / output device 2500. 25, the computing system 2000 may further include ports capable of communicating with, or communicating with, video cards, sound cards, memory cards, USB devices, and the like .

As described above, the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the input / output device 2500 included in the computing system 2000 can be implemented in the embodiment according to the technical idea of the present invention Lt; RTI ID = 0.0 > IC < / RTI > Specifically, in at least one of the plurality of semiconductor elements included in the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the input / output device 2500, The pin transistor included in the semiconductor device includes at least two first contacts extending in a first direction (e.g., Y direction), a second direction extending in a second direction (e.g., X direction) perpendicular to the first direction The at least one conductive line may be skipped by electrically connecting the at least one conductive line extending in the first direction and the second contact and the at least one conductive line by forming one node.

Processor 2100 may perform certain calculations or tasks. According to an embodiment, the processor 2100 may be a micro-processor, a central processing unit (CPU). The processor 2100 is coupled to the memory device 2200, the storage device 2300, and the input / output device 2500 via a bus 2600, such as an address bus, a control bus, and a data bus, Lt; / RTI > In accordance with an embodiment, the processor 2100 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 2200 may store data necessary for operation of the computing system 2000. For example, the memory device 2200 may be implemented as a DRAM, a mobile DRAM, an SRAM, a PRAM, an FRAM, an RRAM, and / or an MRAM. have. The storage device 2300 may include a solid state drive, a hard disk drive, a CD-ROM, and the like.

The input / output device 2500 may include input means such as a keyboard, a keypad, a mouse, etc., and output means such as a printer, a display, and the like. The power supply 2400 may supply the operating voltage required for operation of the computing system 2000.

The integrated circuit according to the embodiments of the present invention described above can be implemented in various types of packages. For example, at least some configurations of an integrated circuit may be implemented using a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in- , Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package Package (WSP) or the like.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10, 20, 30: Protection element
100, 100 ', 100a, 100b, 100c:

Claims (20)

An integrated circuit comprising at least one cell, the at least one cell comprising:
A plurality of conductive lines extending in a first direction and arranged parallel to each other along a second direction perpendicular to the first direction;
First contacts comprising a first left contact between a first one of the plurality of conductive lines and a second one of the plurality of conductive lines; And
A second contact disposed over the second conductive line and the first contacts and electrically connected to the second conductive line and the first contacts and electrically insulated from the first conductive line,
Wherein the second contact, the second conductive line, and the first contacts form one node. The method according to claim 1,
Wherein the first contacts extend in the first direction, and the second contacts extend in the second direction. The method according to claim 1,
And wherein the second contact is disposed in a direction perpendicular to the first contacts. The method according to claim 1,
Wherein the at least one cell further comprises first and second active regions having different conductivity types,
And the second contact is disposed on at least one of the first active region and the second active region. 5. The method of claim 4,
The plurality of conductive lines corresponding to the plurality of gate electrodes, respectively,
Wherein the number of first transistors formed on the first active region is less than the number of second transistors formed on the second active region. 5. The method of claim 4,
The plurality of conductive lines corresponding to the plurality of gate electrodes, respectively,
Wherein the number of first transistors formed on the first active region is greater than or equal to the number of second transistors formed on the second active region. 5. The method of claim 4,
Wherein the at least one cell further comprises a plurality of fins extending in the second direction on the first and second active areas and disposed parallel to each other along the first direction. 8. The method of claim 7,
The plurality of conductive lines corresponding to the plurality of gate electrodes, respectively,
Wherein the number of first pin transistors formed on the first active region is less than the number of second pin transistors formed on the second active region. 8. The method of claim 7,
The plurality of conductive lines corresponding to the plurality of gate electrodes, respectively,
Wherein the number of first pin transistors formed on the first active region is greater than or equal to the number of second pin transistors formed on the second active region. 5. The method of claim 4,
Further comprising a cutoff region disposed between the first and second active regions for isolating the first conductive line on the second active region from the one node. The method according to claim 1,
The first contacts,
The first left contact disposed on the left side of the first conductive line; And
And a first right-side contact disposed on the right side of the second conductive line. 12. The method of claim 11,
Wherein the second contact is disposed on top of a third one of the first left contact, the first right contact, the second conductive line, and the plurality of conductive lines, the first left contact, The right contact, the second conductive line, and the third conductive line. 13. The method of claim 12,
Wherein the first contacts further comprise a first central contact disposed between the second conductive line and the third conductive line. 14. The method of claim 13,
The second contact is disposed on top of the first left contact, the first right contact, the first center contact, the second conductive line, and the third conductive line, and the first left contact, Contact, the first central contact, the second conductive line, and the third conductive line. The method according to claim 1,
The plurality of conductive lines including the first conductive line, the second conductive line, and the third conductive line disposed adjacent to each other,
Wherein the first contacts include a first left contact disposed between the first conductive line and the second conductive line and a first right contact disposed between the second conductive line and the third conductive line,
The length of the second contact along the second direction is greater than the distance between the first left contact and the first right contact and smaller than the distance between the first conductive line and the third conductive line Integrated circuit. The method according to claim 1,
Wherein a length of each of the first contacts along the second direction is less than a space between two adjacent ones of the plurality of conductive lines. The method according to claim 1,
The lengths of the first contacts along the first direction are equal to each other,
Wherein the first contacts and the second contact form an H-shaped jumper. The method according to claim 1,
The lengths of the first contacts along the first direction are different,
Wherein the first contacts and the second contact form an L-shaped jumper. A substrate having at least a first active region having a first conductivity type;
A plurality of gate electrodes extending in a first direction and arranged parallel to each other along a second direction perpendicular to the first direction, the gate electrodes including at least a first gate electrode and a second gate electrode;
First contacts disposed on both sides of the second gate electrode, one of the plurality of gate electrodes, and connected to the second gate electrode; And
A second contact electrically connected to the second gate electrode and the first contacts in the first active region and electrically insulated from the first gate electrode,
Wherein the second contact, the second gate electrode, and the first contacts form one node in the first active region. An integrated circuit comprising at least one cell, the at least one cell comprising:
A plurality of conductive lines extending in a first direction and arranged parallel to each other along a second direction perpendicular to the first direction;
First contacts disposed on both sides of at least one of the plurality of conductive lines; And
A plurality of conductive lines disposed on the at least one conductive line and the first contacts and electrically connected to the at least one conductive line and the first contacts to electrically connect the at least one conductive line and the first contacts, A second contact forming a node,
Wherein the first contacts have the same length in the first direction so that the first contacts and the second contact form an H-shaped jumper, or the first contacts and the second contact are L-shaped jumper And the second direction has a different length in the first direction.

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