KR101651230B1 - Integrated circuit and standard cell library - Google Patents

Abstract

The present disclosure relates to an integrated circuit comprising at least one standard cell, wherein the at least one standard cell comprises a plurality of pins arranged in parallel to each other along a second direction extending in a first direction and perpendicular to the first direction, A first active region adjacent to the first cell boundary line parallel to the fins and spaced a first distance from the first cell boundary line and a second active region adjacent to the second cell boundary line opposite to the first cell boundary line, And a second active region spaced a second distance from the cell boundary line, wherein the first and second distances are constant regardless of the number of fins on the first and second active regions, respectively.

Description

Integrated circuit and standard cell library < RTI ID = 0.0 >

The technical idea of the present invention relates to an integrated circuit, and more particularly to an integrated circuit including at least one standard cell and a standard cell library for storing information about the at least one standard cell.

Due to the miniaturization of transistors due to the development of semiconductor processing technology, a larger number of transistors are being integrated in semiconductor devices. For example, a system-on-chip (SOC), which refers to an integrated circuit (IC) that integrates all the components of a computer or other electronic system on a single chip, As the performance of an application is improved, a semiconductor device including more components is required.

SUMMARY OF THE INVENTION The object of the technical idea of the present invention is to provide an integrated circuit including at least one standard cell capable of reducing a characteristic change of a device corresponding to a target standard cell according to a layout pattern of an adjacent arranged standard cell, And a standard cell library for storing information on a standard cell of the cell.

The integrated circuit according to the technical idea of the present invention includes at least one standard cell and the at least one standard cell is arranged parallel to each other along a second direction extending in a first direction and perpendicular to the first direction A first active region adjacent to a first cell boundary line parallel to the plurality of pins, the first active region being spaced a first distance from the first cell boundary line, and a second active region disposed opposite the first cell boundary line, And a second active region disposed adjacent the second cell boundary line and spaced a second distance from the second cell boundary line, wherein the first and second distances are located in the first and second active regions Regardless of the number of pins on the board.

Further, an integrated circuit according to the technical concept of the present invention includes at least one standard cell, and the at least one standard cell includes a plurality of standard cells extending parallel to each other along a second direction extending in a first direction and perpendicular to the first direction And a plurality of dummy pins arranged parallel to the plurality of active pins, wherein a first active pin closest to a first cell boundary line of the plurality of active pins comprises: A second active pin closest to the second cell boundary line of the plurality of active pins is arranged to be spaced apart from the second cell boundary line by a second distance, The first and second distances are constant regardless of the number of the active pins.

Also, a standard cell library according to the technical idea of the present invention includes information on a plurality of standard cells and is stored in a computer-readable storage medium, and at least one of the plurality of standard cells extends in a first direction A plurality of fins disposed parallel to each other along a second direction perpendicular to the first direction, a first cell boundary disposed adjacent to the first cell boundary parallel to the plurality of fins and spaced a first distance from the first cell boundary And a second active region adjacent to a second cell boundary opposite the first cell boundary and spaced a second distance from the second cell boundary, wherein the first active region, 2 distances are constant regardless of the number of fins on the first and second active regions, respectively.

According to the technical idea of the present invention, the first and second active regions included in the standard cell can be spaced apart from the first and second cell boundary lines by fixed first and second distances, respectively. Accordingly, even if the number of active pins included in the standard cell is changed or the sizes of the first and second active areas are changed, the third distance between the first active area and the second active area is changed only, And the second distance may not change.

Therefore, even if standard cells having different numbers of active fins are disposed adjacent to each other, the interval between the active areas included in each of the two standard cells, that is, the active-to-active interval, can be kept constant. Therefore, it is possible to reduce the characteristic change of the device corresponding to the target standard cell according to the layout pattern of the adjacent standard cells.

Figures 1A-1C are layouts of standard cells according to one embodiment of the present disclosure.
Figures 2a-2d are layouts for some of the integrated circuits including the standard cells illustrated in Figures 1A-1C.
Figs. 3A to 3C are layouts of standard cells according to a comparative example to the embodiment illustrated in Figs. 1A to 1C.
Figures 4A-4D are layouts for some of the integrated circuits including the standard cells illustrated in Figures 3A-3C.
5 is a graph showing the voltage change of a standard cell according to an active-to-active interval.
6 is a graph showing the current change of a standard cell according to an active-to-active interval.
7 is a graph illustrating leakage current ratios according to the number of dummy pins arranged in active-to-active spacing in an integrated circuit according to one embodiment of the present disclosure;
8 is a graph illustrating the operating speed ratios according to the number of dummy pins arranged in active-to-active spacing in an integrated circuit according to one embodiment of the present disclosure;
Figure 9 is a layout illustrating a portion of an integrated circuit according to one embodiment of the present disclosure.
10 is a perspective view showing an example of a semiconductor element having the layout of FIG.
11 is a cross-sectional view taken along the line XX 'in Fig.
12 is a perspective view showing another example of the semiconductor element having the layout of FIG.
13 is a sectional view taken along the line XII-XII 'in Fig.
14 is a block diagram illustrating a storage medium according to one embodiment of the present disclosure;
15 is a block diagram illustrating a memory card including an integrated circuit according to one embodiment of the present disclosure;
16 is a block diagram illustrating a computing system including an integrated circuit according to one embodiment of the present disclosure;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, the terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

The integrated circuit can be defined as a plurality of cells, and specifically, can be designed using a cell library including characteristic information of a plurality of cells. Here, the cell library may be defined with a cell name, a dimension, a gate width, a pin, a delay characteristic, a leakage current, a threshold voltage, and a function. A typical cell library set includes basic cells such as AND, OR, NOR, and inverters, complex cells such as OAI (OR / AND / INVERTER) and AOI (AND / OR / INVERTER) And may include a storage element such as a simple master-slave flip-flop and a latch.

In the embodiments of the present invention described below, the cell library may be a standard cell library. In the standard cell method, a logic circuit block (or cell) having various functions is prepared in advance, and these cells are arbitrarily combined to design a dedicated large-scale integrated circuit (LSI) adapted to the specification of a customer or user. Cells are pre-designed and verified and registered on a computer. Logic design, layout, and wiring are done using a combination of cells using Computer Aided Design (CAD).

Specifically, when a large-scale integrated circuit is designed / manufactured, if standardized logic circuit blocks (or cells) of a certain size are already stored in the library, a logic circuit block suited to the current design purpose is taken out of the library, And the entire circuit can be made by performing the optimum wiring in which the wiring length is the shortest in the wiring space between the cell and the cell. The more kinds of cells stored in the library, the more flexible the design and the more likely the optimum design of the chip.

As such, an integrated circuit using a standard cell is implemented by arranging cells so as to use standard cells stored in a standard cell library and to minimize wiring between them. Therefore, the development cost can be reduced and the development period can be shortened as compared with the fully custom integrated circuit.

Figures 1A-1C are layouts of standard cells according to one embodiment of the present disclosure.

1A, a standard cell C1 is defined by a cell boundary CB and may include a plurality of pins FIN and first and second active areas AR1 and AR2 . In addition, the standard cell C1 may further include a plurality of conductive lines CL. Although not shown, the standard cell C1 may further include contacts connected to the first and second active areas, respectively, and contacts connected to the plurality of conductive lines CL.

The cell boundary CB is an outline defining the standard cell C1 and the placement and wiring tool can recognize the standard cell C1 using the cell boundary CB. The cell boundary CB is composed of four cell boundary lines. Hereinafter, two cell boundary lines parallel to the plurality of pins FIN among the four cell boundary lines are referred to as a first cell boundary line Line CB1 and the second cell boundary line CB2.

The plurality of pins FIN extend in a first direction (e.g., the X direction) and may be disposed parallel to each other along a second direction (e.g., Y direction) perpendicular to the first direction. The plurality of pins FIN includes first and second active pins AF1 and AF2, at least one first dummy pin DF1, at least one second dummy pin DF2, and at least one third dummy pin DF3).

The first active pins AF1 may be disposed in the first active area AR1 and the second active pins AF2 may be disposed in the second active area AR2. At least one first dummy pin DF1 is disposed between the first cell boundary line CB1 and the first active area AR1 and at least one second dummy pin DF2 is disposed between the second active area AR2 and the first cell boundary line CB1, And at least one third dummy pin DF3 may be disposed between the first active area AR1 and the second active area AR2. At this time, an area where the first and second active areas AR1 and AR2 are not disposed in the standard cell C1 may be referred to as a dummy area or a field area.

In this embodiment, the standard cell C1 includes four first active pins AF1, four second active pins AF2, one first dummy pin DF1, one second dummy pin DF2, And two third dummy pins DF3. However, the present invention is not limited to this, and the number of each of the first and second active fins AF1 and AF2 and the first to third dummy fins DF1, DF2 and DF3 may be variously changed. In another embodiment, the standard cell C1 may not include one of the first through third dummy pins DF1, DF2, DF3.

The first height H1a may be changed in accordance with the number of the first active fins AF1 so that the size of the first active area AR1 along the second direction . Similarly, the height of the second active area AR2, i.e., the second height H2a, can be changed in accordance with the number of the second active fins AF2. In one embodiment, the number of first active pins AF1 and the number of second active pins AF2 may be the same so that the first height H1a and the second height H2a are substantially equal can do. In this embodiment, the first active region AR1 and the second active region AR2 may have different conductivity types.

In this embodiment, the first and second active areas AR1 and AR2 may be disposed close to the cell boundary CB, and specifically, the first active area AR1 may be disposed on the first cell boundary line CB1 , And the second active region AR2 may be disposed adjacent to the second cell boundary line CB2. More specifically, the first active area AR1 may be arranged to be separated from the first cell boundary line CB1 by a first distance D1, and the second active area AR2 may be arranged to be separated from the second cell boundary line CB2 by a second distance D2.

In this embodiment, the first and second distances D1 and D2 may have a constant value regardless of the number of the first and second active fins AF1 and AF2. In other words, the first and second distances D1 and D2 can have constant values regardless of the first and second heights H1a and H2a of the first and second active areas AR1 and AR2 have. The third distance D3a between the first active area AR1 and the second active area AR2 is equal to the number of the first and second active fins AF1 and AF2, And may be variable according to the first and second heights H1a and H2a of the regions AR1 and AR2.

As described above, according to the present embodiment, the first active area AR1 is not arranged based on the third distance D3a between the first active area AR1 and the second active area AR2, Are arranged with reference to the first distance D1 from the boundary line CB1. Likewise, the second active area AR2 is not disposed on the basis of the third distance D3a between the first active area AR1 and the second active area AR2, and the second distance from the second cell boundary line CB2 And is disposed with reference to the second distance D2.

The plurality of conductive lines CL may extend in a second direction (e.g., Y direction) and may be disposed parallel to each other along a first direction (e.g., X direction). At this time, the conductive lines CL may be made of any material having electrical conductivity, and may include, for example, polysilicon, metal, metal fitting, and the like.

In one embodiment, the conductive lines CL may correspond to the gate electrodes. However, the present invention is not limited thereto, and the conductive lines CL may be a trace having any conductivity or the like. Although the standard cell C1 is shown as including three conductive lines in FIG. 1A, this is only an example, and the standard cell C1 extends in the second direction and is parallel to the first direction And may include four or more conductive lines arranged.

Referring to FIG. 1B, the standard cell C2 is defined by the cell boundary CB and may include a plurality of pins FIN and first and second active areas AR1 and AR2. In addition, the standard cell C2 may further include a plurality of conductive lines CL. The standard cell C2 according to the present embodiment is an alternative embodiment of the standard cell C1 in Fig. 1A, and the contents described above in Fig. 1A can be applied to this embodiment. Hereinafter, the difference from FIG. 1A will be mainly described.

In this embodiment, the standard cell C2 includes three first active pins AF1, three second active pins AF2, one first dummy pin DF1, one second dummy pin DF2, And four third dummy pins DF3. However, the present invention is not limited to this, and the number of each of the first and second active fins AF1 and AF2 and the first to third dummy fins DF1, DF2 and DF3 may be variously changed. In another embodiment, the standard cell C2 may not include one of the first through third dummy pins DF1, DF2, DF3.

The first height H1b of the first active area AR1 may be changed according to the number of the first active pins AF1. Similarly, the second height H2b of the second active area AR2 can be changed according to the number of the second active fins AF2. In one embodiment, the number of first active pins AF1 and the number of second active pins AF2 may be the same so that the first height H1b and the second height H2b are substantially equal can do. In this embodiment, the first active region AR1 and the second active region AR2 may have different conductivity types.

In this embodiment, the first and second active areas AR1 and AR2 may be disposed close to the cell boundary CB, and specifically, the first active area AR1 may be disposed on the first cell boundary line CB1 , And the second active region AR2 may be disposed adjacent to the second cell boundary line CB2. More specifically, the first active area AR1 may be arranged to be separated from the first cell boundary line CB1 by a first distance D1, and the second active area AR2 may be arranged to be separated from the second cell boundary line CB2 by a second distance D2.

In this embodiment, the first and second distances D1 and D2 may have a constant value regardless of the number of the first and second active fins AF1 and AF2. In other words, the first and second distances D1 and D2 can have constant values regardless of the first and second heights H1b and H2b of the first and second active areas AR1 and AR2 have. The third distance D3b between the first active area AR1 and the second active area AR2 is equal to the number of the first and second active fins AF1 and AF2, And may be variable according to the first and second heights H1b and H2b of the regions AR1 and AR2.

Therefore, according to the present embodiment, since the number of the first and second active fins AF1 and AF2 is smaller than that in Fig. 1A, the first and second heights of the first and second active regions AR1 and AR2 The first and second heights H1b and H2b are also smaller than the first and second heights H1a and H2a of FIG. 1A. Nevertheless, the first and second distances D1, D2 may be substantially the same as the first and second distances D1, D2 of FIG. 1A. On the other hand, the third distance D3b may be larger than the third distance D3a of FIG. 1A.

As described above, according to the present embodiment, the first active area AR1 is not arranged on the basis of the third distance D3b between the first active area AR1 and the second active area AR2, Are arranged with reference to the first distance D1 from the boundary line CB1. Likewise, the second active area AR2 is not arranged on the basis of the third distance D3b between the first active area AR1 and the second active area AR2, and the second distance from the second cell boundary line CB2 And is disposed with reference to the second distance D2.

Referring to FIG. 1C, the standard cell C3 is defined by the cell boundary CB and may include a plurality of pins FIN and first and second active areas AR1 and AR2. In addition, the standard cell C2 may further include a plurality of conductive lines CL. The standard cell C3 according to this embodiment is an alternative embodiment of the standard cell C1 of FIG. 1A and the standard cell C2 of FIG. 1B, and the contents described in FIGS. 1A and 1B can be applied to this embodiment have. Hereinafter, differences from FIGS. 1A and 1B will be mainly described.

In this embodiment, the standard cell C3 includes two first active pins AF1, two second active pins AF2, one first dummy pin DF1, one second dummy pin DF2, And six third dummy pins DF3. However, the present invention is not limited to this, and the number of each of the first and second active fins AF1 and AF2 and the first to third dummy fins DF1, DF2 and DF3 may be variously changed. In another embodiment, the standard cell C3 may not include one of the first through third dummy pins DF1, DF2, DF3.

The first height H1c of the first active area AR1 may be changed in accordance with the number of the first active fins AF1. Likewise, the second height H2c of the second active area AR2 can be changed in accordance with the number of the second active fins AF2. In one embodiment, the number of first active pins AF1 and the number of second active pins AF2 may be the same so that the first height H1c and the second height H2c are substantially equal can do. In this embodiment, the first active region AR1 and the second active region AR2 may have different conductivity types.

In this embodiment, the first and second active areas AR1 and AR2 may be disposed close to the cell boundary CB, and specifically, the first active area AR1 may be disposed on the first cell boundary line CB1 , And the second active region AR2 may be disposed adjacent to the second cell boundary line CB2. More specifically, the first active area AR1 may be arranged to be separated from the first cell boundary line CB1 by a first distance D1, and the second active area AR2 may be arranged to be separated from the second cell boundary line CB2 by a second distance D2.

In this embodiment, the first and second distances D1 and D2 may have a constant value regardless of the number of the first and second active fins AF1 and AF2. In other words, the first and second distances D1 and D2 can have constant values regardless of the first and second heights H1c and H2c of the first and second active areas AR1 and AR2 have. The third distance D3c between the first active area AR1 and the second active area AR2 is equal to the number of the first and second active fins AF1 and AF2, And may be variable according to the first and second heights H1c and H2c of the regions AR1 and AR2.

Therefore, according to the present embodiment, since the number of the first and second active fins AF1 and AF2 is smaller than those in Figs. 1A and 1B, the first and second active fins AF1 and AF2, The second heights H1c and H2c are also smaller than the first and second heights H1a and H2a of FIG. 1A and the first and second heights H1c and H2c of FIG. 1B. Nevertheless, the first and second distances D1, D2 may be substantially the same as the first and second distances D1, D2 of FIGS. 1A and 1B. On the other hand, the third distance D3c may be larger than the third distance D3a of FIG. 1A and the third distance D3b of FIG. 1B.

As described above, according to the present embodiment, the first active area AR1 is not arranged based on the third distance D3c between the first active area AR1 and the second active area AR2, Are arranged with reference to the first distance D1 from the boundary line CB1. Likewise, the second active area AR2 is not arranged on the basis of the third distance D3c between the first active area AR1 and the second active area AR2, and the second distance from the second cell boundary line CB2 And is disposed with reference to the second distance D2.

According to the embodiments illustrated in Figs. 1A to 1C, as the number of the first and second active fins AF1 and AF2 is changed, the heights of the first and second active areas AR1 and AR2 are changed . As described above, according to the present embodiment, the first and second active areas AR1 and AR2 are connected to the first and second cell boundary lines CB1 and CB2, respectively, on the basis of the first and second cell boundary lines CB1 and CB, Can be arranged to be spaced apart from the lines CB1, CB by first and second distances D1, D2. In other words, according to the present embodiment, the first and second active areas AR1 and AR2 can be designed outbound toward the cell boundary CB.

Figures 2a-2d are layouts for some of the integrated circuits including the standard cells according to Figures 1a-1c.

Referring to FIG. 2A, the integrated circuit 10a may include a first standard cell C1 and a second standard cell C2 disposed adjacent to each other along a second direction. In this case, the first standard cell C1 disposed at the upper portion may correspond to the standard cell C1 of FIG. 1A, and the second standard cell C2 disposed at the lower portion may correspond to the standard cell C2 of FIG. 1B have. Hereinafter, the interval between the second active area AR2 of the first standard cell C1 arranged on the upper side and the first active area AR1 of the second standard cell C2 arranged on the lower side is referred to as a first active- Will be referred to as an active-to-active space S1.

In this embodiment, the first active-to-active interval S1 of the integrated circuit 10a may be a fixed interval. Specifically, the first active-to-active spacing S1 of the integrated circuit 10a is greater than the second distance D2 of the first standard cell C1 and the first distance D1 of the second standard cell C2, Can be calculated. In this embodiment, the first distance D1 and the second distance D2 in each standard cell may be substantially the same, and the first and second distances D1 and D2 may be substantially equal to the first distance D1 and the second distance D2, Can be constant regardless of the height of the electrodes AR1 and AR2. Therefore, the second distance D2 of the first standard cell C1 and the first distance D1 of the second standard cell C2 may be substantially the same. At this time, since the number of the second dummy pins DF2 of the first standard cell C1 is one and the number of the first dummy pins DF1 of the second standard cell C2 is one, The number of dummy pins arranged in the active interval S1 is two.

Referring to FIG. 2B, the integrated circuit 10b may include a second standard cell C2 and a second standard cell C2 disposed adjacent to each other along the second direction. At this time, the second standard cell C2 disposed at the upper portion and the second standard cell C2 disposed at the lower portion may correspond to the standard cell C2 shown in FIG. 1B. Hereinafter, the interval between the second active area AR2 of the second standard cell C2 disposed on the upper side and the first active area AR1 of the second standard cell C2 disposed on the lower side is referred to as a second active- Quot; active interval S2 ".

In this embodiment, the second active-to-active interval S2 of the integrated circuit 10b may be a fixed interval. Specifically, the second active-to-active spacing S2 of the integrated circuit 10b is greater than the second distance D2 of the second standard cell C2 and the first distance D1 of the second standard cell C2, Can be calculated. In this embodiment, the first distance D1 and the second distance D2 of the second standard cell C2 may be substantially the same. At this time, since the number of the second dummy pins DF2 of the second standard cell C2 is one and the number of the first dummy pins DF1 of the second standard cell C2 is one, The number of dummy pins arranged in the active interval S2 is two.

Referring to FIG. 2C, the integrated circuit 10c may include a second standard cell C2 and a third standard cell C3 arranged adjacent to each other along the second direction. In this case, the second standard cell C2 disposed at the upper portion may correspond to the standard cell C2 of FIG. 1B, and the third standard cell C3 disposed at the lower portion may correspond to the standard cell C3 of FIG. 1C have. Hereinafter, the interval between the second active area AR2 of the second standard cell C2 disposed on the upper side and the first active area AR1 of the third standard cell C3 disposed on the lower side is referred to as a third active- Quot; active interval S3 ".

In this embodiment, the third active-to-active interval S3 of the integrated circuit 10c may be a fixed interval. Specifically, the third active-to-active spacing S3 of the integrated circuit 10c is greater than the second distance D2 of the second standard cell C2 and the first distance D1 of the third standard cell C3, Can be calculated. In this embodiment, the first distance D1 and the second distance D2 in each standard cell may be substantially the same, and the first and second distances D1 and D2 may be substantially equal to the first distance D1 and the second distance D2, Can be constant regardless of the height of the electrodes AR1 and AR2. Therefore, the second distance D2 of the second standard cell C2 and the first distance D1 of the third standard cell C3 may be substantially the same. At this time, since the number of the second dummy pins DF2 of the second standard cell C2 is one and the number of the first dummy pins DF1 of the third standard cell C3 is one, The number of dummy pins arranged in the active interval S3 is two.

Referring to FIG. 2D, the integrated circuit 10d may include a third standard cell C3 and a third standard cell C3 arranged adjacent to each other along the second direction. At this time, the third standard cell C3 disposed at the upper portion and the third standard cell C3 disposed at the lower portion may correspond to the standard cell C3 shown in FIG. 1C. Hereinafter, the interval between the second active area AR2 of the third standard cell C3 disposed on the upper side and the first active area AR1 of the third standard cell C3 disposed on the lower side is defined as the fourth active- Quot; active interval S4 ".

In this embodiment, the fourth active-to-active interval S4 of the integrated circuit 10d may be a fixed interval. Specifically, the fourth active-to-active spacing S4 of the integrated circuit 10d is equal to the second distance D2 of the third standard cell C3 and the first distance D1 of the third standard cell C3, Can be calculated. In this embodiment, the first distance D1 and the second distance D2 of the third standard cell C3 may be substantially the same. At this time, since the number of the second dummy pins DF2 of the third standard cell C3 is one and the number of the first dummy pins DF1 of the third standard cell C3 is one, The number of dummy pins arranged in the active interval S4 is two.

As described above with reference to Figs. 2A to 2D, according to the present embodiment, regardless of the number of the first and second active pins included in each standard cell, active regions That is, the active-to-active interval may have a constant value. Accordingly, the performance of the target standard cell can be optimized by minimizing the influence of the active region included in the neighboring standard cell on the target standard cell.

Generally, in the standard cell design stage, that is, in the standard cell library generation stage, the standard cell layout can be designed according to the characteristics of the target standard cell itself. However, the characteristics of the target standard cell, for example, the timing characteristic, may be different depending on the layout pattern of the adjacent standard cells disposed adjacent to each other in the standard cell placement step, specifically, the active area included in the adjacent standard cell, can be changed. The phenomenon that the characteristic of the device corresponding to the target standard cell is changed according to the peripheral layout pattern is referred to as LLE (local layout effect). Hereinafter, the LLE will be described in detail with reference to FIGS. 3A to 6.

Figs. 3A to 3C are layouts of standard cells according to a comparative example to the embodiment illustrated in Figs. 1A to 1C.

Referring to FIG. 3A, a standard cell C1 'includes a plurality of pins FIN, first and second active regions AR1 and AR2, and a plurality of conductive lines CL. At this time, the standard cell C1 'includes four first active pins AF1, four second active pins AF2, one first dummy pin DF1, one second dummy pin DF2, Three third dummy pins DF3.

Referring to FIG. 3B, the standard cell C2 'includes a plurality of pins FIN, first and second active regions AR1 and AR2, and a plurality of conductive lines CL. At this time, the standard cell C2 'includes three first active pins AF1, three second active pins AF2, two first dummy pins DF1, two second dummy pins DF2, Three third dummy pins DF3.

The number of the first and second active fins AF1 and AF2 of the standard cell C2 'is smaller than that in Fig. 3A and therefore the first and second active fins AF1 and AF2 of the first and second active areas AR1 and AR2 The heights H1b and H2b are also smaller than the first and second heights H1a and H2a of FIG. 3A. At this time, the first and second active areas AR1 and AR2 are arranged such that the third distance D3 between the first active area AR1 and the second active area AR2 is smaller than the third distance D3 Are arranged toward the center of the standard cell C2 '.

Referring to FIG. 3C, the standard cell C3 'includes a plurality of pins FIN, first and second active regions AR1 and AR2, and a plurality of conductive lines CL. At this time, the standard cell C3 'includes two first active pins AF1, two second active pins AF2, three first dummy pins DF1, three second dummy pins DF2, Three third dummy pins DF3.

The number of the first and second active fins AF1 and AF2 of the standard cell C3 'is smaller than that of Fig. 3B, and therefore the first and second active fins AF1 and AF2 of the first and second active areas AR1 and AR2 The heights H1c and H2c are also smaller than the first and second heights H1b and H2b of FIG. 3b. At this time, the first and second active areas AR1 and AR2 are arranged such that the third distance D3 between the first active area AR1 and the second active area AR2 is smaller than the third distance D3 of FIG. Are arranged toward the center of the standard cell (C3 ').

Referring to FIGS. 3A to 3C, as the number of the first and second active fins AF1 and AF2 is changed, the first and second heights of the first and second active areas AR1 and AR2 are changed . At this time, the first and second active regions AR1 and AR2 are arranged based on a third distance D3 between the first and second active regions AR1 and AR2. In other words, the first and second active areas AR1 and AR2 are designed inbound to the center of the cell. Accordingly, the first distance between the first cell boundary line CB1 and the first active area AR1 and the first distance between the second cell boundary line CB2 (CB2) and the second cell boundary line CB2 (CB2) are changed as the number of the first and second active fins AF1, ) And the second active region AR2 is changed.

Figures 4A-4D are layouts for some of the integrated circuits including the standard cells according to Figures 3A-3C.

Referring to FIG. 4A, the integrated circuit 20a includes a first standard cell C1 'and a second standard cell C2' arranged adjacent to each other along a second direction. In this case, the first standard cell C1 'disposed at the upper portion corresponds to the standard cell C1' of FIG. 3A, and the second standard cell C2 'disposed at the lower portion corresponds to the standard cell C2' . Hereinafter, the interval between the second active area AR2 of the first standard cell C1 'disposed on the upper side and the first active area AR1 of the second standard cell C2' Will be referred to as active-to-active spacing S1 '.

The first active-to-active spacing S1 'of the integrated circuit 20a is determined by the distance between the second distance D2a of the first standard cell C1' and the first distance D1b of the second standard cell C2 ' As shown in FIG. At this time, since the number of the second dummy pins DF2 of the first standard cell C1 'is one and the number of the first dummy pins DF1 of the second standard cell C2' is two, The number of dummy pins arranged in the active-in-active interval S1 'is three.

Referring to FIG. 4B, the integrated circuit 20b includes a second standard cell C2 'and a second standard cell C2' disposed adjacent to each other along the second direction. At this time, the second standard cell C2 'disposed at the upper portion and the second standard cell C2' disposed at the lower portion correspond to the standard cell C2 'shown in FIG. 3B. Hereinafter, the interval between the second active area AR2 of the second standard cell C2 'disposed on the upper side and the first active area AR1 of the second standard cell C2' Quot; active-to-active interval S2 '.

The second active-to-active spacing S2 'of the integrated circuit 20b is greater than the second distance D2b of the second standard cell C2' and the first distance D1b of the second standard cell C2 ' As shown in FIG. At this time, since the number of the second dummy pins DF2 of the second standard cell C2 'is two and the number of the first dummy pins DF1 of the second standard cell C2' is two, The number of dummy pins arranged in the two-active interval S2 'is four.

Referring to FIG. 4C, the integrated circuit 20c includes a second standard cell C2 'and a third standard cell C3' that are disposed adjacent to each other along the second direction. In this case, the second standard cell C2 'disposed on the upper portion corresponds to the standard cell C2' of FIG. 3B, and the third standard cell C3 'disposed on the lower portion corresponds to the standard cell C3' . Hereinafter, the interval between the second active area AR2 of the second standard cell C2 'disposed on the upper side and the first active area AR1 of the third standard cell C3' Will be referred to as an active-to-active interval S3 '.

The third active-to-active spacing S3 'of the integrated circuit 20c is greater than the second distance D2b of the second standard cell C2' and the first distance D1c of the third standard cell C3 ' As shown in FIG. At this time, since the number of the second dummy pins DF2 of the second standard cell C2 'is two and the number of the first dummy pins DF1 of the third standard cell C3' is three, The number of dummy pins arranged in the to-active interval S3 'is five.

Referring to FIG. 4D, the integrated circuit 20d includes a third standard cell C3 'and a third standard cell C3' disposed adjacent to each other along the second direction. At this time, the third standard cell C3 'disposed at the upper portion and the third standard cell C3' disposed at the lower portion correspond to the standard cell C3 'shown in FIG. 3C. Hereinafter, the interval between the second active area AR2 of the third standard cell C3 'disposed on the upper side and the first active area AR1 of the third standard cell C3' Active-to-active interval S4 '.

The fourth active-to-active spacing S3 'of the integrated circuit 20d is greater than the second distance D2c of the third standard cell C3' and the first distance D1c of the third standard cell C3 ' As shown in FIG. At this time, since the number of the second dummy pins DF2 of the third standard cell C3 'is three and the number of the first dummy pins DF1 of the third standard cell C3' is three, The number of dummy pins arranged in the two-active interval S3 'is six.

Thus, if the first and second active regions in each standard cell are designed to be oriented towards the center of the cell, when the two standard cells are placed adjacent, the active-to-active spacing of the integrated circuit is included in each standard cell Lt; RTI ID = 0.0 > active < / RTI > In other words, the number of dummy cells arranged in the active-to-active interval is changed according to the number of active fins included in each standard cell, that is, the heights of the active areas.

When designing the active regions in the standard cell as illustrated in FIGS. 3A to 3C, the active-to-active interval in the placement step of the standard cells can be changed according to the adjacent standard cell, Can be changed. The number of active fins included in the adjacent standard cell can not be predicted in the designing stage for the target standard cell. Therefore, it is impossible to design the characteristic of the target standard cell to change according to the number of the active fins included in the adjacent standard cell.

As described above, a difference may occur between the device actually manufactured through the layout of standard cells and the layout of standard cells. Thus, this difference can result in increased uncertainty in the actually fabricated silicon device, resulting in MHC (Model Hardware Correlation) issues, and even worse, failing devices Lt; / RTI > Therefore, there is a need to minimize MHL uncertainty by minimizing the LLE problem.

5 is a graph showing the voltage change of a standard cell according to an active-to-active interval.

5, the X-axis represents the active-to-active interval between two adjacent active areas included in each of the target standard cell _Ctg and the adjacent standard cell C _adj , and the Y- C _tg ) of the transistor. The first through third cases CASE1, CASE2 and CASE3 may have a size (hereinafter referred to as " size ") of each conductive line (for example, Quot; length "). The length of the conductive line in the second case CASE2 is longer than the length of the first case CASE1 and the length of the conductive line in the third case CASE3 is longer than the length of the conductive line in the first case CASE1. And the length is longer than that of the second case (CASE2).

In the third case (CASE 3), despite the change of the active-to-active interval, the voltage change of the transistor included in the target standard cell C _tg is not large. A second case (CASE2) are active-to-the change in voltage of a transistor included in a target standard cell (C _tg) as the active interval is greater than the change in the third case (CASE3). The first case (CASE1) is an active-active considerably larger than a target standard cell (C _tg) of the voltage change of the second transistor and the third case (CASE2, CASE3) contained in the interval as a change-to.

6 is a graph showing the current change of a standard cell according to an active-to-active interval.

6, the X-axis represents the active-to-active interval between two adjacent active areas included in each of the target standard cell _Ctg and the adjacent standard cell C _adj , and the Y-axis represents the target standard cell C _tg ). &_Lt; / RTI > The first through third cases CASE1, CASE2 and CASE3 are sizes according to a first direction (e.g., X direction) of each conductive line (for example, CL in FIG. 1A) , Length). The length of the conductive line in the second case CASE2 is longer than the length of the first case CASE1 and the length of the conductive line in the third case CASE3 is longer than the length of the conductive line in the first case CASE1. And the length is longer than that of the second case (CASE2).

In the third case (CASE 3), despite the change of the active-to-active interval, the current change of the transistor included in the target standard cell (C _tg ) is not large. A second case (CASE2) are active-to-current change in the transistor included in a target standard cell (C _tg) as the active interval change is greater than a third case (CASE3). The first case (CASE1) is an active-active considerably larger than a target standard cell (C _tg), the current changes in the transistor comprising the second and third case (CASE2, CASE3) as the gap is changed-to.

As described above with reference to Figs. 5 and 6, as the length of the conductive line included in the standard cell decreases from the third case CASE3 to the first case CASE1, the active-to- It can be seen that the voltage / current variation of the transistor included in the target standard cell C _tg increases with the change in the interval. With the development of semiconductor process technology, the miniaturization of the process is further accelerated, and the length of the conductive line included in the standard cell is further reduced.

According to embodiments of the present invention, active areas may be outbound designed in a standard cell as illustrated in Figs. 1A-1C. Specifically, the standard cell can be designed such that the active-to-active spacing is constant in the design stage of the standard cell, so that the active-to-active spacing in the standard cell placement step is constant regardless of adjacent standard cells And thus the characteristic of the target standard cell C _tg can be maintained.

FIG. 7 is a graph showing leakage current ratios according to the number of dummy pins arranged in active-to-active spacing in an integrated circuit according to one embodiment of the present disclosure; FIG.

Referring to FIG. 7, the X axis represents the number of dummy pins arranged in the active-to-active interval between two adjacent active areas included in the target standard cell _Ctg and the adjacent standard cell C _adj , respectively , And the Y-axis represents the leakage current ratio of the device corresponding to the target standard cell (C _tg ). As the active-to-active spacing increases, the number of dummy pins arranged in the active-to-active spacing can increase. Thus, the number of dummy pins arranged in the active-to-active interval can be seen as being proportional to the active-to-active spacing.

As shown in the graph of FIG. 7, as the number of dummy pins arranged in the active-to-active interval increases, the leakage current ratio of the device decreases. Therefore, it may be advantageous to set the active-to-active interval relatively large in order to minimize the leakage current of the device.

8 is a graph illustrating the operating speed ratios according to the number of dummy pins arranged in active-to-active spacing in an integrated circuit according to one embodiment of the present disclosure;

8, the X axis represents the number of dummy pins arranged in the active-to-active interval between two adjacent active areas included in each of the target standard cell _Ctg and the adjacent standard cell C _adj , , And the Y axis represents the operating speed ratio of the device corresponding to the target standard cell (C _tg ). As the active-to-active spacing increases, the number of dummy pins arranged in the active-to-active spacing can increase. Thus, the number of dummy pins arranged in the active-to-active interval can be seen as being proportional to the active-to-active spacing.

As shown in the graph of Fig. 8, as the number of dummy pins arranged in the active-to-active interval increases, the operating speed ratio of the device decreases. Therefore, it may be advantageous to set the active-to-active interval relatively small in order to maximize the operating speed of the device.

Referring to FIGS. 7 and 8, it can be seen that the leakage current and the operating speed of the device are in a trade-off relationship. Therefore, according to this embodiment, in the step of designing the standard cell, the active-to-active interval can be determined by taking into consideration the leakage current and the operation speed of the device corresponding to the standard cell. Further, based on the determined active-to-active interval, a first distance between the first cell boundary line and the first active region in each standard cell and a second distance between the second cell boundary line and the second active region You can decide. In this embodiment, the first and second distances may be determined to have a constant value regardless of the number of active fins included in the standard cell or the height of the active area.

Figure 9 is a layout illustrating a portion of an integrated circuit 100 in accordance with one embodiment of the present disclosure.

Referring to FIG. 9, the integrated circuit 100 may include at least one cell (CELL) defined by a cell boundary CB indicated by a bold solid line. The cell CELL includes a plurality of pins including a plurality of active pins 110 and a plurality of dummy pins 120, a plurality of gate electrodes 130, a plurality of source / drain contacts 140, Two input contacts 155, an output terminal 160 and two power supply lines VDD and VSS. Although not shown, a plurality of conductive lines, e.g., metal lines, may be further disposed on the cell (CELL).

In this embodiment, the cell CELL may be a standard cell. Such a standard cell-based layout design technique is designed such that elements such as OR gates or AND gates used repeatedly are preliminarily designed as standard cells and stored in a computer system, It is possible to shorten the time required for the layout design.

The plurality of active pins 110 may include first through fourth active pins 111 through 114. However, the number of the plurality of active fins 110 included in one cell (CELL) is not limited to four, and can be variously changed according to the embodiment. In one embodiment, the number of the plurality of active pins 110 included in one cell (CELL) may be more than four, and in another embodiment, a plurality of active pins (CELL) included in one cell 110) may be less than four.

The active pins disposed adjacent to each other among the first to fourth active pins 111 to 114 may constitute one pin transistor. As a result, the channel width can be increased in the pin transistor in proportion to the number of active fins constituting one fin transistor, so that the amount of current flowing in the pin transistor can be increased.

The plurality of dummy pins 120 may include first to fourth dummy pins 121 to 124. However, the number of the plurality of dummy pins 120 included in one cell (CELL) is not limited to four, and can be variously changed according to the embodiment. In one embodiment, the number of the plurality of dummy pins 120 included in one cell may be greater than four, and in another embodiment, a plurality of dummy pins included in one cell (CELL) 120) may be less than four.

The first and second active pins 111 and 112 and the first and second dummy pins 121 and 122 are disposed in the first confining layer DL1 and the third and fourth active pins 113 and 114 and The third and fourth dummy pins 123 and 124 may be disposed in the second confinement layer DL2. In this embodiment, the first confinement layer DL1 may be a PMOS confinement layer doped with P + impurities, and the second confinement layer DL2 may be an NMOS confinement layer doped with N + impurities. As a result, the first and second active pins 111 and 112 disposed in the first limiting layer DL1 constitute a PMOS pin transistor, and the third and fourth active pins 113 and 114 may constitute an NMOS pin transistor.

Specifically, since two gate electrodes 130 and three source / drain contacts 140 are disposed on top of the first and second active pins 111 and 112, the first and second active pins 111 and 112 , 112) can constitute two PMOS pin transistors connected in parallel. Since the two gate electrodes 130 and the two source / drain contacts 140 are disposed on the third and fourth active pins 113 and 114, the third and fourth active pins 113 and 114, 114 may comprise two NMOS pin transistors connected in series.

The first to fourth active pins 111 to 114 and the first to fourth dummy pins 121 to 124 extend in the first direction (e.g., the X direction) and extend in the second direction Direction). Here, the second direction may be substantially perpendicular to the first direction.

The first distance D1 'between the first active pin 111 and the first cell boundary line CB1 and the first distance D1' between the fourth active pin 114 and the second cell boundary line CB2 in this embodiment, The distance D2 'may be constant regardless of the number of active fins included in one cell (CELL). Meanwhile, the third distance D3 'between the second active pin 112 and the third active pin 113 can be changed according to the number of active fins included in one cell (CELL).

Therefore, according to the present embodiment, when two cells are arranged adjacent to each other in the second direction (e.g., the Y direction), the difference between the lowest active pin of the upper cell and the uppermost active pin of the cell disposed below The active-to-active spacing of the electrodes can always be constant. Thus, the characteristic change of the target cell due to the active pin included in the adjacent cell can be minimized.

10 is a perspective view showing an example of a semiconductor device 100a having the layout of FIG. 11 is a cross-sectional view taken along the line X-X 'in Fig.

10 and 11, the semiconductor device 100a may be a bulk type pin transistor. The semiconductor device 100a includes a substrate 102, a first insulating layer 104, a second insulating layer 106, first and second active pins 111 and 112, second and third dummy pins 122, 123, and a gate electrode 130. [

The substrate 102 may be a semiconductor substrate, for example, a silicon substrate, a silicon-on-insulator (SOI), a silicon-on-sapphire, Silicon-germanium, and gallium-arsenide.

The first and second active pins 111 and 112 and the second and third dummy pins 122 and 123 may be arranged to be connected to the substrate 102. In one embodiment, the first and second active pins 111 and 112 may be active regions doped with n + or p + portions protruding from the vertical portion of the substrate 102, and the second and third dummy pins 122, and 123 may be regions that are not doped with the portion protruding from the substrate 102 to the vertical portion. In other embodiments, both the first and second active pins 111 and 112 and the second and third dummy pins 122 and 123 may be active regions doped with n + or p +.

The first and second insulating layers 104 and 106 may include an insulating material, for example, the insulating material may include any one of an oxide film, a nitride film, and an oxynitride film. The first insulating layer 104 may be disposed on the first and second active pins 111, 112 and the second and third dummy pins 122, 123. The first insulating layer 104 is disposed between the first and second active fins 111 and 112 and the gate electrode 130 so that it can be used as a gate insulating film. The second insulating layer 106 may be disposed to have a predetermined height in the space between the first and second active pins 111 and 112 and the second and third dummy pins 122 and 123. The second insulating layer 106 is disposed between the first and second active pins 111 and 112 and the second and third dummy pins 122 and 123 so that the second insulating layer 106 can be used as the device isolation film.

The gate electrode 130 may be disposed on top of the first and second insulating layers 104 and 106. The gate electrode 130 may have a structure surrounding the first and second active pins 111 and 112, the second and third dummy pins 122 and 123, and the second insulating layer 106. In other words, the first and second active pins 111 and 112 and the second and third dummy pins 122 and 123 may be disposed inside the gate electrode 130. The gate electrode 130 may include a metal material such as W, Ta, etc., a nitride thereof, a silicide thereof, a doped polysilicon, or the like, and may be formed using a deposition process.

12 is a perspective view showing another example 100b of the semiconductor element having the layout of FIG. 13 is a sectional view taken along the line XII-XII 'in Fig.

12 and 13, the semiconductor device 100b may be an SOI type pin transistor. The semiconductor device 100b includes a substrate 102, a first insulating layer 104 ', a second insulating layer 106', first and second active pins 111 'and 112' Pins 122 ', 123 ', and a gate electrode 130. [ Since the semiconductor device 100b according to the present embodiment is a modified embodiment of the semiconductor device 100a shown in Figs. 10 and 11, the following description will focus on the difference from the semiconductor device 100a, The description of which will be omitted.

The first insulating layer 104 'may be disposed on the substrate 102. The second insulating layer 106 'is disposed between the first and second active fins 111' and 112 'and the second and third dummy fins 122 and 123 and the gate electrode 130, Can be used. The first and second active pins 111 'and 112' and the second and third dummy pins 122 'and 123' may be a semiconductor material, for example, silicon or doped silicon.

The gate electrode 130 may be disposed on top of the second insulating layer 106 '. The gate electrode 130 thus has a structure surrounding the first and second active pins 111 'and 112', the second and third dummy pins 122 'and 123' and the second insulating layer 106 'Lt; / RTI > In other words, the first and second active pins 111 'and 112' and the second and third dummy pins 122 'and 123' may be disposed inside the gate electrode 130.

14 is a block diagram illustrating a storage medium 500 in accordance with one embodiment of the present disclosure.

14, storage medium 500 is a computer-readable storage medium, which may include any storage medium that can be read by a computer while being used to provide instructions and / or data to the computer . For example, the computer-readable storage medium 500 may be a magnetic or optical medium such as a disk, a tape, a CD-ROM, a DVD-ROM, a CD-R, a CD-RW, a DVD- Volatile or nonvolatile memory such as ROM, flash memory, etc., nonvolatile memory accessible through a USB interface, and microelectromechanical systems (MEMS). The computer readable storage medium can be embedded in a computer, integrated into a computer, or coupled to a computer via a communication medium such as a network and / or a wireless link.

14, a computer-readable storage medium 500 may include a placement and routing program 510, a library 520, an analysis program 530, and a data structure 540. The placement and routing program 510 may include a plurality of instructions to perform a method of designing an integrated circuit using a standard cell library according to an exemplary embodiment of the present invention. For example, the computer-readable storage medium 500 may include any arrangement for designing an integrated circuit using a standard cell library including standard cells shown in one or more of the preceding figures, and The wiring program 510 can be stored. The library 520 may include information on a standard cell that is a unit constituting an integrated circuit.

The analysis program 530 may include a plurality of instructions that perform a method of analyzing an integrated circuit based on data defining the integrated circuit. For example, a computer-readable storage medium 500 includes any instructions that perform a method of analyzing the timing characteristics of an integrated circuit according to an active-to-active interval between two adjacent standard cells The analysis program 530 can be stored. The data structure 540 may be obtained by using the standard cell library included in the library 520 or by extracting the marker information from the general standard cell library included in the library 520 or by the analysis program 530 using the timing of the integrated circuit A storage space for managing data generated in the process of analyzing characteristics, and the like.

15 is a block diagram illustrating a memory card 1000 including an integrated circuit according to one embodiment of the present disclosure.

Referring to FIG. 15, the memory card 1000 may be arranged so that the controller 1100 and the memory 1200 exchange electrical signals. For example, when the controller 1100 issues a command, the memory 1200 can transmit data.

The controller 1100 and the memory 1200 may include an integrated circuit according to embodiments of the present invention. Specifically, in at least one semiconductor element of the plurality of semiconductor elements included in the controller 1100 and the memory 1200, the pin transistor included in the semiconductor element or the semiconductor element is in a first direction (e.g., the X direction) A plurality of fins disposed parallel to each other along a second direction (e.g., the Y direction) perpendicular to the first direction, a first cell boundary line extending parallel to the plurality of fins, A first active region disposed to be spaced a first distance from the line and a second active region disposed adjacent the second cell boundary line opposing the first cell boundary line and spaced a second distance from the second cell boundary line, Region, and the first and second distances may be constant regardless of the number of fins on the first and second active regions, respectively.

The memory card 1000 may include various types of cards such as a memory stick card, a smart media card (SM), a secure digital card (SD), a mini-secure digital card a mini-secure digital card (mini SD), and a multimedia card (MMC).

16 is a block diagram illustrating a computing system 2000 including an integrated circuit according to one embodiment of the present disclosure.

16, a computing system 2000 may include a processor 2100, a memory device 2200, a storage device 2300, a power supply 2400, and an input / output device 2500. 16, the computing system 2000 may further include ports capable of communicating with, or communicating with, video cards, sound cards, memory cards, USB devices, and the like .

As described above, the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the input / output device 2500 included in the computing system 2000 can be implemented in the embodiment according to the technical idea of the present invention Lt; RTI ID = 0.0 > IC < / RTI > Specifically, in at least one of the plurality of semiconductor elements included in the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the input / output device 2500, The pin transistor included in the semiconductor element includes a plurality of pins extending in a first direction (e.g., the X direction) and arranged in parallel with each other along a second direction (e.g., the Y direction) perpendicular to the first direction, A first active region adjacent to a first cell boundary line parallel to the plurality of pins and spaced apart from the first cell boundary line by a first distance, and a second cell boundary line adjacent to the second cell boundary line opposing the first cell boundary line, And a second active region arranged to be spaced a second distance from the second cell boundary line, wherein the first and second distances are respectively independent of the number of fins on the first and second active regions It can be determined.

Processor 2100 may perform certain calculations or tasks. According to an embodiment, the processor 2100 may be a micro-processor, a central processing unit (CPU). The processor 2100 is coupled to the memory device 2200, the storage device 2300, and the input / output device 2500 via a bus 2600, such as an address bus, a control bus, and a data bus, Lt; / RTI > In accordance with an embodiment, the processor 2100 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 2200 may store data necessary for operation of the computing system 2000. For example, the memory device 2200 may be implemented as a DRAM, a mobile DRAM, an SRAM, a PRAM, an FRAM, an RRAM, and / or an MRAM. have. The storage device 2300 may include a solid state drive, a hard disk drive, a CD-ROM, and the like.

The input / output device 2500 may include input means such as a keyboard, a keypad, a mouse, etc., and output means such as a printer, a display, and the like. The power supply 2400 may supply the operating voltage required for operation of the computing system 2000.

The integrated circuit according to the embodiments of the present invention described above can be implemented in various types of packages. For example, at least some configurations of an integrated circuit may be implemented using a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in- , Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package Package (WSP) or the like.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

C1, C2, C3: standard cell
10a, 10b, 10c: integrated circuit
100, 100a, 100b: semiconductor element

Claims (21)

Wherein forming at least one standard cell comprises forming at least one standard cell,
Providing a first active region adjacent the first cell boundary line and spaced a first distance from the first cell boundary line, the first active region extending in a first direction parallel to the first cell boundary line;
A second cell boundary line disposed adjacent to the second cell boundary line opposite to the first cell boundary line and spaced apart from the second cell boundary line by a second distance and extending in the first direction parallel to the second cell boundary line, Providing an active area;
Forming fins on the first and second active regions that are parallel to each other along a second direction extending in the first direction and perpendicular to the first direction; And
And forming conductive lines extending in the second direction and arranged parallel to each other,
The first and second cell boundary lines being parallel to the pins,
Wherein the first distance and the second distance are kept constant when the number of the fins on the first and second active areas is changed and the extending direction of the first and second cell boundary lines is an extension of the conductive lines Direction of the integrated circuit. The method according to claim 1,
Further comprising reducing the distance between the first active region and the second active region when the length of the first and second active regions along the second direction increases. Way. The method according to claim 1,
Further comprising adjusting a length of the first and second active regions along the second direction while the first and second distances remain constant. ≪ Desc / Clms Page number 22 > The method according to claim 1,
Wherein the first distance is equal to the second distance. The method according to claim 1,
Wherein forming the pins comprises:
Forming active fins on the first and second active regions; And
Forming dummy pins on the dummy regions where the first and second active regions are not disposed. ≪ Desc / Clms Page number 20 > 6. The method of claim 5,
Wherein forming the dummy pins comprises:
Forming at least one first dummy pin disposed between the first cell boundary line and the first active region;
Forming at least one second dummy pin disposed between the second cell boundary line and the second active region; And
And forming at least one third dummy pin disposed between the first active region and the second active region. The method according to claim 6,
Wherein the number of the at least one first dummy pin is equal to the number of the at least one second dummy pin. The method according to claim 6,
Further comprising decreasing the number of the at least one third dummy pin when the number of the active pins is increased. The method according to claim 6,
Further comprising the step of adjusting the number of the active pins while the number of the at least one first dummy pin and the number of the at least one second dummy pin are kept constant. . delete The method according to claim 1,
Wherein the first active region is doped with an impurity of a first conductivity type and the second active region is doped with an impurity of a second conductivity type different from the first conductivity type. Wherein forming at least one standard cell comprises forming at least one standard cell,
Forming active pins extending in a first direction and parallel to each other along a second direction perpendicular to the first direction;
Forming dummy pins parallel to the active pins; And
And forming conductive lines extending in the second direction and arranged parallel to each other,
Wherein forming the active pins comprises:
Forming a first active pin closest to the first cell boundary line, spaced a first distance from the first cell boundary line and extending in the first direction parallel to the first cell boundary line, and
Forming a second active pin closest to the second cell boundary line and spaced a second distance from the second cell boundary line and extending in the first direction parallel to the second cell boundary line, ,
Wherein the first distance and the second distance are kept constant when the number of the active pins is changed and the extending direction of the first and second cell boundary lines is perpendicular to the extending direction of the conductive lines. A method of generating a layout of a circuit. 13. The method of claim 12,
Wherein forming the dummy pins comprises:
Forming at least one first dummy pin disposed between the first cell boundary line and the first active pin; And
And forming at least one second dummy pin disposed between the second cell boundary line and the second active pin. 14. The method of claim 13,
Wherein the number of the at least one first dummy pin is equal to the number of the at least one second dummy pin. 14. The method of claim 13,
Further comprising the step of adjusting the number of the active pins while the number of the at least one first dummy pin and the number of the at least one second dummy pin are kept constant. . CLAIMS 1. A method of generating an integrated circuit layout using a standard cell library,
Selecting standard cells from a standard cell library stored in a computer readable storage medium; And
Generating the integrated circuit layout using the selected standard cells,
Each of the standard cells includes:
Pins parallel to each other along a second direction extending in a first direction and perpendicular to the first direction,
A first active region adjacent to a first cell boundary line parallel to the fins, a first active region spaced a first distance from the first cell boundary line and extending in the first direction parallel to the first cell boundary line,
A second active region extending in the first direction adjacent to the second cell boundary line opposite to the first cell boundary line and spaced a second distance from the second cell boundary line and extending in the first direction parallel to the second cell boundary line, Area, and
And conductive lines extending in the second direction and arranged parallel to each other,
Wherein the first distance and the second distance are kept constant when the number of the fins on the first and second active areas is changed and the extending direction of the first and second cell boundary lines is an extension of the conductive lines Direction of the integrated circuit. 17. The method of claim 16,
Wherein the step of creating the integrated circuit layout includes reducing the distance between the first active area and the second active area when the length of the first and second active areas along the second direction increases Wherein the integrated circuit layout generating method comprises: 17. The method of claim 16,
Wherein the step of creating the integrated circuit layout includes changing the length of the first and second active areas along the second direction while the first and second distances are kept constant A method of generating an integrated circuit layout. 17. The method of claim 16,
Wherein:
Active fingers disposed on the first and second active regions, and
And dummy pins disposed on dummy regions where said first and second active regions are not disposed. ≪ RTI ID = 0.0 > 11. < / RTI > 20. The method of claim 19,
Wherein the step of generating the integrated circuit layout includes changing the number of the dummy pins disposed between the first active area and the second active area when the number of the active pins is changed A method of generating an integrated circuit layout. 17. The method of claim 16,
Wherein the standard cells include a first standard cell and a second standard cell,
Wherein the step of generating the integrated circuit layout further comprises the step of forming the first standard cell and the second standard cell in the second direction so that the second boundary line of the first standard cell and the first boundary line of the second standard cell are in contact with each other, Adjacent to each other,
Wherein a distance between a second active region included in the first standard cell and a first active region included in the second standard cell is maintained constant.

Images