KR101913851B1 - Clock synchronization oscillators system by using clock bus line - Google Patents

Abstract

The present invention relates to an oscillator system capable of introducing a new type of bus line called a clock bus line to perform clock synchronization of a plurality of oscillators. More specifically, the present invention relates to a semiconductor device having a first oscillator for generating a first clock signal, a second oscillator for generating a second clock signal, and a first and a second oscillator, and a clock bus line connecting the first node on the first oscillator and the second node on the second oscillator corresponding to the specific node, the oscillator system comprising: will be.

Description

CLOCK SYNCHRONIZATION OSCILLATORS SYSTEM BY USING CLOCK BUS LINE.

The present invention relates to an oscillator system capable of accurately synchronizing the frequency and phase of signals generated by two or more oscillators using a new type of bus line called a clock bus line.

With the development of System on Chip (SoC) design technology today, the clock signals of integrated circuits constituting the system are mostly GHz, and the operating speed is continuously increasing. Ultra high-speed clock generation and distribution is a very important technology in integrated circuit design.

Therefore, synchronization in two or multiple chips operating at very high speeds with the development of SoC technology is a very important technical requirement. If an environmentally sensitive voltage with a slightly different mV unit is generated and supplied to each chip, it may cause problems in clock signal generation and distribution. This can lead to problems due to asynchronization of the clock signal of each chip, which can provide a fundamental cause of increasing the failure rate of the system.

 If a clock skew occurs, a system operation that requires a clock signal may fail. Currently, it is preferred to use PLL (Phase Locked Loop) circuit to detect the phase difference of the generated clock signal and to solve the synchronization problem of the circuit. However, the PLL circuit is complicated in structure and has a burden of increasing the chip size due to the wiring area.

Accordingly, there is a need for a technique for achieving overall synchronization by a simple method without additional circuitry.
On the other hand, JP-A-10-2004-0088029 (a phase locked loop circuit for selectively correcting a clock skew in a different mode) is known as a prior art related thereto.

The present invention is directed to solving the above-mentioned problems and other problems. Another object of the present invention is to provide an oscillator system that minimizes errors caused by clock skew and asynchronous operation while minimizing a change in chip size.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, unless further departing from the spirit and scope of the invention as defined by the appended claims. It will be possible.

According to an aspect of the present invention, there is provided an oscillator comprising: a first oscillator for generating a first clock signal; A second oscillator for generating a second clock signal; And the first and second oscillators are comprised of a two-dimensional or three-dimensional fractal structure of a plurality of inverting amplifiers, wherein a first node on the first oscillator and a second oscillator on the second oscillator corresponding to the particular node And a clock bus line connecting the second node.

The fractal structure may have a structure of a ring-shaped oscillator structure including three nodes so as to have a phase difference of 120 DEG with respect to each other on a semiconductor chip as a basic unit.

At this time, the three nodes of the basic unit may be formed into a triangular shape by the first to third inverting amplifiers.

The three nodes include a first node formed by connecting an input terminal of the first inverting amplifier and an output terminal of the third inverting amplifier, and an input terminal of the second inverting amplifier and an output terminal of the first inverting amplifier are connected And a third node formed by connecting an input terminal of the third inverting amplifier and an output terminal of the second inverting amplifier.

Also, in the fractal structure, a plurality of basic units in which three nodes are formed in a triangular shape may be repeatedly connected in a two-dimensional or three-dimensional manner.

In the fractal structure, the number of basic units can be formed by a sum of an odd number sequence having a first term of 1 and a tolerance of 1.

이고, n은 정수일 수 있다.Specifically, the number of the basic units is,

And n may be an integer.

Wherein the fractal structure includes first to third basic units, a node of the first basic unit and a node of the second basic unit are connected to form a fourth node, The nodes of the third basic unit are connected to form the fifth node, and the node of the third basic unit and the node of the first basic unit are connected to form the sixth node.

The first and second oscillators may have the same frequency and the same phase.

The effect of the oscillator system according to the present invention will be described as follows.

According to at least one of the embodiments of the present invention, there is an advantage that the phase of a clock signal generated on a plurality of chips can be synchronized.

In addition, according to at least one embodiment of the present invention, the ring oscillator circuit is used to connect the same phase to the clock line, so that the clock signals generated in the plurality of chips in the system are supplied Clock skew and asynchronous operation can be minimized.

Further scope of applicability of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, such as the preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art.

1 is a diagram showing a structure of a ring oscillator according to an embodiment of the present invention.
2 is a diagram showing the number and the manner in which the base unit 101 is arranged to form the fractal structure 100 of the ring oscillator according to an embodiment of the present invention.
3 and 4 are diagrams showing a conceptual diagram for synchronizing the clock signals of the first and second ring oscillators 301-1 and 301-2, according to an embodiment of the present invention.
FIGS. 5 and 6 are diagrams showing clock signals in the absence of clock bus lines in the ring oscillators 301-1 and 301-2, respectively, according to an embodiment of the present invention.
FIG. 7 is an enlarged view of the clock skew generated in FIG.
8 is a table showing a result of measuring a measured clock skew according to a voltage variation when there is no clock bus line.
9 is a table showing a result of measurement of a measured clock skew in accordance with a voltage variation after being connected to a clock bus line.
10 shows an image in which a ring oscillator is laid out in a CMOS according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals are used to designate identical or similar elements, and redundant description thereof will be omitted. The suffix "module" and " part "for the components used in the following description are given or mixed in consideration of ease of specification, and do not have their own meaning or role. In the following description of the embodiments of the present invention, a detailed description of related arts will be omitted when it is determined that the gist of the embodiments disclosed herein may be blurred. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. , ≪ / RTI > equivalents, and alternatives.

Terms including ordinals, such as first, second, etc., may be used to describe various elements, but the elements are not limited to these terms. The terms are used only for the purpose of distinguishing one component from another.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The singular expressions include plural expressions unless the context clearly dictates otherwise.

In the present application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a component, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In recent years, the degree of integration of semiconductor chips has been increasing due to the development of semiconductor manufacturing technology. As a result, it becomes possible to implement circuits that perform various functions on a single semiconductor chip. In the past, digital blocks and analog blocks have been produced separately. Recently, a system such as a system-on-chip (SOC) can be implemented on a single semiconductor chip. On the other hand, in order to implement one system on a single semiconductor chip, more than several million gates must be mounted. However, when a large number of gates are mounted on a single semiconductor chip, the routing lengths between the gates may be different from each other. Therefore, the phase difference (i.e., signal delay) of the clock signals between gates generated after the routing is completed can become a serious problem.

The phase difference of the clock signal between these gates acts as a main cause of the function error of the whole system and is an unpredictable parameter in the circuit design stage.

Therefore, a functional error of the system due to the phase difference between the gates is not found in the circuit design stage, but is often found in a post verification step performed after the routing is completed. When such a functional error occurs in the post verification step, there is a problem that the design period is increased because the circuit must be redesigned.

Currently, it is preferred to use PLL (Phase Locked Loop) circuit to detect the phase difference of the generated clock signal and to solve the synchronization problem of the circuit. However, the PLL circuit is complicated in structure and has a burden of increasing the chip size due to the wiring area.

In the present invention, a multi-chip system clock signal distribution and synchronization method using an in-phase clock line and a system using the same are proposed. The proposed scheme uses the ring oscillator circuit to connect the same phase to the clock line (clock bus line), so that the clock signals generated from the multiple chips in the system are held according to the difference of the power supply voltage between chips We want to minimize errors caused by clock skew and asynchronous operation. In a CMOS ring oscillator, all nodes operate at the same frequency when oscillating. This structure is very effective for frequency-shift keying by realizing network-wide clock signal synchronization even with partial voltage and temperature differences, and by increasing the number of inverters without the addition of a separately designed circuit. Also, as in the embodiment of the present invention, ring oscillators in the entire chip necessarily have the same frequency if a plurality of different ring oscillators designed with the same structure are connected in phase.

An oscillator system according to an embodiment of the present invention includes: a first oscillator for generating a first clock signal; A second oscillator for generating a second clock signal; And the first and second oscillators comprise a two-dimensional or three-dimensional fractal structure (100) of a plurality of inverting amplifiers, wherein the first node on the first oscillator and the second node on the first oscillator And a clock bus line connecting the second node on the oscillator. It is proposed that the first and second oscillators are provided as ring oscillators.

1 is a diagram showing a structure of a ring oscillator according to an embodiment of the present invention.

The ring oscillator structure according to an embodiment of the present invention is an odd number of inverters (Inverters, or inverting amplifiers) connected in series. In the simplest case, a ring oscillator consisting of three inverters has a phase difference of 120 °, but when passing through three inverters, any point will have the same frequency and phase. In this structure, a cell consists of three inverters and has n feed-pack loops.

The fractal structure of the ring oscillator may have a structure of a ring oscillator type structure including three nodes 102-1 to 102-3 so as to have a phase difference of 120 DEG with respect to each other on a semiconductor chip as a basic unit 101 (unit). As shown in the drawing, the three nodes 102-1 to 102-3 of the basic unit 101 form a triangular shape by the first to third inverting amplifiers 103-1 to 103-3 .

Specifically, the three nodes 102-1 to 102-3 are connected to the first node of the first inverting amplifier 103-1 and the output node of the third inverting amplifier 103-3, A second node 102-2 formed by connecting the input terminal of the second inverting amplifier 103-2 and the output terminal of the first inverting amplifier 103-1, And a third node 102-3 formed by connecting the input terminal of the amplifier 103-3 and the output terminal of the second inverting amplifier 103-2.

2 is a diagram showing the number and the manner in which the basic units 101-1 to 101-3 are arranged to form the fractal structure 100 of the ring oscillator according to an embodiment of the present invention.

As shown in FIGS. 1 and 2, the fractal structure 100 includes a plurality of basic units 101 in which three nodes 102-1 to 102-3 are formed in a triangular shape, as two-dimensional or three-dimensional It can be connected repeatedly.

In the fractal structure 100, the number of basic units 101 can be calculated as the sum of the odd-order series having the first term of 1 and the tolerance of 1. Specifically, the above-described sequence of equations can be expressed by the following equation (1).

Where n is an integer.

The fractal structure will now be described in more detail.

The fractal structure includes first to third basic units 101-1 to 101-3, and a node of the first basic unit 101-1 and a node of the second basic unit 101-2, And a node of the second basic unit 101-2 and a node of the third basic unit 101-3 are connected to form a fifth node 102-5 And a node of the third basic unit 101-3 and a node of the first basic unit 101-1 may be connected to form a sixth node 102-6.

In the present invention, a method of synchronizing a plurality of clock signals of the ring oscillator described above with reference to FIGS. 1 and 2 is proposed.

3 and 4 are diagrams showing a conceptual diagram for synchronizing the clock signals of the first and second ring oscillators 301-1 and 301-2, according to an embodiment of the present invention.

As shown in the drawing, at least one clock bus line connecting the first and second ring oscillators 301-1 and 301-2 may be provided.

More specifically, a clock bus line 302-1 connecting a first node on the first ring oscillator 301-1 and a second node on the second ring oscillator 301-2 corresponding to the specific node, To 302-3, a clock bus line).

The present invention further proposes the positions of the nodes where the clock bus lines 302-1 to 302-3 are provided.

In one embodiment of the present invention, it is proposed to provide the clock bus lines 302-1 to 302-3 at the positions of three nodes corresponding to the vertices in the triangular shape of the entire fractal structure.

The first to third vertex nodes 401-1 to 401-3 and the first to third vertex nodes 401-1 to 401-3 corresponding to the vertex in the triangular shape formed by the entire fractal structure of the first ring oscillator 301-1, 1 to 401-3 are connected to the fourth to sixth vertex nodes 401-4 to 401-6, which are in-phase nodes.

More specifically, the fourth vertex node 401-4 of the second ring oscillator 301-2, which is in phase with the first vertex node 401-1 of the first ring oscillator 301-1, 1 clock bus line 302-1. The fifth vertex node 401-5 of the second ring oscillator 301-2, which is the same as the second vertex node 401-2 of the first ring oscillator 301-1, is connected to the second clock bus line 302-2. Finally, the sixth vertex node 401-6 of the second ring oscillator 301-2, which is in phase with the third vertex node 401-3 of the first ring oscillator 301-1, Lt; RTI ID = 0.0 > 302-3. ≪ / RTI >

In the example of FIG. 4, each of the ring oscillators 301-1 and 301-2 is composed of thirty inverting amplifiers and is used as an oscillator in two different chips. Two oscillator in-phase nodes are connected by three clock bus lines CL. In the system according to the embodiment of the present invention shown in FIG. 3 and FIG. 4, although the difference in voltage supplied to two chips slightly occurs, all the oscillator networks oscillate in the same frequency and phase by three connections.

Hereinafter, experimental results of the embodiment of the present invention will be shown and described.

FIGS. 5 and 6 are diagrams showing clock signals in the absence of clock bus lines in the ring oscillators 301-1 and 301-2, respectively, according to an embodiment of the present invention.

5 shows a clock signal when the same voltage is applied to each of the ring oscillators 301-1 and 301-2, and FIG. 6 shows a case where the voltage applied to the ring oscillators 301-1 and 301-2 is 1% Fig. 2 is a diagram showing a clock signal when the clock signal is supplied. The clock signals of FIGS. 5 and 6 are the result of measuring the signal at the node 13 in FIG.

If the same voltage source is provided to each of the ring oscillators 301-1 and 301-2, which are individually present on two chips as in Fig. 5, the same phase-to-phase frequency will be generated (i.e., no phase difference). In this case, it can be seen that even though the two chips are not connected to the clock line, the two central nodes (node 13 in FIG. 4) are in exactly the same phase.

However, the problem is that there is a difference in the voltage supplied to each chip. 6 shows a state in which a voltage increased by 1% is supplied to the second ring oscillator 301-2 existing in the second chip while the applied voltage of the first ring oscillator 301-1 existing in the first chip is fixed at 3V Lt; / RTI > represents the simulation output waveform in the case of FIG. The larger the voltage swing range on the two different chips, the greater the clock skew range. It can be seen that a phase difference occurs between the two clock signals in the interval of 8 ns to 10 ns.

FIG. 7 is an enlarged view of the clock skew generated in FIG.

It can be confirmed that the phase difference between the first clock signal 701-1 generated in the first ring oscillator 301-1 and the second clock signal 701-2 generated in the second ring oscillator 301-2 occurs .

8 is a table showing a result of measuring a measured clock skew according to a voltage variation when there is no clock bus line. 9 is a table showing a result of measurement of a measured clock skew in accordance with a voltage variation after being connected to a clock bus line.

The table of FIG. 8 shows the results of applying the variation rate from -2% to + 2% to the voltage provided when the in-phase node is not connected to the clock bus line. Referring to FIG. 8, it can be seen that a symmetrical phase difference of 143 ps (22.04% in a cycle) occurs when there is a maximum 2% voltage difference between two chips.

9 is a value measured in a state where two chip in-phase points are connected to the three clock lines 302-1 to 302-3 described above according to the above-described embodiment of the present invention.

When three identical phase points are connected to the clock bus lines 302-1 to 302-3 by the method proposed in the present invention, a symmetrical phase difference of 19.51 ps (2.98% as a cycle) occurs as shown in FIG. 9 do. Therefore, skew is significantly reduced.

FIG. 10 shows an image in which a ring oscillator according to an embodiment of the present invention is laid out in a CMOS (Complementary Metal-Oxide-Semiconductor).

Although the embodiments of the oscillator system according to the present invention have been described above, the present invention is described as at least one embodiment, and the technical idea, structure and operation of the oscillator system of the present invention are not limited thereto. Are not to be limited / limited by the description with reference to the drawings or the drawings. It will also be appreciated by those skilled in the art that the concepts and embodiments of the invention set forth herein may be used as a basis for modifying or designing other structures for carrying out the same purposes of the present invention It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims and their equivalents. And various changes, substitutions, and alterations can be made without departing from the scope of the invention.

Claims (15)

A first oscillator for generating a first clock signal;
A second oscillator for generating a second clock signal; And
The first and second oscillators are configured to have the same structure, and each of the first and second oscillators is composed of a two-dimensional or three-dimensional fractal structure of a plurality of inverting amplifiers,
And a clock bus line connecting a first node on the first oscillator and a second node on a second oscillator in phase with the first node,
The first and second ring oscillators are respectively used as oscillators of two different chips,
The clock bus line includes:
First to third vertex nodes of the first oscillator and third to sixth vertex nodes of the first oscillator and third to sixth vertex nodes of the second oscillator, So that the first oscillator and the second oscillator are synchronized to oscillate at the same frequency and phase by the connection of the three clock bus lines even if there is a difference in voltage supplied to the two chips ,
Oscillator system. The method according to claim 1,
Wherein the fractal structure has a structure in the form of a ring-shaped oscillator including three nodes so as to have a phase difference of 120 [deg.] On the semiconductor chip as a basic unit.
Oscillator system. 3. The method of claim 2,
Wherein the three nodes of the basic unit are formed in a triangular shape by the first to third inverting amplifiers.
Oscillator system. The method of claim 3,
Wherein the three nodes,
A first node formed by connecting an input terminal of the first inverting amplifier and an output terminal of the third inverting amplifier,
A second node formed by connecting an input terminal of the second inverting amplifier and an output terminal of the first inverting amplifier,
And a third node formed by connecting an input terminal of the third inverting amplifier and an output terminal of the second inverting amplifier.
Oscillator system. 3. The method of claim 2,
The fractal structure,
Wherein a plurality of basic units in which three nodes are formed in a triangular shape are repeatedly connected two-dimensionally or three-dimensionally,
Oscillator system. 6. The method of claim 5,
In the fractal structure,
A first term is 1, and a tolerance is 1,
Oscillator system. The method according to claim 6,
Wherein the number of basic units

And n is an integer.
Oscillator system. 6. The method of claim 5,
A second basic unit including first to third basic units,
A node of the first basic unit and a node of the second basic unit are connected to form a fourth node,
A node of the second basic unit and a node of the third basic unit are connected to form a fifth node,
Wherein a node of the third basic unit and a node of the first basic unit are connected to form a sixth node.
Oscillator system. The method according to claim 1,
Wherein the first and second oscillators have the same frequency and the same phase.
Oscillator system. The method according to claim 1,
Characterized in that the fractal structure forms a triangular shape as a whole.
Oscillator system. 11. The method of claim 10,
Characterized in that the first and second ring oscillators forming the fractal structure are each composed of 30 inverting amplifiers.
Oscillator system. delete The method according to claim 1,
Characterized in that the two different chips are connected by at least three clock bus lines.
Oscillator system. The method according to claim 1,
Characterized in that the first and second ring oscillators are laid out in CMOS (Complementary Metal-Oxide-Semiconductor)
Oscillator system. The method according to claim 1,
Wherein the structure of the first and second ring oscillators is an odd number of inverting amplifiers connected in series.
Oscillator system.

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