CN114563693B

CN114563693B - Circuit supporting testability design based on semi-static D trigger

Info

Publication number: CN114563693B
Application number: CN202210455914.1A
Authority: CN
Inventors: 范志军; 李楠; 薛可; 段恋华; 郭海丰
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2022-04-28
Filing date: 2022-04-28
Publication date: 2022-12-16
Anticipated expiration: 2042-04-28
Also published as: CN114563693A

Abstract

The disclosure relates to a circuit supporting design for testability based on a semi-static D flip-flop. Providing a circuit supporting design for testability based on a semi-static D flip-flop, capable of operating in an operating mode or a test mode, comprising: a clock module configured to provide a test clock signal in a test mode; a logic cell comprising a plurality of semi-static D flip-flops, each semi-static D flip-flop comprising a dynamic latch and a static latch coupled in series, wherein a holding clock level of the dynamic latch in each semi-static D flip-flop is a first clock level, in a test mode the plurality of semi-static D flip-flops operate based on a test clock signal, a duration of the first clock level in each clock cycle of the test clock signal satisfies a lowest operating frequency of the dynamic latch, and each semi-static D flip-flop in at least a portion of the semi-static D flip-flops forms at least a portion of a scan register in a scan chain supporting design for testability in the circuit.

Description

Circuit supporting testability design based on semi-static D trigger

Technical Field

The invention relates to a circuit supporting testability design based on a semi-static D trigger and a chip testing method.

Background

Chip manufacturing has yield problems. Design for Test (DFT) is a technology necessary for large-scale chips. The chips with errors can be screened out or classified by DFT. The DFT inserts various hardware logics for improving the testability (including controllability and observability) of the chip into the original design of the chip, thereby making the chip easy to test and greatly saving the cost of chip testing.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a circuit supporting design for testability based on a semi-static D flip-flop, capable of operating in an operating mode or a test mode, the circuit comprising: a clock module configured to provide an operating clock signal in an operating mode and a test clock signal in a test mode; and a logic unit comprising a plurality of semi-static D flip-flops, each semi-static D flip-flop comprising a dynamic latch and a static latch coupled in series, wherein: the holding clock level of the dynamic latch in each semi-static D flip-flop is a first clock level, the holding clock level of the static latch in each semi-static D flip-flop is a second clock level different from the first clock level, and the working clock signal and the test clock signal are both pulse clock signals including the first clock level and the second clock level, in the working mode the plurality of semi-static D flip-flops operate based on the working clock signal, in the test mode the plurality of semi-static D flip-flops operate based on the test clock signal, in each clock cycle of the test clock signal, the duration of the first clock level satisfies the lowest operating frequency of the dynamic latch, and each semi-static D flip-flop in at least part of the semi-static D flip-flops constitutes at least part of a scan register in a scan chain supporting testability design in the circuit.

According to another aspect of the present disclosure, there is provided a chip testing method for testing a chip including a semi-static D flip-flop based design for testability support circuit according to the present disclosure, the method including the steps of: simulating the netlist of the circuit through simulation software for scan test to obtain a test vector sequence and a corresponding reference vector sequence for the scan test; enabling the circuit to work in a test mode, inputting the test vector sequence to the circuit, and obtaining a corresponding result vector sequence; and comparing the result vector sequence with the reference vector sequence so as to judge the performance of the chip.

According to yet another aspect of the present disclosure, an electronic device for implementing the SHA-256 algorithm is provided, including a semi-static D flip-flop based design for testability support circuit according to the present disclosure.

According to yet another aspect of the present disclosure, an electronic device for implementing artificial intelligence algorithms is provided, including a semi-static D flip-flop based design for testability support circuit according to the present disclosure.

The application provides a circuit supporting testability design based on a semi-static D trigger and a corresponding chip testing method by using the semi-static D trigger as a main sequential unit of a System On Chip (SOC)/integrated circuit (ASIC) supporting DFT testing, thereby greatly improving the practicability of the circuit using the semi-static D trigger as a sequential logic unit.

Drawings

A better understanding of the present disclosure may be obtained when the following detailed description of the embodiments is considered in conjunction with the following drawings. The accompanying drawings, which are incorporated in and form a part of the specification, illustrate embodiments of the present invention and, together with the detailed description, serve to explain the principles and advantages of the invention.

Fig. 1A shows a schematic diagram of replacing a normal D flip-flop with a scan register in a scan replacement step.

FIG. 1B shows a schematic diagram of scan registers coupled together to form a scan chain in a scan stitching step.

Fig. 1C shows a circuit configuration of a typical D flip-flop.

FIG. 2A illustrates a block schematic diagram of a semi-static D flip-flop based design for testability enabled circuit according to an embodiment of the present disclosure.

FIG. 2B is a block diagram of one possible implementation of the circuit 100 based on a semi-static D flip-flop supporting design for testability shown in FIG. 2A.

FIG. 2C is a block diagram of another possible implementation of the semi-static D flip-flop based design for testability support circuit 100 shown in FIG. 2A.

Fig. 3A shows a schematic circuit diagram of one specific embodiment of the logic unit 120 shown in fig. 2A, 2B and 2C.

Fig. 3B illustrates an operational schematic diagram of the semi-static D flip-flop in the logic unit 120 shown in fig. 3A, according to an embodiment of the present disclosure.

Fig. 3C illustrates an operating clock signal CLKt and a test clock signal CLKw employed by the logic unit 120 shown in fig. 3A in accordance with an embodiment of the present disclosure.

Fig. 4A and 4B show a logic diagram and truth table of an alternative multiplexer MUX.

Fig. 5 shows a schematic circuit diagram of a specific embodiment of the logic unit 120 shown in fig. 2A, 2B and 2C.

Fig. 6A shows a circuit configuration of one specific embodiment of the clock generation unit 114 shown in fig. 2B and 2C and waveforms of various signals therein.

Fig. 6B shows a circuit configuration of another specific embodiment of the clock generation unit 114 shown in fig. 2B and 2C and waveforms of various signals therein.

Fig. 6C shows a circuit configuration of still another specific embodiment of the clock generation unit 114 shown in fig. 2B and 2C and waveforms of various signals therein.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In some cases, similar reference numbers and letters are used to denote similar items, and thus, once an item is defined in one figure, it need not be discussed further in subsequent figures.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the present disclosure is not limited to the positions, dimensions, ranges, and the like disclosed in the drawings and the like.

Detailed Description

Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the structures and methods herein are shown by way of example to illustrate different embodiments of the structures and methods of the present disclosure. Those skilled in the art will understand, however, that they are merely illustrative of exemplary ways in which the disclosure may be practiced and not exhaustive. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

In a large-scale chip, the main components of a digital circuit are sequential logic units and combinational logic units. The testing process of the combinational logic cell is relatively simple, and usually only a single test vector is needed to detect the target error. The testing process of sequential logic cells is complicated. In most cases, there is no way to rely on only one test vector, but rather a sequence of test vectors is required to ultimately detect the target error.

Scan (Scan) technology can transform a difficult-to-test (differential-to-test) sequential circuit into an easy-to-test (easy-to-test) combinational circuit. The scanning technique mainly comprises two steps. The first step is scan replacement, which replaces the normal registers (e.g., D flip-flops) in the circuit with scan registers (e.g., scan D flip-flops). The second step is scan stitching, which couples the scan registers of the first step together to form a scan chain. Fig. 1A shows a schematic diagram of replacing a normal D flip-flop with a scan register in a scan replacement step. FIG. 1B shows a schematic diagram of scan registers coupled together to form a scan chain in a scan stitching step.

Fig. 1C shows a circuit configuration of a typical D flip-flop 10. As shown in fig. 1C, the D flip-flop 10 includes an inverter 12, a transmission gate 14, a feedback circuit 16, a transmission gate 18, a feedback circuit 20, and an inverter 22. Here, the transmission gate 14 and the feedback circuit 16 constitute a static latch, and the transmission gate 18 and the feedback circuit 20 also constitute a static latch, so that the D flip-flop 10 constituted by two static latches is a static D flip-flop.

Transmission gates

14 and 18 may also be tri-state gates. Also shown in fig. 1C is a circuit for generating gate control signals pc and pcb used in the D flip-flop 10 based on a clock signal clk, which is connected to a supply voltage Vdc and includes inverters T1 and T2.

A D flip-flop that is triggered based on an edge of a clock signal may be composed of two level sensitive latches coupled in series, the two latches being triggered based on different levels of the clock signal. If both latches are static latches, the D flip-flop is a static D flip-flop; if one latch is a static latch and the other is a dynamic latch, then the D flip-flop is a semi-static D flip-flop; if both latches are dynamic latches, the D flip-flop is a dynamic D flip-flop.

Taking fig. 1C as an example, transmission gate 14 constitutes a dynamic latch if feedback circuit 16 is removed, or transmission gate 18 constitutes a dynamic latch if feedback circuit 20 is removed, and accordingly, D flip-flop 10 is a semi-static D flip-flop. If both

feedback circuits

16 and 20 are removed,

transmission gates

14 and 18, respectively, constitute dynamic latches, and accordingly, D flip-flop 10 is a dynamic D flip-flop.

The application provides a circuit supporting design for testability based on a semi-static D trigger.

Fig. 2A illustrates a block schematic diagram of a circuit 100 supporting design for testability based on semi-static D flip-flops, according to an embodiment of the disclosure. The circuit 100 is capable of operating in an operational mode or a test mode and includes a clock module 110 and a logic unit 120. The clock module 110 is capable of providing an operating clock signal in an operating mode and providing a test clock signal in a test mode, and the logic unit 120 is capable of receiving the operating clock signal and the test clock signal from the clock module 110.

FIG. 2B is a block diagram of one possible implementation of the circuit 100 based on a semi-static D flip-flop supporting design for testability shown in FIG. 2A. In some embodiments according to the present disclosure, as shown in fig. 2B, the circuit 100 may include a plurality of logic cells 120. The clock module 110 may include: a phase-locked loop (PLL) module 112, and a clock generation unit 114 coupled to the PLL module, the clock generation unit 114 generating an operating clock signal and a test clock signal for a plurality of logic units 120. The clock generation unit may receive a phase-locked loop clock signal CLKpll from the phase-locked loop PLL module 112, an input clock signal CLKin from outside the circuit 100, and generate an operating clock signal and a test clock signal based on the two signals. In a preferred embodiment, the frequency of the phase-locked loop clock signal CLKpll is higher than the frequency of the input clock signal CLKin.

FIG. 2C is a block diagram of another possible implementation of the semi-static D flip-flop based design for testability support circuit 100 shown in FIG. 2A. In some embodiments according to the present disclosure, as shown in fig. 2C, the circuit 100 may include a plurality of logic cells 120. The clock module 110 may include: a phase-locked loop (PLL) module 112, and a plurality of clock generation units 114 coupled to the PLL module, wherein each clock generation unit 114 generates an operating clock signal and a test clock signal for a corresponding one of the logic units 120. Each clock generation unit may receive a phase-locked loop clock signal CLKpll from the phase-locked loop PLL module 112, an input clock signal CLKin from outside the circuit 100, and generate an operating clock signal and a test clock signal based on the two signals. In a preferred embodiment, the frequency of the phase-locked loop clock signal CLKpll is higher than the frequency of the input clock signal CLKin.

Fig. 3A shows a schematic circuit diagram of one specific embodiment of the logic unit 120 shown in fig. 2A, 2B and 2C. Fig. 3B illustrates an operational schematic diagram of the semi-static D flip-flop in the logic unit 120 shown in fig. 3A, according to an embodiment of the disclosure. Fig. 3C illustrates an operating clock signal CLKw and a test clock signal CLKt employed by the logic unit 120 shown in fig. 3A in accordance with an embodiment of the present disclosure.

As shown in fig. 3A, the logic unit 120 includes a plurality of semi-static D flip-flops DFF1 and DFF2, each of which includes a dynamic Latch1 and a static Latch2 coupled in series.

In some embodiments according to the present disclosure, as shown in fig. 3A, the output of the dynamic latch of each semi-static D flip-flop is coupled to the input of its static latch. In still other embodiments according to the present disclosure, the output of the static latch of each semi-static D flip-flop is coupled to the input of its dynamic latch.

Those skilled in the art will appreciate that the number and arrangement of semi-static D flip-flops illustrated in fig. 3A is for illustration only and is not intended to be limiting, that logic unit 120 according to embodiments of the present disclosure may include any number of semi-static D flip-flops, and that these semi-static D flip-flops may be arranged in any suitable manner. Those skilled in the art will also appreciate that semi-static D flip-flops according to embodiments of the present disclosure may take on a variety of suitable configurations that are now known or that will come in the future.

Referring to fig. 3A and 3C in combination, the holding clock level of the dynamic latch in each semi-static D flip-flop is a first clock level, and the holding clock level of the static latch in each semi-static D flip-flop is a second clock level different from the first clock level. Both the operating clock signal CLKw and the test clock signal CLKt are pulse clock signals including a first clock level and a second clock level. For a level sensitive latch, when the clock signal is at a clock-through level, the latch is in a data-through state, with the output varying with its input, thus enabling input data to pass through the latch; when the clock signal is at the hold clock level, the latch is in a data hold state, and its output does not change with its input, but remains unchanged, thus causing the data at its output to be held.

In the operation mode, the plurality of semi-static D flip-flops DFF1 and DFF2 of the logic unit 120 operate based on the operation clock signal CLKw. In the test mode, the plurality of semi-static D flip-flops DFF1 and DFF2 operate based on the test clock signal CLKt. The duration of the first clock level satisfies the lowest operating frequency of the dynamic latch in each clock cycle of the test clock signal.

The static latch is characterized in that in a data holding state, data held at an output end of the static latch can be always valid; the dynamic latch is characterized in that in a data holding state, data held at an output end of the dynamic latch is gradually degraded until the data is failed. Therefore, the clock signal used by the dynamic latch has a limitation of the lowest operating frequency, and the purpose of the limitation is to prevent the data at the output end of the dynamic latch from being invalid due to the data holding state lasting too long, so as to ensure that the dynamic latch can normally operate. The aforementioned "the duration of the first clock level satisfies the lowest operating frequency of the dynamic latch" may be interpreted as that the duration of the first clock level (i.e., the holding clock level of the dynamic latch) is less than the upper limit of the data holding time of the dynamic latch, thereby enabling the dynamic latch to operate normally without data failure. The definition of the lowest operating frequency of a dynamic latch may be, for example: in the case of ensuring that the dynamic latch operates normally, the duty cycle that can be used is the lowest frequency of the 50% clock signal, in which case the upper limit of the data retention time of the dynamic latch is half the clock period corresponding to the lowest operating frequency.

In embodiments according to the present disclosure, the operating clock signal CLKin of the circuit 100 is typically high in frequency, with a frequency greater than or equal to the lowest operating frequency of the dynamic latches, and may have a duty cycle of 50%, for example.

In embodiments consistent with the present disclosure, the frequency of the test clock signal CLKi of circuit 100 is typically low, which may be less than the minimum operating frequency of the dynamic latch, so that if a 50% duty cycle is employed, the duration of the first clock level (i.e., the holding clock level of the dynamic latch) will exceed the upper limit of the data holding time of the dynamic latch. Thus, the duty cycle of the test clock signal employed by the circuit 100 according to embodiments of the present disclosure is not 50%. If the first clock level is high and the second clock level is low, the duty cycle of the test clock signal is much less than 50%, which is the case in FIG. 3C; if the first clock level is low and the second clock level is high, the duty cycle of the test clock signal is much greater than 50%. The purpose of this setting of the test clock signal is to: although the frequency of the test clock signal is less than the lowest operating frequency of the dynamic latch, the duty cycle of the test clock signal is adjusted so that the first clock level in each cycle of the test clock signal (i.e., the retention clock level of the dynamic latch) satisfies the lowest operating frequency of the dynamic latch, i.e., so that the duration of the first clock level in each cycle is less than or equal to the upper limit of the data retention time of the dynamic latch, thereby ensuring that the semi-static D flip-flop can operate properly under the test clock signal.

FIG. 3B shows the state of the static Latch Latch2, the dynamic Latch Latch3 and the static Latch Latch4 of FIG. 3A in a test mode, the solid line indicates that the Latch is in the data holding state in the current period, the dotted line indicates that the Latch is in the data penetrating state in the current period, and the arrow indicates the transfer direction of the data. The states of the static latches Latch2 and Latch4 and the dynamic Latch3 correspond to the test clock signal CLKt. As shown in fig. 3B, for the dynamic Latch3, the dotted line representing the data penetration state is longer, and the solid line representing the data holding state is shorter, so as to satisfy the lowest operating frequency of the dynamic Latch. For the static latches Latch2 and Latch4, the dotted line representing the data penetration state is shorter, and the solid line representing the data holding state is longer. Since the data retention state of the static latch can in principle last for an infinite time, the static latch can still operate normally, so that the entire semi-static D flip-flop can operate normally under the test clock signal CLKt.

In some embodiments according to the present disclosure, as shown in fig. 3C, the first clock level (i.e., the holding clock level of the dynamic latch) is a high level and the second clock level is a low level. In still other embodiments according to the present disclosure, the first clock level is a low level and the second clock level is a high level.

With continued reference to fig. 3A-3C, it is shown that each of the at least partially semi-static D flip-flops forms at least part of a scan register in a scan chain supporting design for testability in the circuit 100.

In some embodiments according to the present disclosure, the logic unit 120 may further include: at least one multiplexer, each multiplexer together with a respective one of the aforementioned at least partially semi-static D flip-flops for constituting the scan chain constituting the scan register. As shown in fig. 3A, the semi-static D flip-flop DFF2 and the multiplexer MUX together form a scan register.

In a preferred embodiment, as shown in fig. 3A, each multiplexer MUX is a two-select multiplexer, which may comprise a first input coupled to the data signal D to be received in the active mode, a second input for receiving the scan input signal SI, and a select input for receiving the scan enable signal SE. The logic diagram and truth table of the alternative multiplexer MUX are shown in fig. 4A and 4B.

Those skilled in the art will appreciate that the structure of the scan register formed by the multiplexer MUX and the semi-static D flip-flop DFF2 shown in fig. 3A is for illustration only and is not intended to be limiting, and that the scan register formed by the participation of the latch DFF2 may also take any structure that is known now or may come in the future, e.g., the multiplexer and the semi-static D flip-flop are not separate but are fused together, etc.

In some embodiments according to the present disclosure, in the logic unit 120, one or more of the aforementioned at least some of the semi-static D flip-flops for constituting the scan chain constitute a scan register in the scan chain in which the multiplexer is omitted.

The scan register may be formed by a multiplexer MUX and a register, which may be, for example, a D flip-flop. In scan registers, the inputs of the multiplexer MUX are usually connected to different locations for receiving different inputs, respectively, for example, an input signal to be received in the operating mode and an input signal to be received in the scan chain. In circuit 100, it may be that multiple inputs of the multiplexer MUX of the scan register are connected to the same location, in which case the multiplexer may be omitted, thereby forming the scan register with the multiplexer omitted as described above.

In a preferred embodiment, how the multiplexers are arranged in the circuit to form the scan chain requires certain rules to be followed, such as:

rule 1, default, add a multiplexer before each register (e.g., D flip-flop), but there are some special cases where the multiplexer can be omitted;

rule 2, the scan-in signal SI of the multiplexer must come from the output of another register (e.g., D flip-flop) and not from the combinational logic circuit;

rule 3, when there is combinational logic at the input of a register (e.g., a D flip-flop), a multiplexer must be set before the register;

rule 4, on the basis of satisfying the aforementioned rules 2-3, if there are multiple inputs of the multiplexer MUX connected to the same location, the multiplexer can be omitted, except for the following cases: if the inputs of a plurality of registers, e.g. D flip-flops, are connected to the same location, only at most one of the plurality of registers can omit the multiplexer.

Those skilled in the art will appreciate that the rules described above are for illustration only and are not intended to be limiting, and that the circuit 100 according to embodiments of the present disclosure may follow any rule known in the art or that may occur in the future for setting multiplexers in circuits to form scan chains, as desired. Those skilled in the art will also appreciate that the manner in which the multiplexers are provided shown in fig. 3A is by way of illustration only and is not intended to be limiting, and that in a circuit 100 according to embodiments of the present disclosure, multiplexers may or may not be provided before any semi-static D flip-flops, as desired.

Although the adoption of the all-static D flip-flop can avoid the limitation of the lowest working frequency of the dynamic D flip-flop, the area and the power consumption of the all-static D flip-flop are large. Dynamic D flip-flops, in contrast, are limited by the lowest operating frequency, although they are small in area and power consumption. Dynamic D flip-flops have difficulty supporting design for testability because the test clock signal generally cannot have a high frequency. The circuit 100 according to the embodiment of the present disclosure uses the semi-static D flip-flop as a main sequential logic unit, and utilizes the characteristic that the data retention time of the static latch is not limited, and by adjusting the duty ratio of the test clock signal with relatively low frequency, it is ensured that the time for the dynamic latch to retain data in each clock cycle satisfies the limitation of the minimum operating frequency, so that a circuit supporting testability design is formed by using the semi-static D flip-flop as a main sequential logic unit, and compared with a circuit supporting testability design using the static D flip-flop, the area and power consumption are greatly saved.

Fig. 5 shows a schematic circuit diagram of a specific embodiment of the logic unit 120 shown in fig. 2A, 2B and 2C. For the sake of clarity, the circuit structure of the logic unit and the clock signal CLK are shown in fig. 5, without showing a specific clock block. Those skilled in the art will appreciate that the logic unit 120 shown in fig. 5 is a specific embodiment of the logic unit 120 shown in fig. 2A, 2B, and 2C, and is a variation of the computing unit 120 shown in fig. 3A, and therefore, the foregoing description with respect to fig. 2A through 3C is applicable to the logic unit 120 shown in fig. 5.

As shown in fig. 5, the logic unit 120 may include a plurality of semi-static D flip-flops DFF1 to DFF5, and the clock signal CLK may be an operating clock signal or a test clock signal. According to the aforementioned rules for forming the scan chain, since the inputs of the semi-static D flip-flops DFF2 and DFF3 are each provided with combinational logic, both of the semi-static D flip-flops together with the corresponding multiplexer MUX form the scan register. Since the semi-static D flip-flops DFF1, DFF4 and DFF5 each satisfy the aforementioned rules 2-4 for forming the scan chain, the scan registers of the multiplexers in the respective constituent scan chains are omitted.

Those skilled in the art will appreciate that the manner in which the multiplexers are provided shown in fig. 5 is for illustration only and is not intended to be limiting, and that in a circuit 100 according to embodiments of the present disclosure, multiplexers may or may not be provided before any semi-static D flip-flops as desired.

As shown in fig. 6A, the clock generation unit 114 receives a phase-locked loop clock signal CLKpll from the phase-locked loop PLL module and an input clock signal CLKin from outside the circuit 100, wherein an operating frequency of the phase-locked loop clock signal CLKpll is greater than or equal to a lowest operating frequency of the dynamic latches. For example, the frequency of the PLL clock signal CLKpll is 100MHz, and the lowest operating frequency of the dynamic latch is also 100MHz. The input clock signal CLKin sequentially passes through the 3D flip-flops to generate three signals Delay1, delay2, and Delay3 with gradually increasing delays, and the Delay3 signal also passes through the inverter to generate its inverted signal Delay3_ inv. By performing an AND operation on the signal Delay2, the signal Delay3, AND the pll (data participating in the AND operation is indicated by a circle in fig. 6A) by using the three-input AND gate AND3, the test clock signal CLKt having the same frequency as the input clock signal CLKin AND the same pulse width as the pll can be obtained. The control signals BYPASS and TEST are used to control the multiplexers MUX respectively so that the generated TEST clock signal CLKt reaches the output through both multiplexers MUX.

As shown in fig. 6B, the clock generation unit 114 receives a phase-locked loop clock signal CLKpll from the phase-locked loop PLL module and an input clock signal CLKin from outside the circuit 100, wherein an operating frequency of the phase-locked loop clock signal CLKpll is greater than or equal to a lowest operating frequency of the dynamic latches. For example, the frequency of the PLL clock signal CLKpll is 100MHz, and the lowest operating frequency of the dynamic latch is also 100MHz. The input clock signal CLKin sequentially passes through the two D flip-flops to generate two signals Delay1 and Delay2 with gradually increasing delays. The clock generation unit also includes a multi-bit D flip-flop Multibit DFF serving as a counter, and the signal Delay2 serves as its reset signal. In the reset state, the count value CNT at the output terminal of the multi-bit D flip-flop Multibit DFF is cleared, and in addition, the count value CNT is +1 at each cycle of the pll clock signal CLKpll. The count value CNT is input to the comparator COM, and if the count value CNT = N (N is a positive integer set in advance), the Flag signal is high. The signal Flag AND the pll clock signal CLKpll are AND-operated by the two-input AND gate AND2 (data participating in the AND-operation is marked with a circle in fig. 6B), AND the test clock signal CLKt having the same pulse width as the pll clock signal CLKpll can be obtained. The control signals BYPASS and TEST are used to control the multiplexers MUX respectively so that the generated TEST clock signal CLKt reaches the output through both multiplexers MUX.

As shown in fig. 6C, the clock generation unit 114 receives a phase-locked loop clock signal CLKpll from the phase-locked loop PLL module and an input clock signal CLKin from outside the circuit 100, wherein an operating frequency of the phase-locked loop clock signal CLKpll is greater than or equal to twice the lowest operating frequency of the dynamic latch. For example, the frequency of the PLL clock signal CLKpll is 200MHz, and the lowest operating frequency of the dynamic latch is 100MHz. The input clock signal CLKin sequentially passes through the 3D flip-flops to generate three signals Delay1, delay2, and Delay3 with gradually increasing delays, and the Delay3 signal also passes through the inverter to generate its inverted signal Delay3_ inv. By performing an AND operation on the signal Delay2 AND the signal Delay3_ inv through the two-input AND gate AND2 (data participating in the AND operation is indicated by a circle in fig. 6C), the test clock signal CLKt having the same frequency as the input clock signal CLKin AND the same pulse width as the clock period of the pll clock signal CLKpll (or twice the pulse width of the pll clock signal CLKpll) can be obtained. The control signals BYPASS and TEST are used to control the multiplexers MUX respectively so that the generated TEST clock signal CLKt reaches the output through both multiplexers MUX.

Those skilled in the art will appreciate that the specific structure of the clock generation unit 114 in fig. 6A to 6C is merely used as an illustration and is not intended to be limiting, and that the clock generation unit 114 according to the embodiments of the present disclosure may also adopt any other suitable structure.

According to an embodiment of the present disclosure, there is also provided a chip testing method for testing a chip including the semi-static D flip-flop based design for testability support circuit 100 as described in the foregoing. The method comprises the following steps:

step S1: simulating the netlist of the circuit 100 by simulation software for scan test to obtain a test vector sequence and a corresponding reference vector sequence for scan test;

step S2: enabling the circuit 100 to work in a test mode, inputting a test vector sequence to the circuit, and obtaining a corresponding result vector sequence;

and step S3: and comparing the result vector sequence with the reference vector sequence so as to judge the performance of the chip.

There is also provided, in accordance with an embodiment of the present disclosure, an electronic device for implementing the SHA-256 algorithm, including the semi-static D flip-flop based design for testability support circuit 100 as described in the foregoing.

There is also provided, in accordance with an embodiment of the present disclosure, an electronic device for implementing an artificial intelligence algorithm, including a semi-static D flip-flop based design for testability support circuit 100 as described in the foregoing.

The design for testability support circuit based on semi-static D flip-flop and the chip test method of the present disclosure have been described above with reference to specific embodiments. However, it is to be understood that any feature of any one embodiment may be combined with and/or substituted for any other feature of any other embodiment.

Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, components of consumer electronics, electronic test equipment, cellular communication infrastructure such as base stations, and the like. Examples of electronic devices may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headsets, telephones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal Digital Assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereos, DVD players, CD players, digital music players such as MP3 players, radios, camcorders, cameras such as digital cameras, portable memory chips, washing machines, dryers, washer/dryers, peripherals, clocks, and so forth. Further, the electronic device may comprise an incomplete product.

The terms "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" that is to be replicated accurately. Any implementation exemplarily described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.

As used herein, the term "substantially" is intended to encompass any minor variation resulting from design or manufacturing imperfections, device or element tolerances, environmental influences and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitics, noise, and other practical considerations that may exist in a practical implementation.

In addition, the foregoing description may refer to elements or nodes or features being "coupled" or "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element \ node \ feature is electrically, mechanically, logically, or otherwise directly coupled to (or in direct communication with) another element \ node \ feature. Similarly, unless expressly stated otherwise, "coupled" means that one element \ node \ feature may be mechanically, electrically, logically or otherwise joined to another element \ node \ feature in a direct or indirect manner to allow interaction, even though the two features may not be directly coupled. That is, to "couple" is intended to include both direct and indirect coupling of elements or other features, including coupling with one or more intermediate elements.

In addition, "first," "second," and like terms may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.

In this disclosure, the term "providing" is used broadly to encompass all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing," "preparing \ manufacturing," "arranging \ setting," "installing \ assembling," and \ or "ordering" the object, and the like. Furthermore, conditional language, e.g., "may," e.g., "such as" and the like, as used herein are generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or states, unless expressly stated otherwise or otherwise understood in the context of such usage. Thus, such conditional language is not generally intended to imply that features, elements, and/or states are in any way required for one or more embodiments or are included or performed in any particular embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The various features and processes described above may be implemented independently of one another or may be combined in various ways. All suitable combinations and subcombinations of the features of the disclosure are intended to be within the scope of the disclosure.

Claims

1. A circuit supporting design for testability based on semi-static D flip-flops, capable of operating in an operational mode or a test mode, the circuit comprising:

a clock module configured to provide an operating clock signal in an operating mode and a test clock signal in a test mode; and

a logic cell comprising a plurality of semi-static D-flip-flops, each semi-static D-flip-flop comprising a dynamic latch and a static latch coupled in series, wherein:

the retention clock level of the dynamic latch in each semi-static D flip-flop is a first clock level, the retention clock level of the static latch in each semi-static D flip-flop is a second clock level different from the first clock level, and the operational clock signal and the test clock signal are both pulsed clock signals comprising a first clock level and a second clock level,

in an operating mode, the plurality of semi-static D flip-flops operate based on an operating clock signal,

in a test mode, the plurality of semi-static D flip-flops operate based on a test clock signal, a duration of a first clock level in each clock cycle of the test clock signal satisfying a lowest operating frequency of the dynamic latch,

each of the at least partially semi-static D flip-flops forms at least part of a scan register in a scan chain supporting design for testability in the circuit, an

The clock module comprises a phase-locked loop (PLL) module and at least one clock generation unit, each clock generation unit generates a test clock signal for at least one logic unit based on a PLL clock signal from the PLL module and an input clock signal, and the working frequency of the PLL clock signal is greater than or equal to the lowest working frequency of the dynamic latch.

2. The circuit of claim 1, wherein:

in each clock cycle of the test clock signal, the duration of the first clock level is less than or equal to an upper limit of a data retention time of the dynamic latch, the upper limit of the data retention time being half of a clock cycle corresponding to a lowest operating frequency of the dynamic latch.

3. The circuit of claim 1, wherein:

the frequency of the working clock signal is greater than or equal to the lowest working frequency of the dynamic latch; and

the duty cycle of the operating clock signal is about 50%.

4. The circuit of claim 1, wherein the logic unit further comprises:

at least one multiplexer, each multiplexer together with a respective one of the at least partially semi-static D flip-flops forming a scan register in the scan chain.

5. The circuit of claim 4, wherein:

one or more of the at least partially semi-static D flip-flops form a scan register in the scan chain from which a multiplexer is omitted.

6. The circuit of any of claims 1-5, wherein, in each semi-static D flip-flop:

an output of the dynamic latch is coupled to an input of the static latch; or

An output of the static latch is coupled to an input of the dynamic latch.

7. The circuit of any of claims 1-5, wherein:

the circuit comprises a plurality of logic cells; and

the at least one clock generation unit of the clock module comprises:

a plurality of clock generation units coupled to the PLL module, each of the clock generation units generating an operating clock signal and a test clock signal for a corresponding one of the logic units, or

A clock generation unit coupled to the PLL module, the clock generation unit generating an operating clock signal and a test clock signal for the plurality of logic units.

8. A chip testing method for testing a chip including the semi-static D flip-flop based design-for-testability supporting circuit of any one of claims 1 to 7, the method comprising the steps of:

simulating the netlist of the circuit by simulation software for scan test to obtain a test vector sequence and a corresponding reference vector sequence for the scan test;

enabling the circuit to work in a test mode, inputting the test vector sequence to the circuit, and obtaining a corresponding result vector sequence; and

and comparing the result vector sequence with the reference vector sequence so as to judge the performance of the chip.

9. An electronic device for implementing the SHA-256 algorithm, comprising the semi-static D flip-flop based design-for-testability support circuit of any of claims 1-7.

10. An electronic device for implementing artificial intelligence algorithms, comprising a semi-static D flip-flop based design for support of testability circuit according to any of claims 1-7.