KR101878075B1 - Test Socket of Fan-Out Type Semiconductor Device - Google Patents

Abstract

An embodiment of the present invention is a liquid crystal display device having a first surface and a second surface opposite to the first surface, the first surface having a first region and a second region disposed outside the first region, A base layer having an external connection pad formed on the second surface at a pitch corresponding to the electrode terminal of the test board; A plurality of circuit patterns formed in the base layer and rearranged at a pitch corresponding to the external connection pads; A plurality of electrode patterns formed in the second region so as to be electrically connected to the circuit patterns and external connection terminals of the semiconductor device, the electrode patterns being arranged at a pitch corresponding to the external connection terminals; An elastic layer surrounding the electrode pattern so that a part of the electrode pattern is exposed; And a capacitance pad formed in the first region and electrically connected to the external connection pad and the electrode pattern via the circuit pattern.

Description

[0001] The present invention relates to a test socket for a fan-out type semiconductor device,

The present invention relates to a semiconductor device test socket for checking electrical reliability of a semiconductor device.

After the semiconductor device is manufactured, various tests are performed to confirm the reliability of the product. For example, an electrical characteristic test in which all the input / output terminals of a semiconductor device are connected to an inspection signal generating circuit to check whether normal operation and disconnection are performed, and some input / output terminals such as a power input terminal of a semiconductor device are connected to an inspection signal generating circuit, There is a burn-in test in which a stress is applied by a higher temperature, a voltage and a current to check the lifetime of a semiconductor device and whether a defect has occurred.

Usually, the reliability test is carried out while the semiconductor device is mounted on the test socket. The shape of the test socket is basically determined according to the shape of the semiconductor device and serves as an intermediary for connecting the semiconductor device with the inspection equipment by physical or electrical contact between the external connection terminal of the semiconductor device and the electrode of the test socket.

In order to carry out this test process, a pogo pin type test socket was used to test a semiconductor device. However, the pogo pin may damage the external connection terminal of the semiconductor device, It is possible to cause a phenomenon in which the signal flow between the inspection equipment is not smooth.

In addition, in accordance with recent trends in the electronics industry, there is a demand for a semiconductor device having a light weight, miniaturization, high speed, high performance, and high reliability. Accordingly, a test socket capable of meeting a fine pitch is required. However, Test sockets are limited in this respect.

The solder balls of the BGA package are brought into contact with the socket pins in a pogo pin contact manner. However, the contact resistance varies greatly depending on the contact degree of the pogo pin with respect to the solder ball. For example, the contact resistance is varied from tens of mΩ to several hundreds of mΩ. The above problem is a fundamental problem caused by the characteristics of the pogo pin itself which performs soft contact inside the pogo pin. Such contact resistance acts as a noise in the test process and acts as a factor to lower the high frequency signal transmission characteristics.

Korea Registration Office 20-0327630

The present invention provides a semiconductor device test socket capable of improving the test reliability by performing electrical connection between the semiconductor device and the tester by physical and electrical contact.

The present invention also provides a semiconductor device test socket formed in a fan-out shape so as to be able to correspond to a fine pitch of external connection terminals of a semiconductor device.

The objects of the present invention are not limited to those described above, and other objects and advantages of the present invention which are not mentioned can be understood by the following description.

A test socket for a semiconductor device according to an embodiment of the present invention has a first surface having a first region and a second region disposed outside the first region and a second surface opposing the first surface, A base layer having an external connection pad formed on the second surface at a pitch corresponding to an electrode terminal of the test board; A plurality of circuit patterns formed inside the base layer so as to be partially exposed to the first surface of the base layer and rearranged at a pitch corresponding to the external connection pad; A plurality of electrode patterns formed in the second region so as to be electrically connected to the circuit patterns and external connection terminals of the semiconductor device, the electrode patterns being arranged at a pitch corresponding to the external connection terminals; An inner fence and an outer fence respectively disposed on the outer side of the first region and the inner side of the second region; A capacitance pad provided inside the inner fence and electrically connected to the external connection pad and the electrode pattern via the circuit pattern; And an elastic layer surrounding the capacitor pad, the inner fence, and the outer fence and surrounding the electrode pattern so that a part of the electrode pattern is exposed.

In an embodiment of the present invention, the material of the base layer may be polyimide.

In the embodiment of the present invention, the circuit pattern may include a first circuit pattern to be relocated to be electrically connected to the external connection pad, a first circuit pattern to be electrically connected to the first circuit pattern and the electrode pattern, And a second circuit pattern exposed on one side.

The electrode pattern may include a first electrode pattern electrically connected to the circuit pattern, a second electrode pattern in the form of a beam electrically connected to the first electrode pattern, a second electrode pattern electrically connected to the first electrode pattern, A third electrode pattern electrically connected to the third electrode pattern, and a fourth electrode pattern electrically connected to the third electrode pattern and exposed in the form of a beam on the upper surface of the elastic layer.

In an embodiment of the present invention, the material of the elastic layer includes at least one of PDMS (polydimethylsiloxane), polyurethane (PU), polyurethane acrylate (PUA), silicone rubber, and PMMA (polymethylmethacrylate) can do.

In an embodiment of the present invention, the pitch between the external connection pads may be larger than the pitch between the electrode patterns.

In an embodiment of the present invention, the apparatus may further include a first sub-fence disposed on the inner side of the inner fence and a second sub-fence disposed on the outer side of the inner fence.

In an embodiment of the present invention, the first sub-fence and the second sub-fence may each have a height lower than the height of the inner fence.

In the embodiment of the present invention, the inner support fence further includes a plurality of inner support fences connecting the inner fence, the first sub-fence, and the second sub-fence, As shown in Fig.

According to an embodiment of the present invention, a plurality of outer support fences may be formed on the lower portion of the outer fence so as to extend to the inner side and the outer side of the outer side fence.

In the embodiment of the present invention, the height of the inner fence and the outer fence may be lower than the height of the electrode pattern.

In an embodiment of the present invention, a plurality of the capacitance springs may be formed along the inner circumference of the inner fence.

According to an embodiment of the present invention, the base layer may further include a frame portion formed outside the second region, and a bonding portion may be protruded from the frame portion.

In an embodiment of the present invention, the edge of the frame portion may be provided with a lift-off pattern for lift-off of the test socket.

In an embodiment of the present invention, the lift-off pattern may be provided with a dummy pattern that can be removed after the lift-off of the test socket.

According to another aspect of the present invention, there is provided a method of manufacturing a test socket, comprising: preparing a substrate; An external connection pad forming step of forming a plurality of external connection pads on the bottom surface of the substrate; A circuit pattern forming step of forming a base layer on the substrate and rearranging the circuit pattern for electrical connection with the external connection pad to the base layer; An electrode pattern forming step of forming an electrode pattern on the base layer so as to be electrically connected to the circuit pattern and the external connection terminal of the semiconductor element; A capacitor pad forming step of forming a capacitance pad to be electrically connected to the circuit pattern and the electrode pattern; A fence forming step of forming an inner fence and an outer fence inside and outside the electrode pattern, respectively; And forming an elastic layer covering the electrode pattern between the inner fence and the outer fence so that a part of the electrode pattern is exposed to the outside of the elastic layer.

In the embodiment of the present invention, the circuit pattern forming step may include: a first circuit pattern forming step of forming a first circuit pattern on the first base layer so as to correspond to an interval between external connection pads; And a second circuit pattern forming step of forming a second circuit pattern on the second base layer so as to be electrically connected to the first circuit pattern.

In an embodiment of the present invention, the base layer may be prepared by applying a liquid polyimide material and then curing it.

According to an embodiment of the present invention, the electrode pattern forming step includes: a first electrode pattern forming step of forming a first electrode pattern electrically connected to the circuit pattern; A second electrode pattern forming step of forming a second electrode pattern electrically connected to the first electrode pattern; A third electrode pattern forming step of forming a third electrode pattern electrically connected to the second electrode pattern; And a fourth electrode pattern forming step of forming a fourth electrode pattern electrically connected to the third electrode pattern and exposed on the upper surface of the elastic layer.

In an embodiment of the present invention, in the elastic layer forming step, the elastic layer may be formed to seal the capacitance pad.

According to the embodiment of the present invention, it is possible to stably test a semiconductor device in which wiring or the like is implemented at a fine pitch, and to prevent signal delay or distortion in testing a high-frequency device requiring high-speed operation.

It should be understood that the effects of the present invention are not limited to the above effects and include all effects that can be deduced from the detailed description of the present invention or the configuration of the invention described in the claims.

1 is a plan view of a test socket according to a first embodiment of the present invention.
2 is a cross-sectional view taken along the line "A-A '" in FIG.
3A to 3G are cross-sectional views sequentially illustrating steps of manufacturing a base layer and a circuit pattern in a method of manufacturing a test socket according to the first embodiment of the present invention.
4A to 4Q are cross-sectional views sequentially illustrating an electrode pattern and an elastic layer manufacturing process in a method of manufacturing a test socket according to the first embodiment of the present invention.
5 is a sectional view of a test socket according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Also, when an element is referred to as "comprising ", it means that it can include other elements, not excluding other elements unless specifically stated otherwise.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view of a test socket according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line "A-A '" in FIG.

1 and 2, a semiconductor device test socket 100 according to a first embodiment of the present invention includes a base layer 110 mounted on a test board electrically connected to semiconductor testing equipment, a base layer 110, A plurality of electrode patterns 130 formed on the base layer 110, an elastic layer 140 for elastically supporting the electrode patterns 130, and an elastic layer 140 for supporting the elastic layer 140 And includes an inner fence 150 and an outer fence 160.

The base layer 110 has a first surface 110a and a second surface 110b opposite to the first surface and may be substantially rectangular in plan view. The electrode pattern 130 and the elastic layer 140 may be formed on the first surface 110a and the second surface 110b may be seated on a test board (not shown).

The base layer 110 may be formed of, for example, a ceramic material or a polyimide (PI) material. When the base layer 110 is manufactured using the ceramic material, the manufacturing time of the base layer 110 is increased and the cost burden may be increased due to the expensive ceramic material. Accordingly, in one embodiment, it is preferable to form the base layer 110 using a polyimide (PI) material that can achieve performance similar to that of a ceramic material while reducing manufacturing time and cost. Polyimide (PI) is a generic name of a heat-resistant resin having an imide bond (-CO-NR-CO-) in its main chain. Such a polyimide (PI) material is characterized by high heat resistance, The characteristics are not aged. In addition, the ceramic material may have a thermal expansion coefficient different from that of the semiconductor wafer, which makes it difficult to match the base layer 110 to a semiconductor wafer. However, the polyimide (PI) material overcomes the above- .

The first surface 110a of the base layer 110 includes a first region I, a second region II formed on the outer side of the first region, and a third region III formed on the outer side of the second region 110a Can be distinguished. The first region I is a rectangular portion approximately at the center of the base layer 110. A plurality of capacitance pads 170 may be formed around the periphery of the first region, that is, the inner periphery of the inner fence described later. Capacitance pad 170 may be, for example, a power pad or a ground pad. The capacitor pad 170 may be electrically connected to the external connection pad 114 via the circuit pattern 120 and may be electrically connected to the electrode pattern 130 through the internal fence 150. The second region II is a portion where the external connection terminal of the semiconductor element for testing is contacted, and a plurality of the electrode patterns 130 and the elastic layer 140 may be formed. The plurality of electrode patterns 130 may be formed at regular intervals or at irregular intervals. The third region III may have a configuration that can be mounted on the test board as a rim portion of the test socket.

A plurality of external connection pads 114 may be formed on the second surface 110b of the base layer 110. [ Each of the external connection pads 114 may be electrically connected to the circuit pattern 120 and the electrode terminals of the test board. The external connection pads 114 may be arranged at regular intervals or irregular intervals.

On the other hand, a frame portion 113 is formed on the outside of the third region III of the base layer, that is, the outside fence described later, to be adhered and fixed when it is coupled with the test board. If the area of the frame part 113 is large, there is a fear that warping may occur at the time of lift off after completion of the manufacture of the test socket. Therefore, the area of the frame part 113 should be designed as narrow as possible to minimize the occurrence of warpage. At this time, a bonding portion 113a for securing a sufficient bonding area with the test board may be formed on the frame portion 113 to protrude outward. A lift-off pattern 114 for lift-off is formed at the edge of the frame section 113 and an alignment mark 114a for alignment with the test board may be formed in each lift-off pattern 114. [ At this time, when the lift-off pattern 114 is used to lift-off the test socket, the lift-off pattern 114 may be warped, which may cause alignment problems with the test board. Accordingly, a dummy pattern 115 is formed in any one of the lift-off patterns, and the dummy pattern 115 can be formed to be removable when warping occurs after lift-off.

A plurality of conductive circuit patterns 120 may be formed in the base layer 110 by the MEMS method. The circuit pattern 120 may be electrically connected to the electrode pattern 130 and the external connection terminal of the semiconductor device. The plurality of circuit patterns 120 may be formed at regular intervals or irregular intervals.

Each of the circuit patterns 120 includes a first circuit pattern 121 formed inside the base layer 110 and electrically connected to the external connection pad 114, And the second end may be exposed on the base layer 110 and electrically connected to the electrode pattern 130. [ The first circuit pattern 121 is relocated so that the fine pitch external connection terminal of the semiconductor device is connected to the electrode terminal on the universal test board. The arrangement and position of the first circuit patterns 121 can be variously changed depending on the position, structure, etc. of the external connection terminals of the semiconductor device to be tested. The first circuit pattern 121 may be formed of a conductive metal such as Cu or Au and the second circuit pattern 122 may be formed of Ni or Ni-Co for connection and support with the electrode pattern 130 have.

The electrode patterns 130 are formed on the first surface 110a of the base layer 110 and may be formed of a conductive material so as to be electrically connected to the circuit patterns 120 and the external connection terminals of the semiconductor devices, As shown in FIG. The plurality of electrode patterns 130 may be formed at regular intervals or irregular intervals.

Each of the electrode patterns 130 includes a first electrode pattern 131 electrically connected to the circuit pattern 120 and a second electrode pattern 131 electrically connected to the first electrode pattern 131 and formed in a beam shape, The third electrode pattern 133 electrically connected to the second electrode pattern 132 and the fourth electrode pattern 133 electrically connected to the third electrode pattern 133 and exposed on the upper surface of the elastic layer 140, And an electrode pattern 134. The external connection terminal of the semiconductor element to be tested can be physically or electrically contacted to the surface of the fourth electrode pattern 134. [ Nickel (Ni), nickel-cobalt alloy (Ni-Co), or the like may be used as the conductive material used for the electrode pattern 130 to provide a stable function against external factors such as oxidation. In one embodiment, the electrode pattern 130 is configured to have a substantially "d" -shaped cross section including the first to fourth electrode patterns, but if necessary, the shape of the electrode pattern 130 may be changed to a " can do.

The electrode pattern 130 is formed by sealing with the elastic layer 140 except for a part thereof. That is, the first to third electrode patterns may be sealed by the elastic layer 140, and the fourth electrode pattern 134 may be exposed to the outside of the elastic layer 140 to be electrically connected to the external connection terminals of the semiconductor device . The elastic layer 140 may have a height equal to the height of the inner fence and the outer fence described later and the height of the elastic layer 140 may correspond to the bottom of the fourth electrode pattern 134.

The elastic layer 140 may be formed of a material capable of imparting an elastic force to the electrode pattern such as PDMS (polydimethylsiloxane), polyurethane (PU), poly Various synthetic rubbers and resins such as urethane acrylate (PUA), silicone rubber, and PMMA (polymethylmethacrylate) can be used. Therefore, when the electrode pattern and the external connection terminal of the semiconductor element are brought into contact with each other for the purpose of testing, the damage of the external connection terminal can be minimized and the test reliability can be improved. That is, when the external full-speed terminal of the semiconductor device moved by the external pressure comes into contact with the electrode pattern, the external connection terminal comes into surface contact with the fourth electrode pattern 134 and is elastically supported by the elastic layer 140, It is possible to minimize the damage that may occur to the terminal.

The pitch between the external connection pads 114 and the adjacent external connection pads 114 may be larger than the pitch between the electrode patterns and the adjacent electrode patterns. That is, since the electrode patterns are formed at pitches corresponding to the external connection terminals of the semiconductor device for realizing miniaturization and miniaturization, it is possible to directly connect the electrode patterns to the test board, thereby limiting the test. Therefore, the reliability of the semiconductor device can be tested by rearranging the external connection pads 114 so as to have a pitch larger than the pitch between the electrode patterns corresponding to the electrode terminals of the test board.

The inner fence 150 and the outer fence 160 are disposed inside and outside the elastic layer 140 to stably support the elastic layer 140. The inner fence 150 and the outer fence 160 may be made of, for example, Ni, a Ni-Co alloy, or the like.

The inner fence 150 may be formed between the first region I and the second region II of the base layer 110. [ The inner fence 150 may have a height lower than the height of the electrode pattern 130. For example, the upper end of the inner fence 150 may be formed to have the same height as the second electrode pattern 134.

In order to increase the contact area with the elastic layer to be described later and to strengthen the elastic layer, the inner fence 150 includes a first sub-fence 151 and a second sub-fence 152 spaced from each other on the inner side and the outer side . For example, the first sub fence 151 and the second sub fence 152 may be formed symmetrically with respect to the inner fence 150. The first sub-fence 151 and the second sub-fence 152 may be formed to be lower than the height of the inner fence 150. The inner fence 150 and the first sub fence 151 are connected to each other by a plurality of connection fences 153 and the inner fence 150 and the second sub fence 152 are connected to each other. And a plurality of inner support fences 154 are formed on the outer sides of the first and second sub fences 152, 152, respectively. The spacing between the inner support fences 154 may be less than the spacing between the connection fences 153. For example, the spacing between the inner support fences 154 may be one-half the spacing between the connection fences 153.

The outer fence 160 may be formed between the second region II of the base layer 110 and the third region III. The outer fence 160 may be spaced a predetermined distance from the electrode pattern along the outer circumference of the electrode pattern 130 and the outer fence 160 may have the same height as the height of the inner fence 150. A plurality of outer support fences 161 for reinforcing a support force for the outer fence may be formed on the lower portion of the outer fence 160. [ The outer support fence 161 may extend to the inner side and the outer side of the outer side fence to further enhance the supporting force for the outer side fence. The spacing between the outer support fences 161 may be the same as the spacing between the inner support fences 154. Further, if necessary, the inner fence and the outer fence may be provided with a sub fence.

3A to 3G are cross-sectional views sequentially illustrating a manufacturing process of a base layer 110 and a circuit pattern in a method of manufacturing a test socket according to an embodiment of the present invention. 3A to 3G are shown based on a cut-off line "A-A '" in FIG. The following process can be performed by the MEMS method.

Referring to FIG. 3A, a base substrate 200 is prepared. As the base substrate 200, an insulator substrate such as ceramic or glass can be used. At this time, the surface of the base substrate 200 may be cleaned and dried to remove foreign substances adhered to the base substrate 200.

Referring to FIG. 3B, the first seed layer 210 is formed on the upper surface of the base substrate 200. The first seed layer 210 may be formed to a thickness of 1 to 2 탆 by sputtering, electroplating, CVD, or the like. As the material of the first seed layer 210, at least one of copper (Cu), titanium (Ti), and chromium (Cr) may be used. The first seed layer 210 may be formed of a multilayer structure of a lower layer 211 and an upper layer 212. The lower layer 211 may be formed of titanium (Ti) or chromium (Cr) And may be formed of copper (Cu).

Referring to FIGS. 3C and 3D, an external connection pad 114 is formed on the surface of the first seed layer 210. For example, a PR (Photo Resist) is applied to the surface of the first seed layer 210, a pad hole is formed along the mask pattern so that the first seed layer 210 of the portion where the external connection pad is to be formed is exposed, The external connection pad 114 can be formed by using nickel (Ni) or nickel-cobalt (Ni-Co) plating in the pad hole. After the external connection pad 114 is formed, the PR can be removed by etching or the like.

Referring to FIG. 3E, a sacrificial layer 300 may be formed on the surface of the first seed layer 210. For example, the sacrificial layer 300 may be formed by electroplating on the surface of the first seed layer 210 and the external connection pad 114, removing the PR around the external connection pad 114. Thereafter, the upper surface of the external connection pad 114 is exposed through the polishing and planarizing process. As the sacrifice layer 300, for example, copper may be used. Thereafter, a lapping process may be performed to remove the sacrifice layer 300 deposited on the upper surface of the external connection pad 114 so that the upper surface of the external connection pad 114 is exposed.

Referring to FIG. 3F, a first base layer 111 and a first circuit pattern 121 are formed on the sacrificial layer 300 and the external connection pad 114. As the first base layer 111, a polyimide (PI) material may be applied. For example, the first base layer 111 may be formed by applying a liquid polyimide (PI) material and curing it. Alternatively, the first base layer 111 may be formed by pressing a solid polyimide (PI) material on the surface of the sacrificial layer 300.

The first circuit pattern 121 is formed in the first base layer 111 such that the upper portion is exposed on the first base layer 111 and the lower portion is electrically connected to the external connection pad 114. For example, the first base layer 111 corresponding to the external connection pad 114 is etched according to the mask pattern to form a pattern hole in a portion where the first circuit pattern 121 is to be formed, The first circuit pattern 121 may be formed by depositing copper (Cu) or gold (Au) material in a similar manner. The first circuit pattern 121 may have a cross section such as a " T " The height and length of the first circuit pattern 121 may function as a rewiring pattern for electrical connection between the external connection pad 114 and the electrode pattern thereafter by increasing or decreasing as required.

Referring to FIG. 3G, a second base layer 112 is formed by applying a polyimide (PI) material on the first base layer 111.

A second circuit pattern of nickel (Ni) or nickel-cobalt (Ni-Co) so that the upper portion is exposed on the second base layer 112 and the lower portion is electrically connected to the upper portion of the first circuit pattern 121 122 are formed. The second circuit pattern 122 may have a cross section such as a " T " or " a " character, and the upper portion thereof is electrically connected to the electrode pattern.

Also, the capacitance pad 170 is formed on the first region I of the base layer 110. The capacitor pad 170 may be electrically connected to at least one of the second circuit patterns 122 connected to the electrode patterns 130 through the first circuit patterns 121. [

4A to 4Q are cross-sectional views sequentially illustrating a manufacturing process of the electrode pattern 130 and the elastic layer 140 in the method of manufacturing a test socket according to an embodiment of the present invention. 4A to 4Q are shown based on a cut-off line "A-A '" in FIG. The following process can be performed by the MEMS method.

Referring to FIG. 4A, a first electrode pattern 131 is formed on a base layer, particularly, a second base layer 112. For example, the first PR is applied to the surface of the second base layer 112, and the first PR of the portion where the first electrode pattern 131, the inner fence 150, and the outer fence 160 are to be formed is etched according to the mask pattern Thereby forming pattern holes and fence holes. A pattern hole is formed at a position connected to the second circuit pattern 122 and nickel or nickel-cobalt (Ni-Co) alloy is electroplated to the pattern hole to form a first electrode pattern 131 . In addition, the inner fence 150 and the outer fence 160 are formed at the same height by electroplating or the like for the inner fence and the outer fence in the fence hole. At this time, at least one first sub fence 151 and a second sub fence 152 may be formed on the inner side and the outer side of the inner fence 150, respectively, in order to maximize an adhesion area with the elastic layer, which will be described later. The first sub-fence 151 and the second sub-fence 152 may have a height lower than the height of the inner fence 150. [

4B to 4D, a second seed layer 220 is formed on the upper surface of the first PR. For example, the first PR is removed to a predetermined height so that the upper portion of the first electrode pattern 131 is exposed. Thereafter, a lower layer 221 of the second seed layer 220 is formed on the first PR. Next, the second PR is applied to the surface of the lower layer 221 of the second seed layer 220, the second PR is removed to expose the upper portion of the first electrode pattern 131 and a part of the periphery thereof, And the upper layer 222 is formed on the exposed lower layer 221 by removing the second PR.

Referring to FIG. 4E, a second electrode pattern 132 is formed on the exposed upper surface of the first electrode pattern 131 and the upper surface of the upper layer 222 to be electrically connected to the first electrode pattern 131. A third PR is applied on the second seed layer 220 including the first electrode pattern 131 and the second electrode pattern 132.

Referring to FIG. 4F, a third electrode pattern 133 is formed to be electrically connected to the second electrode pattern 132. For example, a fourth PR is applied to the upper surface of the third PR and the second electrode pattern 132, and a third electrode pattern 133 is formed to be electrically connected to the second electrode pattern 132. Specifically, the fourth PR is applied to the surface of the third PR, and the surface of the second electrode pattern 132 in the portion where the third electrode pattern is to be formed is etched using a mask, and then nickel (Ni) The three-electrode pattern 133 can be formed.

4G to 4I, a third seed layer 230 is formed on the upper surface of the fourth PR. After the fourth PR is removed to expose the upper portion of the third electrode pattern 134, a lower layer 231 of the third seed layer 230 is formed. Next, the fourth PR is removed so that the top of the third electrode pattern 133 and a part of the periphery thereof are exposed. Thereafter, the fourth PR is removed to be electrically connected to the third electrode pattern 133, and an upper layer 232 is formed of copper (Cu) on the lower layer 231 of the exposed third seed layer 230.

Referring to FIG. 4J, a fourth electrode pattern 134 is formed on the fourth PR to be electrically connected to the third electrode pattern 133. For example, after the fifth PR is applied on the third seed layer 230 and the third electrode pattern 133, the fifth PR is removed to expose the periphery of the third electrode pattern 134 and the third electrode pattern, A fourth electrode pattern 134 is formed on the upper surface of the third electrode pattern 133 and the upper surface of the upper layer 232 of the third seed layer 230.

Referring to FIGS. 4K to 4O, PRs and seed layers except for the electrode pattern 130 are removed in the stacked order. For example, after the fifth PR is removed, the third seed layer is removed, the fourth PR and the third PR are removed, the second seed layer is removed, and then the second PR and the first PR are removed, (130).

Referring to FIG. 4P, the elastic layer 140 is formed to surround the electrode pattern 130 to elastically support the electrode pattern. For example, the elastic layer 140 may be formed by injecting a material of a liquid-like elastic layer 140 into the inner fins 150 and the outer fences 160, followed by firing and curing. As the material of the elastic layer 140, PDMS can be applied. At this time, the elastic layer may be provided with a stronger supporting force by increasing the area of adhesion by the inner fence 150, the first sub fence 151, and the second sub fence 152 formed by the concavo-convex structure.

Referring to FIG. 4Q, the base layer 110 formed on the base substrate 200 through the sacrificial layer 300 is separated from the base substrate 200 to complete the manufacture of the test socket.

Since the electrode pattern 130 is elastically supported by the elastic layer 140, it is possible to minimize damage to the external connection terminal when the semiconductor device is brought into contact with the external connection terminal, Even if the terminals are formed at fine pitches, the test pattern can be stably connected to the base layer 110 through the general-purpose test board by means of the circuit pattern 120 rearranged, so that the test reliability can be improved.

5 is a sectional view of a test socket according to a second embodiment of the present invention.

Referring to FIG. 5, a semiconductor device test socket 100 according to a second embodiment of the present invention includes a base layer 110 mounted on a test board electrically connected to semiconductor inspection equipment, A circuit pattern 120, a plurality of electrode patterns 130 formed on the base layer 110, an elastic layer 140 elastically supporting the electrode pattern 130, an inner fence 140 supporting the elastic layer 140 150 and an outer fence 160. Since this configuration is similar to that of the first embodiment, detailed description of each configuration will be omitted.

However, since the elastic layer is formed between the first sub fence and the outer fence in the first embodiment, when the semiconductor device is connected to the test socket, the load is concentrated between the first sub fence 151 and the outer fence 160 The electrode pattern 130 may be deformed.

However, in the second embodiment, the elastic layer 140 may extend to the inside of the second sub fence 152 to seal the capacitance pad 170. That is, referring to FIG. 1, the elastic layer 140 may be formed on the entire upper surface of the base layer 110 except for the frame portion 111. The elastic layer 140 stably sustains the load of the semiconductor element when the semiconductor element is connected to the electrode pattern 130 and the elastic layer 140 formed on the entire upper surface of the base layer 110 The occurrence of deformation of the electrode pattern 130 can be minimized.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be.

That is, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

Accordingly, the scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100; Test socket
110; Base layer 111; The first base layer
112; A second base layer 114; External connection pad
120; Circuit pattern 121; The first circuit pattern
122; The second circuit pattern
130; Electrode pattern 131; The first electrode pattern
132; A second electrode pattern 133; The third electrode pattern
134; The fourth electrode pattern
140; Elastic layer 150; Inner fence
151; A first sub-fence 152; The second sub-fence
153; Connection fence 154; Inner support fence
160; An outer fence 161; Outer support fence
170; Capacitance Pad
200; A base substrate 210; The first seed layer
220; A second seed layer 230; The third seed layer
300; Sacrificial layer

Claims (20)

A test socket for electrical connection between a semiconductor device and a test board,
A first surface having a first region and a second region disposed outside of the first region and a second surface opposing the first surface, wherein a pitch corresponding to an electrode terminal of the test board is formed on the second surface, A base layer having external connection pads formed therein;
A plurality of circuit patterns formed inside the base layer so as to be partially exposed to the first surface of the base layer and rearranged at a pitch corresponding to the external connection pad;
A plurality of electrode patterns formed in the second region so as to be electrically connected to the circuit patterns and external connection terminals of the semiconductor device, the electrode patterns being arranged at a pitch corresponding to the external connection terminals;
An inner fence and an outer fence respectively disposed on the outer side of the first region and the inner side of the second region;
A capacitance pad provided inside the inner fence and electrically connected to the external connection pad and the electrode pattern via the circuit pattern;
And an elastic layer surrounding the capacitor pad, the inner fence, and the outer fence and surrounding the electrode pattern so that a part of the electrode pattern is exposed.
The method according to claim 1,
Wherein a material of the base layer is polyimide.
The method according to claim 1,
Wherein the circuit pattern includes a first circuit pattern that is relocated to be electrically connected to the external connection pad, a second circuit that is partially exposed to the first surface of the base layer to be electrically connected to the first circuit pattern and the electrode pattern, Wherein the semiconductor device is a semiconductor device.
The method according to claim 1,
The electrode pattern may include a first electrode pattern electrically connected to the circuit pattern, a second electrode pattern in the form of a beam electrically connected to the first electrode pattern, a third electrode pattern electrically connected to the second electrode pattern, And a fourth electrode pattern electrically connected to the third electrode pattern and exposed in a beam form on an upper surface of the elastic layer.
The method according to claim 1,
Wherein the material of the elastic layer comprises at least one of PDMS (polydimethylsiloxane), polyurethane (PU), polyurethane acrylate (PUA), silicone rubber, and polymethylmethacrylate (PMMA). Test socket.
The method according to claim 1,
And a pitch between the external connection pads is larger than a pitch between the electrode patterns.
The method according to claim 1,
Further comprising a first sub-fence spaced apart from an inner side of the inner fence, and a second sub-fence spaced apart from the outer side of the inner fence.
8. The method of claim 7,
Wherein the first sub-fence and the second sub-fence each have a height lower than the height of the inner fence.
8. The method of claim 7,
And a plurality of inner support fences connecting the inner fence, the first sub-fence, and the second sub-fence, wherein the inner support fence extends outside the first sub-fence and the second sub-fence Of the semiconductor device.
The method according to claim 1,
Wherein a plurality of outer support fences extending inwardly and outwardly of the outer fence are formed in a lower portion of the outer fence.
The method according to claim 1,
Wherein a height of the inner fence and a height of the outer fence are respectively set lower than the height of the electrode pattern.
The method according to claim 1,
Wherein a plurality of the capacitor spurs are formed along the inner circumference of the inner fence.
The method according to claim 1,
Wherein the base layer further includes a frame portion formed outside the second region, and a bonding portion protrudes from the frame portion.
14. The method of claim 13,
And a lift-off pattern for lift-off of the test socket is provided at an edge of the frame portion.
15. The method of claim 14,
Wherein the lift-off pattern is provided with a removable dummy pattern after lift-off of the test socket.
A method of manufacturing a test socket for electrical connection between a semiconductor device and a test board,
A substrate preparation step of preparing a substrate;
An external connection pad forming step of forming a plurality of external connection pads on the bottom surface of the substrate;
A circuit pattern forming step of forming a base layer on the substrate and rearranging the circuit pattern for electrical connection with the external connection pad to the base layer;
An electrode pattern forming step of forming an electrode pattern on the base layer so as to be electrically connected to the circuit pattern and the external connection terminal of the semiconductor element;
A capacitor pad forming step of forming a capacitance pad to be electrically connected to the circuit pattern and the electrode pattern;
A fence forming step of forming an inner fence and an outer fence inside and outside the electrode pattern, respectively;
Forming an elastic layer covering the electrode pattern between the inner fence and the outer fence so that a part of the electrode pattern is exposed;
The method comprising the steps of:
17. The method of claim 16,
The circuit pattern forming step may include a first circuit pattern forming step of forming a first circuit pattern in the first base layer so as to correspond to an interval between external connection pads; And forming a second circuit pattern on the second base layer so as to be electrically connected to the first circuit pattern.
17. The method of claim 16,
Wherein the base layer is formed by applying a liquid polyimide material and then curing the base material layer.
17. The method of claim 16,
The electrode pattern forming step may include: a first electrode pattern forming step of forming a first electrode pattern electrically connected to the circuit pattern; A second electrode pattern forming step of forming a second electrode pattern electrically connected to the first electrode pattern; A third electrode pattern forming step of forming a third electrode pattern electrically connected to the second electrode pattern; And forming a fourth electrode pattern electrically connected to the third electrode pattern and exposed on the upper surface of the elastic layer.
17. The method of claim 16,
Wherein in the forming of the elastic layer, the elastic layer is formed to seal the capacitance pad.

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