KR101689973B1 - A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for three-phase rectifier - Google Patents

Abstract

There is no constitution of another ordinary transformer circuit and a structure of a zener diode element in a voltage converter for converting a high voltage of AC and DC power to a DC power of low voltage and the voltage between negative gate sources (NMOS) field-effect transistor (FET), that is, a negative threshold voltage 5-terminal NMOS transistor (negative threshold 5-terminal NMOS FET). Therefore, the circuit area of the transformer circuit 101 and the zener diode 104 is usually removed to remove the area occupied by the circuit area of the transformer circuit 101 and the zener diode 104, It is possible to implement a cost circuit and realize a circuit without power consumption in standby and operation power supply state by blocking standby and operation power loss and to realize free voltage operation up to high voltage supply region As shown in FIG.
Among the three or four input terminals of the three-phase input power source, the first input terminal 401 is connected to the input terminal of the first half-wave rectification power generator, and the second input terminal 402 is connected to the second half- Wave rectification power generator, the third input terminal 402 is connected to the input terminal of the third half-wave rectification power generator, and the fourth input terminal 402 is connected to the input terminal of the fourth half-wave rectification power generator And a power supply unit.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a power supply circuit device using a 5-terminal NMOS transistor device, and a power supply circuit device using the same. rectifier}

(EN) A voltage converting apparatus for converting a high voltage alternating current and a direct current (DC) power source to a low voltage direct current power source, characterized in that the constitution of the circuit region of the transformer circuit (101) and the zener diode ) And zener diode (104) circuit area, thereby realizing a low-cost circuit and preventing standby and operation power loss, thereby realizing a circuit without power consumption in standby and operation power supply state And a power supply circuit device capable of implementing a free voltage operation using a negative threshold voltage emmos transistor element.

In a voltage converting apparatus for converting a high voltage AC power source to a low voltage DC power source, the normal voltage transforming circuit 101 is a circuit region causing a large area and cost in the circuit structure.

Therefore, it becomes an obstacle factor in constructing a low cost circuit. On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

At this time, a constant current is allowed to flow through the Zener diode 104 in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

In order to solve such a problem, it is necessary to construct a circuit without power loss in standby and operation power supply states. Particularly, in terms of energy saving, a circuit configuration without power loss in a standby state is desperately needed.

In addition, a circuit having the same characteristics as described above is also required when converting the voltage of the DC power source such as the automobile power supply to a low voltage.

In recent years, the role of surge protection to protect the system from system transients and lightning-induced transients in the field of communication and ESD (electrostatic discharge) protection to protect circuits against static electricity in mobile communication terminals, notebook PCs, A PN varistor is required.

It is used as a surge absorbing element to prevent a sudden change in voltage (surge) to appliances such as various information devices and control devices. It is used in various parts ranging from power devices such as power plants, substations, and power stations to the core devices of lightning arresters for safeguarding equipment from lightning strikes.

Accordingly, there is a strong demand for protecting the system from power surges, ridiculous surges, and the like that occur in these devices.

A surge protection device (SPD, VTMS, or Transient Voltage Surge Suppressor: TVSS) is used in order to prevent surges from destroying or malfunctioning electronic equipment installed in the power system from such transient external surges. Should be installed.

The embodiment of the present invention has the following features.

First, the circuit area of the normal transformer circuit 101 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 101 and the zener diode 104, Which makes it possible to implement a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 101 and the zener diode 104, it is possible to implement a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss .

Third, a negative threshold Vt depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) critical high voltage (about 1000V or higher) A free voltage operation can be realized.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, effect transistors, i.e., elements of a negative threshold 5-terminal NMOS FET, to enable stable operation in the operational characteristics of the circuit. .

Fifth, even when the voltage of the DC power source such as the automobile power source is converted into the DC voltage of the low voltage, the same circuit can be used to implement it.

Sixth, it is possible to realize the function of PN varistor as the role of power surge, Brain Brain surge, and electrostatic discharge (ESD) protection.

Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. . ≪ / RTI >

A voltage converting apparatus for converting a high-voltage alternating current and a direct-current power source into a low-voltage direct-current power source, the configuration of the ordinary transformer circuit 101 is removed to save a large area and power consumption in the constitution of the transformer circuit 101 So that a low-cost circuit can be constituted. In addition, the structure of the Zener diode 104 circuit area is removed to reduce the area occupied in the circuit area of the Zener diode 104, and the standby and operation power consumption, And to realize a circuit without power loss in standby and operation power supply states.

In addition, since the input voltage of the high voltage AC and DC power supplies must operate over a wide voltage range, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. And a free voltage operation characteristic.

A depletion NMOS transistor having a negative threshold voltage, that is, a voltage between negative gate sources (negative Vgs), in a voltage converter for converting AC and DC power to a voltage of a DC power source, Includes a configuration of a field effect transistor (FET), that is, a configuration of a negative threshold 5-terminal NMOS FET. The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, an isolated body, B) and a P-substrate (P-substrate: P-Sub). The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, . The gate is connected to the ground terminal of the P-substrate and the drain D is connected to the terminal to which power is supplied before the voltage conversion. -1 power supply terminal, respectively.

As described above, the embodiment of the present invention has the following effects.

First, the circuit area of the normal transformer circuit 101 and the zener diode 104 is removed to remove the area occupied in the circuit area of the transformer circuit 101 and the zener diode 104, Thereby enabling implementation of a cost circuit.

Second, by eliminating the configuration of the circuit region of the normal transformer circuit 101 and the zener diode 104, it is possible to implement a circuit free from power consumption in standby and operation power supply state by interrupting standby and operation power loss do.

Third, the input voltage of AC and DC power supplies of high voltage must operate over a wide voltage range. Therefore, it is required to have such an operating characteristic that the same output voltage characteristics can be maintained in all voltage operating ranges. (About 1000 V or more) power supply voltage range.

Fourth, a depletion NMOS (N-type metal oxide semiconductor) field effect transistor (FET) having a negative threshold Vt, that is, a negative Vgs characteristic, transistor, or a negative threshold 5-terminal NMOS FET), so that a stable operation can be realized in the operational characteristics of the circuit. Effect.

Fifth, the same circuit can be used to convert a voltage of a DC power source such as a vehicle power source into a DC voltage of a low voltage.

Sixth, it is possible to implement a PN varistor function as a role of power surge, rational brace, and electrostatic discharge (ESD) protection.

Seventh, when N negative threshold voltage 5-terminal NMOS FETs are constructed by the step connection method, the voltage of N times of Vgs and the voltage of N times of Vgs at the final stage are realized. The present invention provides an effect that is feasible.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode; Fig.
2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.
3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.
4 is a configuration diagram of a three-phase three-wire type power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.
FIG. 5 is a schematic diagram of a power supply terminal synthesizing configuration of a three-phase three-wire type power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention. FIG.
FIG. 6 is a schematic diagram of a power supply terminal synthesis configuration of a three-phase four-wire power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention. FIG.
FIG. 7 is an operational waveform diagram of a 3-phase power amplification voltage conversion circuit using a negative threshold 5-terminal NMOS FET of the present invention. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a voltage conversion circuit using a normal transformer circuit and a zener diode.

A rectifying circuit 102 and a zener diode 104 in a voltage converting apparatus for converting an AC input power supply 100 into a low voltage DC power supply voltage do. The transformer circuit 101 is a circuit region for converting a high voltage input power supply to a low voltage.

The rectifying circuit 102 is a circuit region composed of a half-wave or full-wave rectifying diode for converting an AC power source to a DC power source. The transformer circuit 101 is usually a circuit area that causes a large area and cost in the construction of the circuit.

Therefore, it becomes an obstacle factor in constructing a low cost circuit.

On the other hand, the circuit region of the Zener diode 104 is arranged in parallel with the output terminal 103 of the rectifying circuit 102 in order to secure the output voltage characteristic of the constant voltage.

The output terminal 103 of the rectifying circuit 102 is used as the final output Step-1 power supply terminal 105. [

At this time, a constant current flows to the Zener diode in the standby or operating power supply state, thereby securing the output voltage characteristic of the constant voltage from the output voltage. Therefore, a certain amount of standby or operation power is lost in standby or operating power supply.

2 is a terminal block diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A configuration of a depletion NMOS field effect transistor (FET) having a negative threshold voltage Vt, that is, a voltage between negative gate sources (negative Vgs) And a configuration of a threshold voltage 5-terminal NMOS FET.

The negative threshold 5-terminal NMOS FET includes a drain D, a gate G, a source S, an isolated body, B) and a P-substrate (P-substrate).

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET may be a negative value such as -1V, -2V, -3V, -4V, .

The P-type isolated body (B) terminal has an isolated element structure and is connected to a common ground terminal for supplying a 0V ground voltage according to a design selection method as follows The first connection method and the second connection method, which is connected to the source (S) terminal and used as an output terminal, are possible.

More specifically,

As a first method, the gate (G) terminal, the isolated body (B) terminal, and the P-substrate (P-sub) Respectively.

In another alternative method, the gate (G) terminal and the P-substrate (P-sub) terminal are respectively connected to a common ground terminal for supplying a ground voltage of 0V, An isolated body (B) terminal is connected to the source (S) terminal and is used as an output terminal.

And the gate (G) terminal may be supplied with a separate control voltage.

The drain (D) terminal is a semiconductor doping region having an n-type semiconductor characteristic, and is a terminal configuration for connecting to a power supply. The drain (D) terminal is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

In addition, the drain (D) terminal region may surround the isolated body (B) terminal and the source (S) terminal region and may be included in the drain (D) terminal region .

The drain (D) terminal region is directly contacted with a P-substrate (P-sub) terminal to form a PN varistor structure.

The PN varistor is connected in parallel to the drain (D) terminal region to be protected. The PN varistor acts as a nonconductor at a constant voltage or lower, but it does not affect the circuit. However, when a certain voltage or more is applied, the PN varistor connected in parallel becomes a conductor, - P-substrate (P-sub) terminal to protect the device from surge.

Additional operating characteristics of the PN varistor structure are as follows.

Varistors are short for variable resistors, sometimes called VDRs (Voltage-Dependent Resistors). The role of the PN varistor is a semiconductor device whose resistance varies according to the input voltage, as can be expected from the above name.

A typical PN varistor is characterized by a nonlinear I-V plot, which acts as an insulator for electricity until a certain breakdown voltage, but after the breakdown voltage it exhibits the nature of the conductor.

When a low voltage microprocessor is used in a system or device, a surge that occurs when a lightning strike or switch is opened can cause system stoppage, equipment burnout or deterioration, data transmission error, communication error, The failure of the system, such as inoperability, can occur momentarily. This is a big weakness of the system using the semiconductor. To protect this weak point, a PN varistor is needed.

The source S terminal is a semiconductor doping region having an n-type semiconductor characteristic and is used as an output terminal for obtaining a target output power supply voltage. The source S terminal may be connected to the isolated body B terminal as an output terminal or may be used as an output terminal using only the source S terminal. Specification characteristics.

3 is an operational characteristic diagram of a negative threshold 5-terminal NMOS FET of the present invention.

A negative threshold voltage at the Vds between the gate (G) terminal and the source (S) terminal, Vgs, and the current between the drain (D) terminal and the source (S) A threshold voltage value of a voltage 5-terminal NMOS FET is characterized by having a negative value (VT).

4 is a configuration diagram of a three-phase three-wire type power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The three-phase three-wire rectifier and power supply circuit of the present invention is a circuit area for converting three-phase three-wire AC input power to DC output power. It is also characterized in that it can be used for converting DC input power to DC output power.

That is, the present invention is also applicable to a case where a DC power source is connected to a DC power source regardless of the polarity of the DC power source.

The three-phase three-wire rectifier and power supply circuit of the present invention includes a three-phase input power supply 400 for a three-phase three-wire power input, a first half-wave rectification power generator 460 corresponding to three half- A second half-wave rectification power generator 470, and a third half-wave rectification power generator 480. [

The three input terminals of the three-phase input power source 400 are connected to a first input terminal 401 and a second input terminal 402 are connected to the input terminal of the first half-wave rectification power generator 460 and the second half- Generator 470 and the third input terminal 483 is connected to the input terminal of the third half-wave rectification power generator 480, respectively.

The circuit configurations in the circuit areas of the first half-wave rectification power generator 460, the second half-wave rectification power generator 470, and the third half-wave rectification power generator 480 are the same.

Wave rectification power generator 460, the second half-wave rectification power generator 470, and the third half-wave rectification power generator 480 are the same as those of the first half-wave rectification power generator 460 460, the second half-wave rectification power generator 470, or the third half-wave rectification power generator 480, the detailed circuit configuration will be described below.

The first input terminal 401, the second input terminal 402, or the third input terminal 483, which are three input terminals of the three-phase input power supply 400, are connected to the first half-wave rectification power generator 460, A plurality of N negative threshold 5-terminal NMOS FETs 403 (see FIG. 4) are arranged in the circuit region of the first half-wave rectification power generator 470 or the third half-wave rectification power generator 480. (D) terminals 404, 410, 416, 422 of the first, second, third, fourth, fifth, sixth,

The connection configuration of the first negative threshold voltage 5-terminal NMOS FET 403 is as follows.

The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406 are respectively connected to a common ground terminal for supplying a ground voltage of 0V.

The source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics doping region connected to the P-type terminal of the output PN diode D1. The N-type terminal of the output PN diode D1 is used as a Step-1 power supply terminal 408 which is an output terminal for obtaining a target output power supply voltage.

The source (S) terminal 407 is connected to the P-type isolated body (B) terminal 403 of the negative threshold 5-terminal NMOS FET 403 And may be used as an output terminal by using only the source (S) terminal 407. In addition,

The drain (D) terminal 404 is connected to the first input terminal 401 or the second input terminal 401 of the single-phase input power supply 400 as a semiconductor doping region having n-type semiconductor characteristics 402, respectively. The drain (D) terminal 404 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 405 and the P-substrate (P-sub) terminal 406 are connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The connection configuration of the second negative threshold voltage 5-terminal NMOS FET 409 is as follows.

The source (S) terminal 413 of the negative threshold 5-terminal NMOS FET 409 is a semiconductor doping having an n-type semiconductor characteristic doping region connected to the P-type terminal of the output PN diode D2. The N-type terminal of the output PN diode D2 is used as a Step-2 power supply terminal 414 which is an output terminal for obtaining a target output power supply voltage.

The source (S) terminal 413 is common to the isolated body (B) terminal of the negative threshold 5-terminal NMOS FET 409 And may be used as an output terminal, or may be used as an output terminal using only the source (S) terminal 413.

The drain (D) terminal 410 is a semiconductor doping region having an n-type semiconductor characteristic and is connected to the first input terminal 401 or the second input terminal 401 of the single- 402, respectively. The drain (D) terminal 410 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 409 may be, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 411 of the negative threshold 5-terminal NMOS FET 409 is connected to the negative threshold voltage 5-terminal NMOS transistor (negative) (S) terminal 407 of the threshold 5-terminal NMOS FET 403 or the Step-1 power supply terminal 408 serving as an output terminal. The P-substrate (P-sub) terminal 412 is connected to a common ground terminal for supplying a ground voltage of 0V, respectively.

The connection configuration of the Nth negative threshold voltage 5-terminal NMOS FET 415 is as follows.

The source terminal 419 of the negative threshold 5-terminal NMOS FET 415 is connected to a semiconductor doping (not shown) having n-type semiconductor characteristics doping region connected to the P-type terminal of D3, the output PN diode. The N-type terminal of the output PN diode D3 is used as a Step-N power supply terminal 420 which is an output terminal for obtaining a target output power supply voltage.

The source (S) terminal 420 is common to the isolated body (B) terminal of the negative threshold 5-terminal NMOS FET 415 Or may be used as an output terminal by using only the source (S) terminal 420. In addition,

The drain (D) terminal 416 is a semiconductor doping region having an n-type semiconductor characteristic. The first input terminal 401 or the second input terminal 416 of the single- 402, respectively. The drain (D) terminal 416 is characterized by being capable of applying a high voltage of about 1000 V or more, that is, a free voltage.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 415 is set to a value of, for example, -1 V, -2 V, -3 V, And has a negative value.

The gate (G) terminal 417 of the negative threshold 5-terminal NMOS FET 415 is connected to the negative threshold voltage 5-terminal NMOS transistor 415 (S) terminal 413 of the threshold 5-terminal NMOS FET 409 or the Step-2 power supply terminal 414 which is an output terminal.

The P-substrate (P-sub) terminal 418 is connected to a common ground terminal for supplying a ground voltage of 0V.

Multiple N means one or more natural numbers. The source terminal S (N-1) or the output terminal Step- (N-1) of the negative threshold 5-terminal NMOS FET The next step is to connect the gate to the gate (G) terminal of the threshold voltage 5-terminal NMOS FET.

FIG. 5 is a view illustrating a configuration of a power supply terminal of a three-phase three-wire power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The rectification and power supply circuit of the present invention includes an input power source 400 for inputting power, a first half-wave rectification power generator 460, a second half-wave rectification power generator 470, And a third half-wave rectification power generator 480 circuit area.

Phase input power supply 400 is connected to the input terminal of the first half-wave rectification power generator 460 and the second input terminal 402 is connected to the second half- The third input terminal 470 and the third input terminal 483 are connected to the input terminals of the third half-wave rectification power generator 480, respectively.

The circuit configurations in the circuit areas of the first half-wave rectification power generator 460, the second half-wave rectification power generator 470, and the third half-wave rectification power generator 480 are the same.

The Step-1 power supply terminal 408, which is an output power supply terminal of each of the first half-wave rectification power generator 460, the second half-wave rectification power generator 470, or the third half-wave rectification power generator 480, ), The Step-2 power supply terminal 414, and the Step-N power supply terminal 420 have the same circuit configuration in the circuit region.

Thus, the Step-1 power supply terminal 408, which is the output power supply terminal of the first half-wave rectification power generator 460, the Step-1 power supply terminal 1408, which is the output power supply terminal of the second half-wave rectification power generator 470, And the signal of the Step-1 power supply terminal 2408, which is the output power supply terminal of the third half-wave rectification power generator 480, to constitute a combined Step-1 power supply terminal 508. If the composite configuration is expanded as described above, the composite Step-2 power supply terminal 514 and the composite Step-N power supply terminal 520 are configured in the same manner.

FIG. 6 is a view illustrating a configuration of a power supply terminal of a three-phase four-wire power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The rectification and power supply circuit of the present invention includes an input power source 400 for inputting power, a first half-wave rectification power generator 460, a second half-wave rectification power generator 470, The third half-wave rectification power generator 480, and the third half-wave rectification power generator 490.

The first input terminal 401 which is the four input terminals of the single phase input power supply 400 is connected to the input terminal of the first half wave rectification power generator 460 and the second input terminal 402 is connected to the second half wave rectifier power generator 460. [ The third half-wave rectification power generator 480 and the fourth input terminal 494 are connected to the input terminals of the fourth half-wave rectification power generator 490, the third input terminal 483, the third half-wave rectification power generator 480 and the fourth input terminal 494, respectively.

The circuit configuration in each circuit area of the first half-wave rectification power generator 460, the second half-wave rectification power generator 470, the third half-wave rectification power generator 480 and the fourth half-wave rectification power generator 490 Are the same.

The output power of each of the first half-wave rectification power generator 460, the second half-wave rectification power generator 470, the third half-wave rectification power generator 480, The Step-1 power supply terminal 408, the Step-2 power supply terminal 414, and the Step-N power supply terminal 420 are the same in circuit configuration in the circuit region.

Thus, the Step-1 power supply terminal 408, which is the output power supply terminal of the first half-wave rectification power generator 460, the Step-1 power supply terminal 1408, which is the output power supply terminal of the second half-wave rectification power generator 470, A Step-1 power supply terminal 2408 which is an output power supply terminal of the third half-wave rectification power generator 480 and a Step-1 power supply terminal 2408 which is an output power supply terminal of the fourth half-wave rectification power generator 490 3408 are connected to each other to constitute a combined Step-1 power supply terminal 508. If the composite configuration is expanded as described above, the composite Step-2 power supply terminal 514 and the composite Step-N power supply terminal 520 are configured in the same manner.

FIG. 7 is an operational waveform diagram of a three-phase power amplification voltage conversion circuit using a negative threshold voltage 5-terminal NMOS FET of the present invention.

The three-phase input power supply 500 includes an AC waveform of a first half wave, a second half wave, and a third half wave, and the first half wave rectification power generator 460, the second half wave rectification power generator 470, and / Is input to the drain (D) terminal of the negative threshold voltage 5-terminal NMOS FET in the third half-wave rectification power generator 480 circuit region.

The threshold voltage (Vt: Vgs) of the negative threshold 5-terminal NMOS FET 403 is, for example, -1 V, -2 V, -3 V, And has a negative value.

The voltage of the Step-1 power supply terminal 508 of the source S terminal 407 is lower than the threshold voltage Vt of the negative threshold 5-terminal NMOS FET : + 1V, + 2V, + 3V, + 4V, and the like, respectively, corresponding to the output voltage Vgs.

Further, the voltage is increased by the threshold voltage (Vgs) of the negative threshold voltage 5-terminal NMOS FET for each step.

Therefore, when N negative threshold voltage 5-terminal NMOS FETs are constructed in this way, voltages of N times of Vgs and voltages of N times Vgs can be obtained at the final stage .

100 input power
101 transformer circuit
102 rectifier circuit
104 Zener diode
105 Step-1 Power supply terminal
400 input power
401 first input terminal
402 second input terminal
483 third input terminal
494 fourth input terminal
403 negative threshold voltage 5-terminal NMOS FET with negative threshold
404 drain (D) terminal
405 gate (G) terminal
406 P-substrate (P-sub) terminal
407 source (S) terminal
408 Step-1 power supply terminal
414 Step-2 power supply terminal
420 Step-N power supply terminal

Claims (6)

1. A power supply apparatus for converting a high-voltage AC or DC input power supply to an output voltage of low voltage,
A first input terminal 401 of the three-phase input power supply 400; And
A second input terminal 402 of the three-phase input power supply 400; And
A third input terminal 483 of the three-phase input power supply 400; And
In the first half-wave rectification power generation circuit region,
A drain (D) terminal 404 of a negative threshold 5-terminal NMOS FET 403 connected to the first input terminal 401; And
The gate terminal G 405 of the negative threshold 5-terminal NMOS FET 403 and the P-substrate P-sub terminal 405 of the negative threshold voltage 5- 406) for supplying a ground voltage; And
A P-type terminal of D1, which is an output PN diode connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403; And
A Step-1 power supply terminal 408 connected to the N-type terminal of the output PN diode D1 to supply output power; And
Type isolated body (P-type) connected to the source (S) terminal 407 of the negative threshold 5-terminal NMOS FET 403, A first half-wave rectification power generator (460); And
In the second half-wave rectification power generation circuit region,
A drain (D) terminal 1404 of a negative threshold 5-terminal NMOS FET 1403 connected to the second input terminal 402; And
The gate terminal G 1405 of the negative threshold 5-terminal NMOS FET 1403 and the P-substrate (P-sub) terminal 1405 of the negative threshold voltage 5- 1406) for supplying a ground voltage; And
A P-type terminal of D1, which is an output PN diode connected to the source of the negative threshold 5-terminal NMOS FET 1403; And
A Step-1 power supply terminal 1408 connected to the N-type terminal of the output PN diode D1 to supply output power; And
Type isolated body (P-type) connected to the source (S) terminal 1407 of the negative threshold 5-terminal NMOS FET 1403, B); a second half-wave rectification power generator (470); And
In the third half-wave rectified power generation circuit region,
A drain (D) terminal 2404 of a negative threshold 5-terminal NMOS FET 2403 connected to the third input terminal 483; And
A gate terminal G 2405 of the negative threshold 5-terminal NMOS FET 2403 and a P-substrate (P-substrate) terminal 2405 of the negative threshold voltage 5- 2406) for supplying a ground voltage; And
A P-type terminal of D1, which is an output PN diode connected to the source of the negative threshold 5-terminal NMOS FET 2403; And
A Step-1 power supply terminal 2408 connected to the N-type terminal of the output PN diode D1 to supply output power; And
A P-type isolated body (not shown) connected to the source (S) terminal 2407 of the negative threshold 5-terminal NMOS FET 2403, B); a third half-wave rectification power generator (480); And
The first Step-1 power supply terminal 408, which is the output terminal of the first half-wave rectification power generator 460, the second Step-1 power supply terminal 408, which is the output terminal of the second half- And a third Step-1 power supply terminal 2408 which is an output terminal of the third half-wave rectification power generator 480 are connected to each other to form a synthetic Step-1 power supply terminal 508, which is an output terminal, ≪ / RTI > delete delete delete delete delete

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