JP2002247838A - Voltage boosting circuit, and inverter circuit for alleviating voltage between drain and source - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage boosting circuit which can output a plurality of different DC voltages and an inverter circuit of the type for alleviating voltage between drain and source which operates with a DC voltage outputted from this voltage boosting circuit as the drive source. SOLUTION: The voltage boosting circuit 1 is composed of a voltage boosting means 15 cascade-connecting voltage boosting portions 6 and 12, a voltage boosting control means 21, and a voltage level controlling means 22. The voltage boosting circuit 1 boosts the step-by-step voltage boosting operation based on the clock of the constant period outputted from the voltage boosting controlling means 21 and the inverted clock and outputs different two voltages VA and VB. In this timing, a voltage value VB is detected with the voltage level controlling means 22 and the clock and inverted clock outputs are controlled. Consequently, the feedback control is performed to always provide the constant voltage VB. The inverter circuit of the type for alleviating the voltage between the drain and source is structured to operate with the voltages VA, VB as the drive sources.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit for outputting a plurality of different DC voltages, and a drain-source voltage moderating inverter circuit driven by the DC voltage output from the booster circuit.

[0002]

2. Description of the Related Art An inverter circuit is one of the basic circuits in a digital circuit, and a large number of inverter circuits composed of MOSFETs with low power consumption and high operating speed are mounted on a chip such as an IC or LSI. .

As such an inverter circuit, although not shown, for example, a pair of a p-channel MOSFET (hereinafter simply referred to as a pMOS) and an n-channel MOSFET
There is a type in which both drains (hereinafter simply referred to as nMOS) are connected. This inverter circuit has p
A DC voltage (for example, 20 V) is applied between both the pMOS and the nMOS sources so that the source of the MOS becomes high potential. And pMOS and nM
Both gates of the OS are connected to a common input terminal, and both drains are connected to a common output terminal.

In this inverter circuit, for example, when a low level (0 V) is applied to an input terminal, the source and the drain of the pMOS are turned on, and the drain and the source of the nMOS are turned off. 20V) is output. At this time, since a voltage of 20 V is applied between the drain and the source of the nMOS that is turned off, the withstand voltage between the drain and the source of the nMOS needs to be set to a value larger than 20 V. For the same reason, it is necessary to set the withstand voltage between the drain and the source of the pMOS to a value larger than 20V.

However, the withstand voltage between the drain and source of the pMOS and the nMOS is smaller than 20 V (for example, 12
V). In such a case, two pMOSs and nMOSs are connected between the drain and the source.
A drain-source voltage relaxation type inverter circuit (hereinafter simply referred to as a relaxation type inverter circuit) 30 as shown in FIG. 2 is applied so that a voltage of 0 V is not applied.
For a detailed description of the moderating inverter circuit 30,

Please refer to [Usage form] of the embodiments of the present invention.

Now, this relaxation type inverter circuit 30
For example, a pMOS 32 and a voltage relaxing pMOS (hereinafter simply referred to as relaxing pMOS) 33 connected in the forward direction
And nMOS 34 and n for voltage relaxation connected in the forward direction.
A MOS (hereinafter simply referred to as a relaxation nMOS) 35 is connected in series. And pMOS32
Of the pMOS 32 and n
A DC voltage VA (for example, 20
V) is applied, the relaxing pMOS 33 and the relaxing nMO
At both gates of S34, p is higher than the ground potential VE and p
A DC voltage VB (for example, 10 V) smaller than the DC voltage VA applied to the source of the MOS 32 is applied. Further, both gates of the pMOS 32 and the nMOS 35 are connected to a common input terminal 37, and both drains are connected to a common output terminal 39.

In this relaxation type inverter circuit 30, when a low level (0 V) is applied to the input terminal 37, for example, pMO
S32 and the source and drain of the pMOS 33 are turned on, and the drain and source of the nMOS 34 and nMOS 35 are turned off, so that the output terminal 39 operates to output a high level (20 V).

The voltage at the common connection point 40 between the source of the relaxing nMOS 34 and the drain of the nMOS 35 is 0 V when the drain and source of the relaxing nMOS 34 and nMOS 35 are on. When switching off, relax n
A value (9) obtained by subtracting the threshold voltage VT (for example, 1 V) from the gate voltage (10 V in this case) of the MOS 34
V).

Therefore, the relaxing nMOS 34 and the nMOS
When the 35 is off, a voltage of 11 V is applied between the drain and the source of the relaxed nMOS 34, and a voltage of 9 V is applied between the drain and the source of the nMOS 35. The applied voltage can be suppressed to a withstand voltage of 12 V or less.

Also, when a high level is applied to the input terminal 37, the drain of the pMOS 32 and the relaxing pMOS
Similarly, the voltage at the common connection point 41 between the sources is 20 V when the source and the drain of the pMOS 32 and the pMOS 33 for relaxation are on, but when the drain and the source are switched off, the voltage is 20 V. Is
The gate voltage of the pMOS 33 for relaxation (in this case, 10
V) to a value (11 V) obtained by subtracting the threshold voltage VT (for example, -1 V) from (V).

Therefore, a voltage of 9 V is applied between the source and the drain of the pMOS 32, and a voltage of 11 V is applied between the source and the drain of the pMOS 33 for relaxation. Can be suppressed to a withstand voltage of 12 V or less.

[0012]

In order to drive such a relaxation type inverter circuit 30, a drive source for generating two different DC voltages VA and VB is required. Conventionally, a first booster circuit for generating a DC voltage VA by boosting a predetermined DC voltage VC externally applied, for example, in a chip such as an IC or an LSI, By separately mounting the second booster circuit for generating the voltage VB,
One drive source.

[0013] However, as described above, two
When two booster circuits are mounted, there is a problem that the power consumption increases by that much, the mounting area increases, and the chip cost increases. Moreover, when a plurality of relaxation type inverter circuits are mounted on one chip, if the DC voltage values of the respective driving sources are different, a plurality of booster circuits corresponding to the driving sources are further required. Since the above problem occurs more remarkably, an improvement measure has been desired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and therefore has as its object a booster circuit capable of outputting a plurality of different DC voltages, and a DC voltage output from the booster circuit as a drive source. An object of the present invention is to provide a drain-source voltage relaxation type inverter circuit that operates.

[0015]

To achieve the above object, the means described in claim 1 can be employed. According to this means, the boosting operations of the boosting units are performed simultaneously by cascading the boosting units in multiple stages, and different output voltages (first to m-th) are sequentially increased from one boosting circuit from the first stage of the boosting unit. DC voltage) can be output.
In addition, by performing feedback control by the voltage level control means, the level of the output voltage output from the m-stage booster can be controlled with high accuracy. This also indirectly controls the level of the output voltage output from the booster other than the m-th stage, and can stabilize the output voltage with the fluctuation amount suppressed. Thus, when a predetermined circuit using a plurality of different voltages as a drive source, for example, a drain-source voltage relaxation type inverter circuit is mounted in a chip such as an IC or an LSI, if this booster circuit is applied,
Power consumption can be reduced, a mounting area can be reduced, and an increase in chip cost can be suppressed, as compared with mounting an individual booster circuit for each drive source.

According to the second aspect of the present invention, the ripple components of the output voltage (first to m-th DC voltages) output from the booster can be cut off by the rectifier. Distortion can be suppressed.

According to the third aspect of the present invention, it is possible to drive the drain-source voltage relaxation type inverter circuit only by mounting one booster circuit in a chip such as an IC or LSI. Power consumption can be reduced, a mounting area can be reduced, and an increase in chip cost can be suppressed, as compared with a case where a plurality of one-output booster circuits are individually mounted.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which the booster circuit of the present invention is applied to a booster circuit that outputs two different output voltages will be described below with reference to FIG.
This booster circuit is intended to be mounted on an IC, an LSI, or the like.

First, FIG. 1 shows a circuit configuration of the booster circuit 1. In FIG. 1, an n-channel MOSF
A DC voltage input terminal 17 is connected to a drain of the ET (hereinafter simply referred to as nMOS) 2a, so that a DC voltage VC, which is a voltage, is applied. The nMOS 2a is a rectifier that has a gate connected to its own drain and a substrate grounded to a ground potential VE (for example, 0 V), so that the direction from the drain to the source is a forward direction. The source is connected to one terminal of the capacitor 2b (hereinafter, referred to as + terminal), and the unit booster 2 is configured by the nMOS 2a and the capacitor 2b.

Subsequently, the unit boosters 3 to 5 are connected to the nMOS
The size of each of the capacitors 3a to 5a and the capacitors 3b to 5b is equal to that of the unit booster 2. The unit boosters 2 to 5 are cascade-connected to a plurality of stages in this order, for example, such that the source of the nMOS 2a (first stage) is connected to the drain of the nMOS 3a (second stage). Thus, the first stage booster 6 is composed of the unit boosters 2 to 5.
The source of the last nMOS 5a is connected to the drain of an nMOS 7 connected as a rectifier for preventing ripple, and the source of the nMOS 7 is connected to an output terminal 8 for outputting a voltage VA.

Next, the unit boosters 9 to 11 are nMOS
The units 9a to 11a and the capacitors 9b to 11b are configured to have the same size. The unit boosters 9 to 11 are cascade-connected to a plurality of three stages in this order, and the second booster 12 It is configured. The source of the last nMOS 11a is connected to the drain of an nMOS 13 which is a rectifier for preventing ripple. The source of the nMOS 13 is connected to an output terminal 14 for outputting a voltage VB, and is connected to a sense terminal to be described later. It is connected to the input terminal of the circuit 16. The boosting unit 15 is configured by cascade-connecting these boosting units 6 and 12 in two stages (m = 2) of m (a natural number of 2 or more).

The size of the nMOSs 2a to 5a and the capacitors 2b to 5b of the booster 6 depends on the size of the output terminals 8 and 1.
4 is set such that a current capability larger than the total current consumption by a load (not shown) connected to the load 4 is obtained.
Further, the sizes of the nMOSs 9a to 11a and the capacitors 9b to 11b of the booster 12 are set so as to obtain a current capability larger than a current consumption by a load (not shown) connected to the output terminal 14.

In the sense circuit, an enable signal from an upper control circuit (not shown) is applied to an enable terminal, and a reference voltage Vref from the upper control circuit is applied to a reference terminal. It is supposed to be. In this case, the sense circuit 16 is configured to output a high-level output signal when the DC voltage VB is equal to or lower than the reference voltage Vref, and to output a low-level output signal when the DC voltage VB is opposite. The output terminal of the sense circuit 16 is connected to one input terminal of the NAND circuits 18 and 19.

The clock generation circuit 20 generates a clock signal (CLK signal) of a rectangular wave having a constant cycle repeating high level and low level, and an inverted clock signal (_CLK signal) obtained by inverting this clock signal. Is output from the CLK signal output terminal 20a and the _CLK signal output terminal 20b. And
The CLK signal output terminal 20a is connected to the other input terminal of the NAND circuit 18, and the _CLK signal output terminal 20a
“b” is connected to the other input terminal of the NAND circuit 19. The underbar of the _CLK signal is _CL
The K signal is an inverted signal of the CLK signal.

The NAND circuits 18 and 19 have a high level set to the voltage VC and a low level set to 0V. The output terminal of the NAND circuit 19 is connected to the other terminals of the odd-numbered stage capacitors 2b, 4b, 9b and 11b (hereinafter referred to as "-side terminal"), and the output terminal of the NAND circuit 18 is connected to the even-numbered stage. The capacitors 3b, 5b, and 10b are connected to the other terminals (hereinafter, referred to as negative terminals).

Thus, the NAND circuits 18
, 19 and the clock generation circuit 20 constitute a boost control means 21, and the NAND circuits 18 and 19 and the sense circuit 16 constitute a voltage level control means 22. The booster 15, the boost controller 21, and the voltage level controller 22 constitute the booster circuit 1.

<Description of Operation of Boost Circuit 1> Next, the operation of the booster circuit 1 will be described. First, as an initial state, it is assumed that no charge is accumulated in all the capacitors 2b to 5b and 9b to 11b, and the clock generation circuit 20
Output the CLK signal and the _CLK signal. In this case, since the voltage VB applied to the input terminal of the sense circuit 16 becomes 0 V, a high-level signal is output from the output terminal, whereby the NAND circuits 18 and 19 output the CLK signal and the _CLK signal. Is output.

At this time, first, it is assumed that a low level is output as the CLK signal and a high level is output as the _CLK signal. In this case, since the negative terminal of the capacitor 2b becomes 0V, a forward voltage is applied to the nMOS 2a, and the drain and source of the nMOS 2a are turned on. Then, the capacitor 2b
And the capacitor 2b is charged until the inter-terminal voltage becomes VC.

Subsequently, it is assumed that a high level is output as the CLK signal and a low level is output as the _CLK signal when the CLK signal and the _CLK signal advance by a half cycle. At this time, the voltage of the negative terminal of the capacitor 2b is V
C, and the voltage of the + terminal becomes 2 VC. In this case, a reverse voltage is applied to the nMOS 2a, and the drain and source of the nMOS 2a are turned off. On the other hand, since the negative terminal of the capacitor 3b is at 0 V, a forward voltage of 2VC is applied to the nMOS 3a,
The drain and source are turned on, and the capacitor 3b is charged until the voltage between the terminals becomes 2VC.

As described above, each time the CLK signal and the _CLK signal advance by half a cycle, each capacitor 4
The voltage between the terminals b, 5b, and 9b to 11b is stepped up. That is, the voltage between the terminals of the capacitor 4b is 3
VC, and the voltage between the terminals of the capacitor 5b is 4VC
, And finally the voltage between the terminals of the capacitor 11b is increased to 7VC. And capacitors 5b and 1
The voltages of 4VC and 7VC respectively boosted in 1b are output as voltages VA and VB from the output terminals 8 and 14 via the nMOSs 7 and 13 for preventing ripple.

During such a boosting operation, the voltage level control means 22 performs feedback control of the output voltage VB. In the feedback control, when the output voltage VB is equal to or lower than the reference voltage Vref, the above-described boosting operation is performed by outputting the CLK signal and the _CLK signal from the NAND circuits 18 and 19, and the output voltage VB
When B exceeds the reference voltage Vref, the boosting operation is temporarily stopped by stopping the output of the CLK signal and the _CLK signal, and the output voltage VB is constantly changed to the reference voltage Vr.
ef.

When the booster circuit stops the boosting operation, a low-level enable signal is input to the sense circuit 16 in conjunction therewith, the output signal of the sense circuit 16 becomes low level, and the feedback control is turned off. Is performed.

As described above, according to this embodiment,
The booster 6 in which the unit boosters 2 and 5 are cascaded in four stages, and the booster 12 in which the unit boosters 9 and 11 are also cascaded in three stages are cascaded in two stages in the order of the boosters 6 and 12. As a result, the voltage VA obtained by increasing the DC voltage VC by four times and the voltage VB obtained by increasing the DC voltage VC by n times are output as nM as output voltages from one booster circuit 1.
It can be output via OS7 and OS13. In addition, by performing feedback control by the voltage level control means 22, the voltage VB output from the output terminal 14 is output.
Can be controlled with high accuracy so that the level of the reference voltage is always maintained at the reference voltage Vref. In addition, the level of the voltage VA output from the output terminal 8 is also indirectly controlled, and a stable voltage VA with a reduced amount of fluctuation can be obtained. Accordingly, the booster circuit 1 can be applied to a case where a predetermined circuit using two different voltages VA and VB as drive sources, for example, a drain-source voltage relaxation type inverter circuit is mounted in a chip such as an IC or an LSI. For example, power consumption can be reduced, a mounting area can be reduced, and an increase in chip cost can be suppressed, as compared with a case where an individual booster circuit is mounted for each driving source.

The ripple components of the voltages VA and VB output from the output terminals 8 and 14 are converted into nMOS 7 and 13
Therefore, the DC voltage with suppressed waveform distortion can be output as the output voltage.

[Usage Pattern] Next, pMOS and nMOS
Are used as drive sources of a voltage-relaxed inverter circuit between drain and source (hereinafter simply referred to as a relaxed inverter circuit) using a booster circuit configured by connecting two stages each of which is m stages, respectively. This will be described with reference to FIG.

First, the booster circuit 1 of this usage example boosts a DC voltage VC (for example, 2 V) applied from the outside, and a voltage VA (for example, 10 V) as a first DC voltage and a voltage VB as a second DC voltage. (For example, 20 V).

FIG. 2 shows a circuit configuration of the relaxation type inverter circuit 30. As shown in FIG. In FIG. 2, the booster circuit 1
A second DC voltage input terminal (hereinafter, simply referred to as a second input terminal) 31 for applying the voltage VB output from the
The source of the pMOS 32 is connected. Also, pMO
The drain of S32 is connected to the source of a voltage relaxing pMOS (hereinafter simply referred to as relaxing pMOS) 33, and a voltage relaxing nMOS (hereinafter simply referred to as relaxing nMOS) 3
4 and the drain of the nMOS 35 are connected. That is, the source and the drain of the pMOS 32 and the relaxation pMOS 33 are connected in two stages of m stages in the forward direction, and the drain and source of the relaxation nMOS 34 and nMOS 35 are connected in two stages of m stages in the forward direction. And
The drains of the pMOS 33 and the nMOS 34 are connected to form a series circuit 36, and the nMOS 3
5 is grounded to the ground potential VE (for example, 0 V).

The pMOS 32 and the relaxing pMOS 3
3 is connected to the second input terminal 31, and the mitigation nMO
The substrates of S34 and nMOS 35 are grounded to the ground potential VE. The gates of the pMOS 32 and the nMOS 35 are connected to a common input terminal 37 and
33 and the gates of the mitigation nMOS 34 are connected to a common first DC voltage input terminal (hereinafter simply referred to as a first input terminal) 38 for applying the voltage VA output from the booster circuit 1. And nMOS 34 for relaxation
An output terminal 39 is connected between the two drains.

Further, a pMOS 32 and a relaxation pMOS 3
3. The withstand voltage between the drain and source of the relaxing nMOS 34 and nMOS 35 is set to, for example, 12 V or less. The withstand voltage between the drain and the source of each of the MOSs 32 to 35 may be set to a different value.

<Explanation of Function of Relaxed Inverter Circuit 30>
Next, the operation of the relaxation type inverter circuit 30 will be described. It is assumed that the low level of the input / output signal of the relaxation type inverter circuit 30 is set to the ground potential VE (0 V), and the high level is set to the voltage VB (20 V).

Now, this relaxation type inverter circuit 30
The operation is performed when an operation condition of “ground potential (VE) <first DC voltage (voltage VA) <second DC voltage (voltage VB)” is satisfied. Therefore, FIG.
, 10 V is applied to the first input terminal 38 and the second
When 20 V is applied to the input terminal 31, the above-mentioned operation condition is satisfied, and the relaxed inverter circuit 30 operates normally.

For example, when a low level is applied to the input terminal 37, the pMOS 32 and the relaxing pMOS 33
Is turned on, and the drain and source of the relaxing nMOS 34 and nMOS 35 are turned off, so that the output terminal 39 outputs a high level. Conversely, when a high level is applied to the input terminal 37, the drain and source of the relaxing nMOS 34 and the nMOS 35 are turned on, and the source and drain of the pMOS 32 and the relaxing pMOS 33 are turned off. As a result, a low-level output signal is output from the output terminal 39.

<Relationship Between Voltage Between Drain and Source of Each MOS 32 to 35 and Breakdown Voltage> Next, the relationship between the voltage applied between the drain and source of each MOS 32 to 35 and these breakdown voltages will be described. First of all,
For example, a case where an input signal is switched from a high level to a low level will be described.

In FIG. 2, first, when the input signal is at the high level, since the drain and source of the relaxing nMOS 34 and nMOS 35 are on, the relaxing nMOS
The voltage at the common connection point 40 between the source 34 and the drain of the nMOS 35 is 0V. When the input signal is switched from high level to low level, nMO
Since the voltage between the gate and the source in S35 becomes 0 V, nM
The drain and source of the OS 35 are turned off.

At this time, at the same time, the pMOS 32
Since the source and drain of the pMOS 33 for relaxation are turned on, the voltage at the common connection point 40 increases from 0V to a higher voltage. When the voltage at the common connection point 40 rises to a value (in this case, 9 V) obtained by subtracting the threshold voltage VT (for example, 1 V) between the source and the gate of the relaxing nMOS 34 from the voltage VA (10 V). , The drain and source of the relaxing nMOS 34 are turned off.

Therefore, when a low level is applied to the input terminal 37, the relaxing nMOS 34 and the nMOS
When 35 is turned off, the voltage at the common connection point 40 becomes 9V. Therefore, a voltage of 11 V is applied between the drain and the source of the relaxation nMOS 34, and a voltage of 9 V is applied between the drain and the source of the nMOS 35.
The voltage applied between the drain and the source of both MOSs 34 and 35 can be suppressed to a withstand voltage of 12 V or less.

Next, the case where the input signal is switched from low level to high level will be described. In this case as well, considering the same as above, first, when the input signal is at the low level, the pMOS 32 and the pMOS 33 for mitigation are on, so the voltage at the common connection point 41 between the drain of the pMOS 32 and the source of the pMOS 33 for mitigation Is 20V. When the input signal is switched from the low level to the high level, the voltage between the gate and the source of the pMOS 32 becomes 0 V, so that the source and the drain of the pMOS 32 are turned off.

At this time, at the same time, the relaxation nMO
Since S34 and the drain and source of the nMOS 35 are turned on, the voltage at the common connection point 41 decreases from 20V to a lower voltage. Then, when the voltage at the common connection point falls to a value obtained by subtracting a threshold voltage VT (for example, -1 V) between the source and the gate of the pMOS 33 for relaxation from the voltage VA (10 V) (in this case, 11 V),
The source and drain of the pMOS 33 for relaxation are turned off.

Therefore, when a high level is applied to the input terminal 37, the pMOS 32 and the pMOS
When the switch 33 is turned off, the voltage at the common connection point 41 is 11 V
Becomes Therefore, a voltage of 11 V is applied between the source and the drain of the pMOS 32, and a voltage of 9 V is applied between the source and the drain of the pMOS 33 for relaxation, and applied between the source and the drain of both the MOSs 32 and 33. Voltage can be suppressed to a withstand voltage of 12 V or less.

In this example, the first DC voltage of the relaxation type inverter circuit 30 is set to 10 V. However, as described above, the operation condition of the relaxation type inverter circuit 30 is as follows: "ground potential (VE) < The first DC voltage is not limited to 10 V, as long as the relationship of 1 DC voltage (voltage VA) <second DC voltage (voltage VB) is satisfied.
It can be changed to a predetermined range.

Then, based on these operating conditions, the voltage applied between the drain and the source of each of the MOSs 32 to 35 is obtained by using the value of the first DC voltage as a parameter.
It becomes the value as shown in. That is, in the relaxation type inverter circuit 30, the voltage applied between the drain and the source of each of the MOSs 32 to 35 falls below the withstand voltage 12V when the first DC voltage is set in the range of 9V to 11V. In this range, the moderating inverter circuit 30
Works fine. Accordingly, it is understood that the voltage VA output from the booster circuit need only be substantially stable even if the level is not maintained at a high accuracy and constant (see FIG. 4).

As described above, in the application example using one embodiment, a series circuit in which the pMOS 32, the relaxing pMOS 33, the relaxing nMOS 34, and the nMOS 35 are connected in this order (a series circuit in which each of the pMOS and the nMOS is connected in two stages, respectively). Circuit) and the booster circuit 1 that outputs the voltages VA and VB constitute the relaxed inverter circuit 30. Therefore, only one booster circuit 1 is mounted in a chip such as an IC or LSI. The inverter circuit 30 can be driven. As a result, power consumption can be reduced, a mounting area can be reduced, and an increase in chip cost can be suppressed, as compared with a case where a plurality of single-output booster circuits are individually mounted as in the related art.

The present invention is not limited to the above embodiment, but can be modified and expanded as follows. In one embodiment of the present invention, a booster circuit is formed by cascading boosters in two stages. However, the present invention is not limited to this.
A booster circuit that outputs one or more output voltages may be configured. Further, in the usage example of the present invention, the pMOS and the nMOS are respectively connected in two stages to form the relaxation type inverter circuit. However, the present invention is not limited to this.
The relaxation type inverter circuit may be configured by connecting each of the OS and the nMOS in three or more stages. In that case, the number of connection stages of the booster of the booster circuit is set to the same value.

In the embodiment of the present invention, a rectangular CLK signal and _CL of a fixed cycle outputted from the clock generation circuit are used.
The K signal is supplied to the capacitors 2b to 5b and 9b to 11
The boost control means and the voltage level control means are configured so as to control the boost operation such that the voltage VB always becomes the reference voltage Vref by controlling the timing of application to the negative terminal of b. Is not
For example, by changing the cycle of the CLK signal and the _CLK signal output from the clock generation circuit based on the value of the voltage VB, the boosting control means and the voltage control circuit control the boosting operation so that the voltage VB becomes constant. Level control means may be configured. Similarly, the duty ratio of the CLK signal and the _CLK signal output from the clock generation circuit may be changed.

In the embodiment of the present invention, a rectifier for preventing ripples is provided at the output terminal, but this rectifier may be provided as needed. In the embodiment of the present invention, the boost circuit is applied to a Cockcroft-Walton type, but the present invention is not limited to this. For example, a Rimmelman type,
It may be applied to a Schenkel type or the like.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of a booster circuit showing one embodiment of the present invention.

FIG. 2 is an electric circuit diagram of a drain-source voltage relaxation type inverter circuit showing an example of use of one embodiment;

FIG. 3 is a data diagram showing a settable range of a first DC voltage.

FIG. 4 is a diagram showing a settable range of a first DC voltage.

[Explanation of symbols]

In the drawing, 1 is a booster circuit, 2, 3, 4, 5, 9, 10, 1
1 is a unit booster, 2a, 3a, 4a, 5a, 9a, 10
a and 11a are nMOS (rectifier), 2b, 3b, 4b,
5b, 9b, 10b and 11b are capacitors, 6 and 12 are boosters, 7 and 13 are nMOS (rectifiers for preventing ripple), 15 is booster, 16 is sense circuit, 21 is booster, 21 is voltage level. Control means, 30 is a drain-source voltage relaxation type inverter circuit, 32 is pMO
S (p-channel MOSFET), 33 is a pMOS for relaxation
(P-channel MOSFET), 34 is a relaxation nMOS
(N-channel MOSFET), 35 indicates nOS (n-channel MOSFET), and 36 indicates a series circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) EE12 FF08

Claims (3)

[Claims] 1. A unit booster comprising a rectifier and a capacitor is cascaded in a plurality of stages, and a DC voltage applied to a first unit booster is stepwise boosted and output as an output voltage from the last unit booster. Boosting means configured to cascade-connect m (m is a natural number of 2 or more) stages to output first to m-th DC voltages sequentially increasing from the first stage; Boosting control means for performing a stepwise boosting operation by alternately charging and discharging the capacitors of the odd-numbered and even-numbered stages, and detecting the m-th DC voltage and feeding back the boosting operation of the boosting control means A boosting circuit comprising: voltage level control means for controlling the level of the m-th DC voltage based on the control. 2. The unit booster for outputting the first to m-th DC voltages is connected to a rectifier for preventing ripples. The first to m-th DC voltages are supplied to the rectifier for preventing ripples. 2. The booster circuit according to claim 1, wherein the booster circuit is output via a booster circuit. 3. A p-channel MOS connected m stages in the forward direction.
FET and n-channel MOSFE connected m stages in the forward direction
And a main circuit formed by connecting T and T in series. A first DC voltage is applied between both sources of the p-channel MOSFET and the n-channel MOSFET at both ends of the main circuit, and the other p-channel MOSFET and n Channel MOS
2. The device according to claim 1, wherein the second to m-th DC voltages are applied to the gate of the FET from the end to the center.
Or a drain-source voltage relaxation type inverter circuit comprising the booster circuit according to 2.