KR101612719B1 - Light-receiving element and display device - Google Patents

Abstract

The light receiving element includes: a first conductive semiconductor region configured to be formed on an element formation surface; A second conductive semiconductor region configured to be formed on the element formation surface; An intermediate semiconductor region formed on the element formation surface between the first conductivity type semiconductor region and the second conductivity type semiconductor region and configured to have an impurity concentration lower than that of the first conductivity type semiconductor region and the second conductivity type semiconductor region, . The light receiving element may further include: a first electrode configured to be electrically connected to the first conductivity type semiconductor region; A second electrode configured to be electrically connected to the second conductive semiconductor region; And a control electrode configured to be formed in an opposite region opposite to the intermediate semiconductor region on the element formation surface.

Description

[0001] LIGHT-RECEIVING ELEMENT AND DISPLAY DEVICE [0002]

The present invention relates to a light receiving element including a control electrode and a display device including such a light receiving element.

Cross reference of related application

The present invention includes Japanese Patent Application No. 2008-228255 filed on September 5, 2008 and Japanese Patent Application No. 2007-332100 filed on December 25, 2007, All of the contents disclosed in these applications are incorporated herein by reference.

2. Description of the Related Art In recent years, a light receiving element such as a photodiode, which is used for detecting and controlling the brightness or contrast of a display image in a display device such as a liquid crystal display device and an organic EL display device, is widely used. The photodiode is mounted on a display device together with a display device having a driving circuit composed of a thin film transistor (TFT) or the like.

As one type of such a photodiode, a planar PIN photodiode is known. The PIN photodiode includes an i-type semiconductor (intermediate semiconductor) formed on the surface of the transparent substrate and formed on the p-type semiconductor region and the n-type semiconductor region made of polycrystalline silicon, Region.

For example, Japanese Laid-Open Patent Application No. 2004-119719 proposes a technique of controlling a threshold voltage by using a third electrode (gate electrode) of a PIN photodiode.

As described above, in the display device, in the photodiode formed on the same substrate together with the TFT, the thickness of the semiconductor film must be thinned so as to suppress the leakage current generated when the TFT is in the off state. Therefore, the thickness (volume) of the intermediate semiconductor region as the light receiving section also becomes small, and there arises a problem that the light receiving sensitivity can not be sufficiently secured.

In order to deal with this problem, an attempt has been made to increase the W and L lengths of the gate electrode as a method for increasing the light receiving sensitivity by increasing the volume of the intermediate semiconductor region as the light receiving portion. However, when the W length is increased, the parasitic capacitance also increases in an overlap area between the gate electrode and the p-type semiconductor region or the n-type semiconductor region. Therefore, the effect that the generated photocurrent is absorbed by this parasitic capacitance and effectively improves the photosensitivity is limited. When the length L is increased, if the length L is increased to a value within a range of, for example, about 8 to 10 mu m, the photocurrent is saturated. Therefore, even if the length L is further increased beyond this value, the photocurrent can not be increased.

As described above, since the prior art has a limitation in increasing the photocurrent generated in the light receiving element, it is difficult to sufficiently improve the light receiving sensitivity.

Therefore, the present invention is intended to provide a light receiving element capable of sufficiently improving light receiving sensitivity and a display apparatus including such a light receiving element.

According to an embodiment of the present invention, there is provided a semiconductor device comprising: a first conductive semiconductor region configured to be formed on an element foramtion surface on one side of a substrate; A second conductive semiconductor region configured to be formed on the element formation surface; An intermediate semiconductor region formed on the element formation surface between the first conductivity type semiconductor region and the second conductivity type semiconductor region and configured to have an impurity concentration lower than that of the first conductivity type semiconductor region and the second conductivity type semiconductor region, And a second light receiving element. The first light receiving element may further include: a first electrode configured to be electrically connected to the first conductive type semiconductor region; A second electrode configured to be electrically connected to the second conductive semiconductor region; And a control electrode configured to be formed in an opposite region facing the intermediate semiconductor region via an insulating film to the substrate side of the intermediate semiconductor region. In the first light receiving element, the conductivity type of the impurity injected into the intermediate semiconductor region is p-type, the first electrode is an anode electrode, the second electrode is a cathode electrode, A part of the electrode electrically connected to the anode electrode or the anode electrode is partially overlapped with the region facing the control electrode.
According to another embodiment of the present invention, there is provided a first display device including a plurality of arrayed display elements and a first light receiving element of the present invention.

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In the first light receiving element and the first display apparatus of the present invention, by applying a voltage to the control electrode, it is possible to control the photocurrent generated when light is irradiated to the intermediate semiconductor region as the light receiving portion. Further, since the impurity of the impurity in the intermediate semiconductor region is p-type and the voltage applied to the control electrode is a constant potential, the intermediate semiconductor region has an n-i-p structure along the thickness direction of the light receiving element. Therefore, the electron-hole pairs generated in the depletion layer are rapidly separated into electrons and holes. Therefore, the trap probability of the electron-hole pairs is lowered by the recombination center, and the increase of the L length of the intermediate semiconductor region contributes to the increase of the photocurrent corresponding thereto.

According to another embodiment of the present invention, there is provided a semiconductor device comprising: a first conductive semiconductor region configured to be formed on an element formation surface on one side of a substrate; A second conductive semiconductor region configured to be formed on the element formation surface; And an intermediate semiconductor layer formed on the element formation surface between the first conductivity type semiconductor region and the second conductivity type semiconductor region and configured to have an impurity concentration lower than that of the first conductivity type semiconductor region and the second conductivity type semiconductor region, A second light receiving element is provided. The second light receiving element further comprises: a first electrode configured to be electrically connected to the first conductive type semiconductor region; A second electrode configured to be electrically connected to the second conductive semiconductor region; And a control electrode configured to be formed in an opposite region facing the intermediate semiconductor region via an insulating film to the substrate side of the intermediate semiconductor region. In the second light receiving element, the conductivity type of the impurity in the intermediate semiconductor region is n-type, the first electrode is an anode electrode, the second electrode is a cathode electrode, Or a part of the electrode electrically connected to the anode electrode partially overlaps with the region facing the control electrode.

According to another embodiment of the present invention, there is provided a second display device including a plurality of arrayed display elements and a second light receiving element of the present invention.

In the second light receiving element and the second display apparatus of the present invention, by applying a voltage to the control electrode, it is possible to control the photocurrent generated when light is irradiated to the intermediate semiconductor region as the light receiving portion. Further, the impurity in the intermediate semiconductor region is n-type, and the voltage applied to the control electrode is the negative potential, so that the intermediate semiconductor region has a p-i-n structure along the thickness direction of the light receiving element. Therefore, the electron-hole pairs generated in the depletion layer are rapidly separated into electrons and holes. Therefore, the trap probability of the electron-hole pairs due to the recombination center is lowered, and the increase of the L length of the intermediate semiconductor region contributes to the increase of the photocurrent corresponding thereto.

In the first light receiving element or the first display, the conductivity type of the impurity in the intermediate semiconductor region is p-type, and the voltage applied to the control electrode is the positive potential. Therefore, the electron-hole pairs generated in the depletion layer of the intermediate semiconductor region are quickly separated to promote the generation of the photocurrent. Therefore, even if the L length of the intermediate semiconductor region is increased, the photocurrent does not saturate, and the light receiving sensitivity can be sufficiently improved.

Further, in the second light receiving element or the second display, the impurity of the impurity in the intermediate semiconductor region is n-type, and the voltage applied to the control electrode is the negative potential. The electron-hole pairs generated in the depletion layer of the intermediate semiconductor region are quickly separated to promote the generation of the photocurrent. Therefore, even if the L length of the intermediate semiconductor region is increased, the photocurrent does not saturate, and the light receiving sensitivity can be sufficiently improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Configuration example of light receiving element)

1 shows a planar configuration of a light receiving element (light receiving element 1) according to an embodiment of the present invention. Fig. 2 shows a sectional configuration of the light-receiving element 1 taken along the line II-II in Fig.

The light receiving element 1 is an optical sensor having a so-called PIN photodiode. The light receiving element 1 includes a glass substrate 10, a p + layer 11 as a first conductivity type semiconductor region provided on one surface side of the glass substrate 10, a p + layer 11 as a p + layer 11 on the glass substrate 10 And a light receiving portion 13 as an intermediate semiconductor region provided between the p + layer 11 and the n + layer 12. The n < + > The p + layer 11 is electrically connected to the anode electrode 21 through the contact portion 241 and the n + layer 12 is electrically connected to the cathode electrode 22 through the contact portion 242. In the region of the glass substrate 10 opposed to the light receiving portion 13 on the same surface side as the p + layer 11, the n + layer 12 and the light receiving portion 13, (23) are formed. A gate insulating film 14 is formed between a constituent element group composed of the glass substrate 10 and the gate electrode 23 and a constituent element composed of the p + layer 11, the n + layer 12 and the light receiving portion 13 . an interlayer insulating film 15 is formed between a constituent element group composed of the p + layer 11, the n + layer 12 and the light receiving portion 13 and a constituent element group composed of the anode electrode 21 and the cathode electrode 22 . The anode electrode 21 is electrically connected to the wiring layer 251 and the cathode electrode 22 is electrically connected to the wiring layer 252.

The glass substrate 10 is a transparent substrate having light transmittance. Instead of using the glass substrate 10, a substrate may be formed using a transparent (light-transmitting) material such as plastic, quartz, or aluminum oxide.

The gate insulating film 14 and the interlayer insulating film 15 are made of an insulating material such as silicon nitride (SiN) or silicon oxide (SiO). These films may be formed by depositing a single layer, or may be formed as a mixed layer using a plurality of materials.

The p + layer 11 is formed on the gate insulating film 14 in contact with the light receiving portion 13, and is formed of a p-type semiconductor doped with a high concentration of p-type impurity. The p-type impurity is, for example, boron. The p-type semiconductor is preferably, for example, a crystalline semiconductor. This is because the crystalline semiconductor can provide high carrier mobility. Examples of the crystalline semiconductor include polycrystalline silicon (polysilicon). The p + layer 11 made of polycrystalline silicon is formed by depositing amorphous silicon (amorphous silicon) by CVD (Chemical Vapor Deposition), irradiating with laser light such as an excimer laser, melting and solidifying . Therefore, since the light-receiving element 1 can be manufactured on the same substrate together with the driving circuit composed of TFT or the like, the display device described below preferably includes the light-receiving element 1. [

The n + layer 12 is formed on the gate insulating film 14 in contact with the light receiving portion 13, and is formed of an n-type semiconductor doped with an n-type impurity at a high concentration. The n-type impurity is, for example, phosphorus. The n-type semiconductor is preferably, for example, a crystalline semiconductor. This is because, similarly to the p-type semiconductor, high carrier mobility can be obtained. Examples of crystalline semiconductors include crystalline silicon. The n + layer 12 made of polycrystalline silicon is preferable because it can be formed by the same manufacturing method as that of the p + layer 11, for example.

The light receiving portion 13 is a light receiving region of the light receiving element 1 and is formed in contact with these layers on the gate insulating film 14 between the p + layer 11 and the n + The light receiving section 13 is formed in the intermediate semiconductor region (the p-type semiconductor region) 12 formed so as to have an impurity (n-type impurity) concentration (for example, in the range of about 1 x 10 ^{17 to} 5 x 10 ¹⁸ (atm / cm ³ ) n-layer). The light receiving portion 13 may include a non-single crystal semiconductor layer. Examples of the material of the non-single crystal semiconductor layer include amorphous silicon, microcrystalline silicon, or polycrystalline silicon.

The thickness of the non-single crystal semiconductor layer is preferably as large as possible, and for example, a thickness in the range of about 30 to 60 nm is preferable. The reason is that if the thickness is thinner than this range, the photocurrent generated in the light receiving portion 13 is reduced, and if the thickness is thicker than this range, the leakage current is increased. The crystal grain size of the polycrystalline silicon is preferably in the range of about 50 nm to 1 mu m. In the case of using microcrystalline silicon formed by the CVD method instead of using the laser irradiation described above, the crystal grain size is preferably within a range of about 10 to 100 nm.

The anode electrode 21 is electrically connected to the p + layer 11 and is made of a conductive material.

The cathode electrode 22 is electrically connected to the n + layer 12, and is made of a conductive material in the same manner as the anode electrode 21.

The gate electrode 23 is formed in a region opposed to the light receiving portion 13 via the gate insulating film 14. The gate electrode 23 functions as a control electrode capable of controlling the photocurrent generated when light is applied to the light receiving section 13 by applying a voltage. In this embodiment, the conductivity type of the impurity (n-type impurity) in the light receiving portion 13 is n-type, and the voltage applied to the gate electrode 23 is the negative potential.

(Function and effect of light receiving element)

With reference to Figs. 3 to 8 in addition to Figs. 1 and 2, the operation and effect of the light receiving element 1 of the present embodiment will be described in detail below in comparison with a comparative example.

First, referring to Fig. 1 and Fig. 2, the basic operation of the light receiving element 1 will be described below. In the light-receiving element 1, when light is irradiated to the light-receiving portion 13 (light is incident on the light-receiving portion 13), a photocurrent is generated in the light-receiving portion 13 according to the amount of incident light to form the p + layer 11 and the n + 12 so that the light receiving element 10 functions as a light receiving element.

Next, the characteristic actions and effects of the light-receiving element 1 will be described below with reference to Figs. 3 to 8, in comparison with the comparative examples. 3 shows a planar configuration of a light receiving element (light receiving element 100) according to a comparative example. 4 shows a sectional configuration of the light-receiving element 1 along the line III-III in Fig.

In the light receiving element 100 of the comparative example, the voltage applied to the gate electrode 23 is negative, unlike the light receiving element 1 of the present embodiment. The conductivity type of the impurity (p-type impurity) in the light receiving portion 103 is p-type, or the light receiving portion 103 is an intrinsic layer (I-layer).

With this configuration, when the conductive type of the impurity (p-type impurity) in the light receiving portion 103 is p-type, when the light receiving element 100 is irradiated with light, the light receiving portion 103 ), No depletion layer is generated, and no photocurrent is generated. When the light receiving section 103 is an intrinsic layer (I layer), the number of recombination centers in the light receiving section 103 as the intermediate semiconductor region is increased. Therefore, in a situation where the electron-hole pairs generated in the light-receiving portion 103 travel over a long L-length, these electron-hole pairs are easily captured at the recombination center, and thus do not contribute to generation of photocurrent. Therefore, when the L length L1 of the gate electrode 23 is increased to increase the L length of the light receiving portion 103, for example, as shown by the broken line G100 in FIG. 5, (L1 = about 10 mu m), the photocurrent is saturated.

In contrast, in the light receiving element 1 of the present embodiment, the impurity (n-type impurity) in the light receiving portion 13 has the n-type conductivity and the voltage applied to the gate electrode 23 is the negative potential. Thus, when the light receiving section 13 is irradiated with light, the light receiving section 13 as an intermediate semiconductor region has a p-i-n structure along the thickness direction of the light receiving element 1. [ Therefore, the electron-hole pairs generated in the depletion layer are rapidly separated into electrons and holes. Therefore, the trap probability of the electron-hole pairs is lowered by the recombination center, and the increase of the L length of the light receiving portion 13 contributes to the increase of the photocurrent corresponding thereto (to promote the generation of the photocurrent).

 As a result, for example, as shown by the solid line of G1 in Fig. 5, the increase in L length can linearly increase the photocurrent to a wide range (range of 20 to 40 mu m as a range of L1) The light receiving sensitivity can be sufficiently improved.

6, by applying a reverse bias voltage between the anode electrode 21 and the cathode electrode 22 of the light receiving element 1 by using the variable voltage power supply V1, Characteristics can be known. Specifically, for example, as shown in Fig. 7, the magnitude (light-receiving sensitivity) of the generated photocurrent is larger than the voltage Vng (gate voltage Vg) between the n + layer 12 and the gate electrode 23 It can be seen that there is an optimal range (in Fig. 7, the optimal range is -6 to -9 V).

The parasitic capacitance generating region which is the overlap region between the gate electrode 23 and the p + layer 11 or the n + layer 12 does not increase even when the L length L1 is increased. Therefore, the shape of the light receiving element 1 The flexibility of the system is also improved.

In this case, as shown in Fig. 8, for example, the impurity concentration in the light receiving section 13 is preferably about 2 x 10 ¹⁸ (atm / cm ³ ) or less. This is because the impurity concentration higher than this value causes a sharp fluctuation of the breakdown voltage (breakdown voltage) upon application of the gate voltage Vg.

As described above, in this embodiment, the conductivity type of the impurity in the light receiving portion 13 is n-type, and the voltage applied to the gate electrode 23 is the negative potential. Therefore, the electron-hole pairs generated in the depletion layer in the light-receiving portion 13 can be quickly separated, and the generation of the photocurrent can be promoted. Therefore, even if the length L is increased, the photocurrent does not saturate (the increase of the length L can linearly increase the photocurrent in a wide range), and the light receiving sensitivity can be sufficiently improved.

(Modified example)

Modifications to the embodiment of the present invention will be described below. The same reference numerals are given to the same constituent elements as those in the above-described embodiment, and a description thereof will be omitted.

[First Modification]

Fig. 9 shows a planar configuration of the light-receiving element (light-receiving element 1A) according to the first modification. Fig. 10 shows a sectional configuration of the light receiving element 1A along the line IV-IV in Fig. In the light receiving element 1A, the conductivity type of the impurity (p-type impurity) in the light receiving portion 13A is p-type, and the voltage applied to the gate electrode 23 is a constant potential. That is, the light receiving portion 13A is a p-layer.

Further, in the light receiving element 1A of this modification of this configuration, the generation of the photocurrent can be promoted and the light receiving sensitivity can be sufficiently improved by the action similar to the above-described embodiment.

[Second Modification]

11 shows a sectional configuration of a light receiving element (light receiving element 1B) according to the second modification. In the above-described embodiment and the first modification, the gate electrode 23 is connected to the bottom-gate light receiving element formed below the p + layer 11, the n + layer 12 and the light receiving section 13 . On the other hand, the light-receiving element 1B is a top-gate light-receiving element in which the gate electrode 23B is formed on the p + layer 11, the n + layer 12, and the light- Interlayer insulating films 161 and 162 and a gate insulating film 14B are formed in the light receiving element 1B.

In the light receiving element 1B, when the conductivity type of the impurity (p-type impurity) in the light receiving portion 13 is p-type, the voltage applied to the gate electrode 23B is a constant potential. On the other hand, when the conductivity type of the impurity (n-type impurity) in the light receiving portion 13 is n-type, the voltage applied to the gate electrode 23B is the negative potential.

Also in the light receiving element 1B of this modification of this configuration, the generation of the photocurrent can be promoted and the light receiving sensitivity can be sufficiently improved by the action similar to the above-described embodiment and the first modification.

[Third Modified Example and Fourth Modified Example]

12A and 12B show sectional configurations of light receiving elements (light receiving elements 1C and 1D) according to Modification 3 and Modification 4, respectively.

In the light receiving element 1C, the cathode electrode 22C has an opposing region d12 opposed to the gate electrode 23 via at least a part of the light receiving portion 13. Further, the light receiving portion 13 is formed so that the impurity (n-type impurity) concentration is lower than the impurity concentration of the n + layer 12 (i.e., formed as an n-layer). Further, at the time of light irradiation, the gate voltage Vg at the negative potential is applied to the gate electrode 23.

In the light receiving element 1D, the anode electrode 21D has an opposing region d11 opposed to the gate electrode 23 via at least a part of the light receiving portion 13A. Further, the light receiving portion 13A is formed so that the concentration of the impurity (p-type impurity) is lower than the impurity concentration of the p + layer 11 (that is, formed as a p-layer). At the time of light irradiation, the gate voltage (Vg) of the positive potential is applied to the gate electrode (23).

The following advantages can be obtained in the light receiving elements 1C and 1D according to the third modification and the fourth modification. More specifically, in the light-receiving element 1C shown in Fig. 13, when a negative voltage is applied to the gate electrode 23, the voltage applied to the opposing region d12 of the cathode electrode 22C causes the back channel back -channel side is prevented from being infinitely lifted to the negative electrode side. Therefore, the generation of the region 13P which changes into the p-type region in the light receiving portion 13 which is the n-layer is suppressed. Thereby, the electric field generated between the region 13P and the n + layer 12 changed to the p-type region in the light-receiving unit 13 is relaxed, and a breakdown phenomenon hardly occurs. Therefore, the manufacturing yield can also be improved. Further, similar advantageous effects can be obtained by the same action in the light receiving element 1D.

[Fifth Modified Example and Sixth Embodiment]

Figs. 14A and 14B show sectional configurations of the light receiving elements (light receiving elements 1E and 1F) according to the fifth and sixth embodiments, respectively. These light receiving elements 1E and 1F are top gate type light receiving elements provided with the same opposing area as the opposing area described in the third and fourth modified examples.

The electrode 262 electrically connected to the cathode electrode 22E through the contact portion 244 in the light receiving element 1E is opposed to the gate electrode 23B via at least a part of the region of the light receiving portion 13, And an opposing region d22. The electrode 261 electrically connected to the anode electrode 21F through the contact portion 243 in the light receiving element 1F is electrically connected to the gate electrode 23B via at least a part of the light receiving portion 13A And an opposing facing region d21.

In the light receiving elements 1E and 1F according to the fifth and sixth embodiments having such a configuration, the yield phenomenon hardly occurs due to the same operation as that of the third and fourth modifications, Can be improved.

[Seventh Modification]

Fig. 15 shows a planar configuration of a light-receiving element (light-receiving element 1G) according to the seventh modification. Fig. 16 shows a sectional configuration of the light receiving element 1G along the line V-V in Fig.

In the light receiving element 1G of this modification, the light receiving portion 13 is formed so that the impurity (n-type impurity) concentration is lower than the impurity concentration of the n + layer 12 (that is, formed as an n-layer). At the time of light irradiation, the gate voltage Vg at the negative potential is applied to the gate electrode 23.

In addition, in the light receiving element 1G, the boundary portion Bn between the light receiving portion 13 (n - layer) and the n + layer 12 is larger than the edge En close to the n + layer 12 of the gate electrode 23, (I.e., closer to the outside) than the opposite end of the layer 12. This boundary portion Bn may be located above the end En.

This structure is intended to avoid problems related to the pressure resistance, which will be described later. Specifically, when the impurity type of the impurity in the light receiving portion 13 (n-layer) is n-type and the voltage Vg applied to the gate electrode 23 is the negative potential, the gate voltage Vg becomes a constant voltage , There arises a problem with the breakdown voltage between the n + layer 12 and the light receiving portion 13 (n- layer).

More specifically, in this case, holes are induced in the light receiving portion 13 (n-layer) on the gate electrode 23, and the interface (boundary portion A pn junction is formed in the vicinity of Bn).

Here, since the internal electric field is strong between the p- region and the n + region in the entire p-n junction formed by the induced holes, there arises a problem related to the breakdown voltage.

However, if an n-layer, which is not easily affected by the electric field by the gate electrode 23, can be provided between the p- region and the n + region in the pn junction, the internal electric field between the p- region and the n + So that the breakdown voltage can be improved.

Therefore, in the light receiving element 1G of this modification, the boundary Bn is closer to the opposite end of the n + layer 12 than the end En of the gate electrode 23 close to the n + layer 12 ). ≪ / RTI > This structure reduces the influence of the electric field from the gate electrode 23. Therefore, by solving the electric field between the n + region and the n < - > region, a problem related to the breakdown voltage can be avoided and the sensitivity of the light receiving element can be improved to enable stable operation.

17 shows the relationship between the gate voltage Vgn and the photocurrent Inp in the light receiving element 1G. 17, Vnp is 6.0 V, and the impurity concentration in the light receiving section 13 is 1 x 10 ¹⁸ (atm / cm ³ ). The data in FIG. 17 is based on the position of the boundary Bn for each position changed from + 1.5 μm to -0.25 μm. 15, the " + "sign of the position of the boundary Bn indicates that the boundary Bn is closer to the end opposite to the n + layer 12 than the edge En (i.e., closer to the outside) . On the other hand, the sign "- " means that the boundary portion Bn is closer to the center of the light receiving portion 13 (i.e., closer to the inner side) than the end En.

17, attention is focused on the photocurrent Inp obtained when Vgn of -8 V is applied. When the boundary Bn is closer to the center of the light receiving portion 13 than to the end En (i.e., closer to the inside) 1.0 x 10 < ^{-9 &} gt ^; A photocurrent (Inp) of A or more flows, which indicates that there is a problem with the breakdown voltage. On the other hand, when the boundary Bn is located closer to the opposite end of the n + layer 12 than the edge En (i.e., closer to the outside), there is no problem of withstand voltage.

18 shows the relationship between the impurity concentration of the light-receiving portion 13 and the photocurrent Inp in the light-receiving element 1G. 18, the gate voltage Vgn is -8V, and the position of the boundary Bn is 0.0 占 퐉 (that is, positioned on the end En).

Fig. 18 shows that, when the conductivity type of the impurity is n-type, the impurity concentration should be 2 x 10 ¹⁸ (atm / cm ³ ) or less.

[Modification 8]

Fig. 19 shows a planar configuration of a light-receiving element (light-receiving element 1H) according to the eighth modification. Fig. 20 shows a sectional configuration of the light receiving element 1H along the line VI-VI in Fig.

In the light receiving element 1H of this modification, the light receiving portion 13A is formed so that the impurity (p-type impurity) concentration is lower than the impurity concentration of the p + layer 11 (that is, formed as a p-layer). Further, at the time of light irradiation, the gate voltage Vg of the positive potential is applied to the gate electrode 23. [

In this light receiving element 1H, the boundary portion Bp between the light receiving portion 13A (p-layer) and the p + layer 11 is larger than the edge Ep close to the p + layer 11 of the gate electrode 23 (Closer to the outer side) to the end of the p + layer 11 on the opposite side to the boundary Bp. This boundary portion Bp may be located on the end Ep.

This structure is for avoiding the problem of the withstand voltage described in the seventh modification, similarly to the light receiving element 1G of the seventh modification.

Therefore, in the light receiving element 1H of the present modification, the boundary portion Bp is located closer to the opposite end of the gate electrode 23 than the end Ep closer to the p + layer 11, opposite to the p + layer 11. [ This structure reduces the influence of the electric field from the gate electrode 23. Thus, by alleviating the electric field between the p + region and the p- region, it is possible to avoid a problem related to the breakdown voltage, and the sensitivity of the light receiving element can be improved to enable stable operation.

21 shows the relationship between the gate voltage Vgn and the photocurrent Inp in the light receiving element 1H. 21, Vnp is 6.0 V, and the impurity concentration in the light receiving section 13A is 1 x 10 ¹⁸ (atm / cm ³ ). The data in Fig. 21 is based on a change in the position of the boundary portion Bp from + 1.5 占 퐉 to -0.25 占 퐉 for each position. 19, the " + "sign of the position of the boundary portion Bp indicates that the boundary portion Bp is closer to the end portion opposite to the p + layer 11 (i.e., closer to the outer side) than the end portion Ep . On the other hand, the sign "-" means that the boundary portion Bp is closer to the center of the light receiving portion 13A (p-layer) (that is, closer to the inner side) than the end Ep.

Referring to FIG. 21, attention is focused on the photocurrent Inp obtained when 2 V of Vgn is applied. The boundary Bp is closer to the center of the light receiving portion 13A (p-layer) 1.0 x 10 < ^{-9 &} gt ^; A photocurrent (Inp) of A or higher flows, which indicates that there is a problem with the breakdown voltage. On the other hand, when the boundary portion Bp is located closer to the opposite side end of the p + layer 11 than the end Ep, the problem of withstand voltage does not occur.

22 shows the relationship between the impurity concentration of the light-receiving portion 13A and the photocurrent Inp in the light-receiving element 1H. 22, the gate voltage Vgn is 8 V, and the position of the boundary portion Bp is 0.0 占 퐉 (i.e., the boundary portion Bp is located on the end portion Ep).

22 shows that when the conductivity type of the impurity is p-type, the impurity concentration should be 2 x 10 ¹⁸ (atm / cm ³ ) or less.

[Ninth Modified Example]

23 shows a circuit configuration of the light receiving element according to the ninth modification. The circuit of the light-receiving element of this modification is composed of two light-receiving elements 1a and 1b (each composed of the above-described light-receiving element 1 or another light-receiving element). Specifically, two light receiving elements 1a and 1b connected in series to each other are arranged between the power supply VDD and the ground GND.

In the case of the light receiving element 1a, the cathode electrode 22 is connected to the power supply VDD, the anode electrode 21 is connected to the terminal B and the output terminal OUTPUT, and the gate electrode 23 is connected to the terminal A). In the case of the light receiving element 1b, the cathode electrode 22 is connected to the terminal B and the output terminal OUTPUT, the anode electrode 21 is connected to the ground GND, and the gate electrode 23 is connected to the terminal C.

The light receiving element 1b is disposed under the black matrix BM (within the formation area of the black matrix BM) in order to compensate for environmental disturbance. On the other hand, the light-receiving element 1a is arranged at a portion other than the formation region of the black matrix BM so that the illuminance can be measured.

Boron is ion-implanted into the p-type region of the light receiving section 13 of the light receiving elements 1a and 1b. The boron concentration should be not more than 2 x 10 ¹⁸ (atm / cm ³ ) and not more than 1.5 x 10 ¹⁶ to 3.5 x 10 ¹⁷ (atm / cm ³ ).

 It is desirable that the potentials VA, VB, and VC of the terminals A, B, and C, the power supply VDD, and the ground GND shown in FIG. 23 are designed to satisfy the following formula (1). The reason is that,

This is because satisfying equation (1) enables stable output of photocurrent.

GND <VC <VB <VA <VDD (1)

The embodiments of the present invention and modifications thereof have been described above. However, the present invention is not limited to this embodiment and the like, and various modifications are possible.

For example, the cathode electrode or the electrode electrically connected to the cathode electrode and the anode electrode or the electrode electrically connected to the anode electrode described in the embodiment (at least the opposed regions d11, d12, d21, d22 ) Is preferably a transparent electrode made of a transparent material such as indium tin oxide (ITO). This configuration improves the incident efficiency of light with respect to the light receiving portion, so that the light receiving sensitivity can be further improved.

The effect of the present invention is not limited to the effect on visible light, but effects can be obtained on non-visible light (e.g., X-rays, electron beams, ultraviolet light, infrared light). Particularly, when the present invention is used for light in the vicinity of the band gap of the semi-conductor layer, an effective light receiving element can be obtained.

Further, in the embodiment of the present invention, a silicon thin film is mainly used as a semiconductor layer, but any material can be used for the semiconductor layer as long as it is a semiconductor material which can be controlled by an electric field. Examples of other materials include SiGe, Ge, Se, an organic semiconductor film, an oxide semiconductor film, and the like.

The light-receiving element according to the embodiment of the present invention can be applied to a display device including a display element and a light-receiving element, such as the liquid crystal display device 4 and the organic EL display device 5 shown in Figs. 24 to 27 Can be applied. Thus, it is possible to receive ambient light from the outside and display light from the display unit 48 or the like, to control the display data, the amount of light of the backlight, and the like, and to provide a touch panel function, a fingerprint input function, Functioning as a multi-function display. Specifically, the liquid crystal display device 4 shown in Fig. 24 includes the N-type TFT 3N and the P-type TFT 3P such as the light receiving element 1 described in the above-described embodiments and the like. The N-type TFT 3N includes a source electrode 3N21, a drain electrode 3N22, gate electrodes 3N231 and 3N232, channel layers 3N131 and 3N132, an n + layer 3N12 and an LDD (Lightly Doped Drain) 3N14). The P-type TFT 3P has a source electrode 3P22, a drain electrode 3P21, a gate electrode 3P23, a channel layer 3P13, and a p + layer 3P11. The liquid crystal display device 4 further includes a planarization film 41, a pixel electrode 421, a common electrode 422, a liquid crystal layer 43, a spacer 44, an overcoat layer 45, a black matrix layer 46, A color filter layer 47, and a glass substrate 40. 25, the data lines DL, the gate lines G11 to GL3, the power source line VDD, the ground line GND (not shown), and the like are connected to the pixels 49 in the display unit 48. [ ), The common line COM, the reading line RL, the liquid crystal element LC, the light receiving element 1, the pixel selecting TFT elements SW1 and SW3, the capacitive element C1 and the source follower element SF ) Are formed in the pixel circuit. The organic EL display device 5 shown in Fig. 26 includes the n-type TFT 3N, the p-type TFT 3P, the planarization film 51, the anode 5, and the like, such as the light receiving element 1 according to the above- The light emitting layer 53, the resin layer 54, the overcoat layer 55, the black matrix layer 56, the color filter layer 57, and the glass substrate 50 . The position of the light receiving element 1 and the like is not limited to the pixel 49 and the light receiving element 1 or the like may be disposed in the vicinity of the display unit 48 as in the liquid crystal display 4A shown in Fig. Area. &Lt; / RTI &gt;

The configurations and the like according to the above-described embodiments and the like may be combined with each other.

Those skilled in the art will appreciate that various modifications, combinations, subcombinations, and alterations of the present invention are possible in accordance with design requirements and other factors as long as they are within the scope of the appended claims or their equivalents.

1 is a plan view showing a configuration of a light receiving element according to an embodiment of the present invention.

2 is a cross-sectional view showing the configuration of the light-receiving element shown in Fig.

3 is a plan view showing a configuration of a light receiving element according to a comparative example.

4 is a cross-sectional view showing a configuration of a light receiving element according to a comparative example shown in Fig.

Fig. 5 is a characteristic diagram showing the relationship between the length L of the gate electrode and the photocurrent in the light-receiving element shown in Figs. 1 and 3. Fig.

Fig. 6 is a circuit diagram for explaining a circuit used for measuring light-receiving characteristics of the light-receiving element shown in Fig.

7 is a characteristic diagram showing the relationship between the gate voltage and the photocurrent in the light receiving element shown in Fig.

Fig. 8 is a characteristic diagram showing the relationship between the impurity concentration and the breakdown voltage of the light-receiving unit in the light-receiving element shown in Fig.

9 is a plan view showing a configuration of a light receiving element according to a first modification of the embodiment of the present invention.

10 is a cross-sectional view showing a configuration of a light receiving element according to the first modification shown in Fig.

11 is a cross-sectional view showing a configuration of a light receiving element according to a second modification of the embodiment of the present invention.

12A and 12B are cross-sectional views showing the configuration of the light receiving element according to the third and fourth modifications of the embodiment of the present invention, respectively.

13 is a cross-sectional view for explaining a characteristic operation of the light receiving element according to the third modification shown in Fig. 12A.

Figs. 14A and 14B are cross-sectional views showing the configuration of the light receiving element according to the fifth and sixth modifications of the embodiment of the present invention, respectively.

15 is a plan view showing a configuration of a light receiving element according to a seventh modification of the embodiment of the present invention.

16 is a cross-sectional view showing a configuration of a light receiving element according to a seventh modification shown in Fig.

17 is a characteristic diagram showing the relationship between the gate voltage and the photocurrent in the light receiving element according to the seventh modification shown in Fig.

Fig. 18 is a characteristic diagram showing the relationship between the impurity concentration and the photocurrent of the light-receiving unit in the light-receiving element according to the seventh modification shown in Fig. 15. Fig.

19 is a plan view showing a configuration of a light receiving element according to an eighth modification of the embodiment of the present invention.

20 is a cross-sectional view showing a configuration of a light receiving element according to an eighth modification shown in Fig.

21 is a characteristic diagram showing the relationship between the gate voltage and the photocurrent in the light receiving element according to the eighth modification shown in Fig.

22 is a characteristic diagram showing the relationship between the impurity concentration and the photoelectric current of the light receiving section in the light receiving element according to the eighth modification shown in Fig.

23 is a circuit diagram showing a configuration of a light receiving element according to a ninth modification of the embodiment of the present invention.

24 is a cross-sectional view showing an example of a liquid crystal display device including the light receiving element shown in Fig.

25 is a plan view and a circuit diagram showing an example of a pixel circuit in the liquid crystal display device shown in Fig.

26 is a cross-sectional view showing an example of an organic EL display device including the light receiving element shown in Fig.

27 is a plan view showing another example of the liquid crystal display device including the light receiving element shown in Fig.

Claims (18)

A first conductive semiconductor region configured to be formed on an element foramtion surface on one side of the substrate; A second conductive semiconductor region configured to be formed on the element formation surface; An intermediate semiconductor region formed on the element formation surface between the first conductivity type semiconductor region and the second conductivity type semiconductor region and configured to have an impurity concentration lower than that of the first conductivity type semiconductor region and the second conductivity type semiconductor region, ; A first electrode configured to be electrically connected to the first conductive type semiconductor region; A second electrode configured to be electrically connected to the second conductive semiconductor region; And A control electrode formed to be opposed to the intermediate semiconductor region and opposed to the intermediate semiconductor region via the insulating film; Wherein the conductivity type of the impurity implanted in the intermediate semiconductor region is p-type, Wherein the first electrode is an anode electrode and the second electrode is a cathode electrode, Wherein a part of the electrode electrically connected to the anode electrode or the anode electrode is partially overlapped with a region facing the control electrode, Receiving element. The method according to claim 1, And the impurity concentration of the intermediate semiconductor region is 2 x 10 ¹⁸ (atm / cm ³ ) or less. The method according to claim 1, Wherein the first conductivity type semiconductor region, the second conductivity type semiconductor region, and the intermediate semiconductor region comprise a non-single-crystal layer made of polycrystalline silicon. The method of claim 3, Wherein the thickness of the non-single crystal semiconductor layer is 30 nm or more and 60 nm or less. 5. The method according to any one of claims 1 to 4, Wherein a boundary between the intermediate semiconductor region and the first conductivity type semiconductor region is located on an end near the first conductivity type semiconductor region of the control electrode or between the first conductivity type semiconductor region and the first conductivity type semiconductor region, And the light receiving element is located on the region side. A first conductive semiconductor region configured to be formed on an element formation surface on one side of the substrate; A second conductive semiconductor region configured to be formed on the element formation surface; An intermediate semiconductor region formed on the element formation surface between the first conductivity type semiconductor region and the second conductivity type semiconductor region and configured to have an impurity concentration lower than that of the first conductivity type semiconductor region and the second conductivity type semiconductor region, ; A first electrode configured to be electrically connected to the first conductive type semiconductor region; A second electrode configured to be electrically connected to the second conductive semiconductor region; And A control electrode configured to be formed on the substrate side of the intermediate semiconductor region with an insulating film therebetween in an opposite region facing the intermediate semiconductor region; / RTI &gt; The conductivity type of the impurity implanted into the intermediate semiconductor region is n-type, Wherein the first electrode is an anode electrode and the second electrode is a cathode electrode, Wherein a part of the electrode electrically connected to the anode electrode or the anode electrode is partially overlapped with a region facing the control electrode, Receiving element. The method according to claim 6, And the impurity concentration of the intermediate semiconductor region is 2 x 10 ¹⁸ (atm / cm ³ ) or less. The method according to claim 6, Wherein the first conductivity type semiconductor region, the second conductivity type semiconductor region, and the intermediate semiconductor region comprise a non-single crystal semiconductor layer composed of polycrystalline silicon. 9. The method of claim 8, Wherein the thickness of the non-single crystal semiconductor layer is 30 nm or more and 60 nm or less. 10. The method according to any one of claims 6 to 9, Wherein a boundary portion between the intermediate semiconductor region and the second conductivity type semiconductor region is located on an end portion closer to the second conductivity type semiconductor region of the control electrode or on the side of the second conductivity type semiconductor region than the end portion, device. A display device comprising a plurality of display elements and a light receiving element arranged, The light- A first conductive semiconductor region configured to be formed on an element formation surface on one side of the substrate; A second conductive semiconductor region configured to be formed on the element formation surface; An intermediate semiconductor region formed on the element formation surface between the first conductivity type semiconductor region and the second conductivity type semiconductor region and configured to have an impurity concentration lower than that of the first conductivity type semiconductor region and the second conductivity type semiconductor region, ; A first electrode configured to be electrically connected to the first conductive type semiconductor region; A second electrode configured to be electrically connected to the second conductive semiconductor region; And A control electrode configured to be formed on the substrate side of the intermediate semiconductor region with an insulating film therebetween in an opposite region facing the intermediate semiconductor region; / RTI &gt; The conductivity type of the impurity implanted into the intermediate semiconductor region is p-type, Wherein the first electrode is an anode electrode and the second electrode is a cathode electrode, Wherein a part of the electrode electrically connected to the anode electrode or the anode electrode is partially overlapped with a region facing the control electrode, Display device. A display device comprising a plurality of display elements and a light receiving element arranged, The light- A first conductive semiconductor region configured to be formed on an element formation surface on one side of the substrate; A second conductive semiconductor region configured to be formed on the element formation surface; An intermediate semiconductor region formed on the element formation surface between the first conductivity type semiconductor region and the second conductivity type semiconductor region and configured to have an impurity concentration lower than that of the first conductivity type semiconductor region and the second conductivity type semiconductor region, ; A first electrode configured to be electrically connected to the first conductive type semiconductor region; A second electrode configured to be electrically connected to the second conductive semiconductor region; And A control electrode configured to be formed on the substrate side of the intermediate semiconductor region with an insulating film therebetween in an opposite region facing the intermediate semiconductor region; / RTI &gt; The conductivity type of the impurity implanted into the intermediate semiconductor region is n-type, Wherein the first electrode is an anode electrode and the second electrode is a cathode electrode, Wherein a part of the electrode electrically connected to the anode electrode or the anode electrode is partially overlapped with a region facing the control electrode,  Display device. delete delete delete delete delete delete

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