KR101612133B1 - Metal Wrap Through type solar cell and method for fabricating the same - Google Patents

Abstract

The present invention relates to a MWT solar cell capable of improving the photoelectric conversion efficiency of a solar cell by minimizing the recombination rate of carriers by applying an amorphous silicon thin film having excellent passivation characteristics and a method of manufacturing the same. A method of manufacturing a battery includes the steps of preparing a p-type silicon substrate provided with a via hole, performing a diffusion process to form an emitter layer on the entire surface of the substrate, and forming an intrinsic layer, an amorphous semiconductor layer, And a step of forming an n-electrode, a p-electrode, a via-electrode, and a grid line.

Description

[0001] The present invention relates to a MWT solar cell and a manufacturing method thereof,

The present invention relates to a MWT solar cell and a manufacturing method thereof, and more particularly, to a MWT solar cell capable of improving photoelectric conversion efficiency of a solar cell by minimizing the recombination rate of carriers by applying an amorphous silicon thin film excellent in passivation characteristics A battery and a manufacturing method thereof.

A solar cell is a core element of solar power generation that converts sunlight directly into electricity. Basically, it is a diode made of p-n junction. When the sunlight is incident on the solar cell, electrons and holes (pairs) are generated. The generated electrons and holes are diffused, and then the electrons generated by the electric field formed in the pn junction And the hole moves to the p-layer, so that the photovoltaic power is generated between the pn junctions. When the system is connected to both ends of the solar cell, current flows and the power can be produced.

In general, the structure of a solar cell has a structure in which a front electrode and a rear electrode are provided on a front surface and a rear surface, respectively. Since the front electrode is provided on the front surface of the light receiving surface, the light receiving area is reduced by the area of the front electrode. In order to solve the problem of reducing the light receiving area, a rear electrode type solar cell has been proposed. The back electrode type solar cell is provided with a (+) electrode and a (-) electrode on the rear surface of the solar cell, thereby maximizing the light receiving area of the solar cell front surface.

Such a back electrode type solar cell is classified into interdigitated back contact (IBC), point contact type, emitter wrap through (EWT), and metal wrap through (MWT) depending on the type. Among them, the MWT type solar cell has a grid finger of a front side and a grid finger of a bus bar, which are left on the front side and a bus bar is moved to the rear side. The grid finger on the front side and the bus bar on the rear side And is connected by a via hole.

1, an emitter layer 102 is provided on the entire surface of the substrate 101. An antireflection film 103 and a front grid electrode 104 (not shown) are formed on the front surface of the substrate 101, . An n-electrode 105 and a p-electrode 106 are provided on the rear surface of the substrate 101. The n-electrode 105 and the front grid electrode 104 are connected to each other through a via hole 108 passing through the substrate 101. [ ) Are electrically connected.

In order to prevent an electrical short between the emitter layer 102 on the front surface of the substrate 101 and the p + region on the back surface of the substrate 101 and a short circuit between the n electrode 105 and the p electrode 106, Are provided with isolation trenches 107 on the front and rear surfaces, respectively.

The n-electrode 105 and the p-electrode 106 are formed by firing the conductive paste at a high temperature of about 1000 ° C. after the application of the conductive paste. However, the substrate is physically deformed due to firing at a high temperature. The p-electrode 105 is formed of aluminum (Al) and is fired to form a back electric field (BSF, p ++). The back electric field (BSF) basically serves to improve the carrier collection rate, It is disadvantageous in that it has a lot of defects in itself and acts as a recombination factor to lower the passivation characteristics.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a MWT solar cell capable of improving the photoelectric conversion efficiency of a solar cell by minimizing the recombination rate of carriers by applying an amorphous silicon thin film excellent in passivation characteristics, The purpose of the method is to provide.

According to an aspect of the present invention, there is provided an MWT solar cell including: a first conductive type crystalline silicon substrate having a via hole; a via electrode provided in the via hole; And an amorphous semiconductor layer, a transparent conductive oxide film provided on the amorphous semiconductor layer, a p-electrode provided on the transparent conductive oxide film, and an n-electrode electrically connected to the via-electrode.

An antireflection film and a grid line are provided on the front surface of the substrate, and the grid line is connected to the via electrode.

A method of manufacturing an MWT solar cell according to the present invention includes the steps of preparing a p-type silicon substrate provided with a via hole, performing a diffusion process to form an emitter layer on the entire surface of the substrate, Forming an n-electrode, a p-electrode, a via-electrode, and a grid line by sequentially laminating an amorphous semiconductor layer and a transparent conductive oxide layer.

The forming of the n-electrode, the p-electrode, the via-electrode, and the grid line may be performed by applying a conductive paste to a portion where an n-electrode is to be formed, a portion where a p-electrode is to be formed and a via- Forming an n-electrode, a p-electrode and a via electrode, selectively removing the antireflection film at a portion where the grid line is to be formed, applying a conductive paste, and curing at a low temperature of 50 to 300 캜 to form a grid line .

The MWT type solar cell according to the present invention has the following effects.

As the amorphous silicon thin film is provided on the rear surface of the substrate, the recombination rate of the carrier can be lowered, thereby improving the photoelectric conversion efficiency of the solar cell. Further, deformation of the substrate can be minimized by forming the electrode through low-temperature firing.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of a conventional MWT type solar cell. FIG.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an MWT type solar cell.
3 is a flowchart illustrating a method of manufacturing an MWT solar cell according to an embodiment of the present invention.
4A to 4F are cross-sectional views illustrating a method of manufacturing a MWT solar cell according to an embodiment of the present invention.

Hereinafter, an MWT solar cell and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the drawings.

2, a MWT solar cell according to an embodiment of the present invention includes a first conductive type crystalline silicon substrate 301, and a substrate 301 And a via electrode 311 is formed in the via hole 302. The via hole 302 is formed in the via hole 302. [ An anti-reflection film 305 and a grid line 312 are provided on the substrate 301. Here, the first conductivity type is p-type or n-type, the second conductivity type described below is the opposite of the first conductivity type, and in the following description, the first conductivity type is p-type.

The via electrode 311 is connected to the second conductive type electrode, that is, the n-electrode 310, on the rear surface of the substrate 301. In addition, an intrinsic layer 306, an amorphous semiconductor layer 307 (a-Si: H), and a transparent conductive oxide layer 308 are sequentially stacked on the rear surface of the substrate 301. Like the amorphous semiconductor layer 307, the intrinsic layer 306 is formed of an amorphous silicon thin film, and the amorphous semiconductor layer 307 is doped with p-type impurity ions. The intrinsic layer 306 and the amorphous semiconductor layer 307 serve to lower the recombination rate of carriers and the transparent conductive oxide layer 308 serves to compensate the low electric conductivity of the amorphous semiconductor layer 307 . On the other hand, a p-electrode 309 is provided on the transparent conductive oxide film 308.

Next, a method of manufacturing an MWT type solar cell according to an embodiment of the present invention will be described.

As shown in FIGS. 3 and 4A, a first conductive type crystalline silicon substrate 301 is prepared, and via holes 302 vertically penetrating the substrate 301 are formed at regular intervals (S301). Then, a texturing process is performed so that the irregularities 303 are formed on the surface of the silicon substrate 301 of the first conductivity type (S302). The texturing process is performed to reduce light reflection on the surface of the substrate 301, and may be performed using a wet etching method or a dry etching method such as reactive ion etching.

In the state where the texturing process is completed, a diffusion process is performed as shown in FIG. 4B to form an emitter layer 304 (n +) (S303). Specifically, a silicon substrate 301 is provided in a chamber, and a gas (for example, POCl ₃ ) containing second conductivity type impurity ions, that is, n-type impurity ions is supplied into the chamber, To be diffused into the substrate 301. An emitter layer 304 is formed at a predetermined depth along the periphery of the substrate 301 and an emitter layer 304 is formed in the substrate 301 around the via hole 302 as well.

The diffusion process of the n-type impurity ions may be performed by using a solution containing the n-type impurity ions, for example, a solution of the silicon substrate 301 in a phosphoric acid (H ₃ PO ₄ ) solution, (P) ions may be diffused into the substrate 301 through a subsequent heat treatment to form the emitter layer 304. [0064] In addition, an emitter layer may be selectively formed only on the entire surface of the substrate by using a doping paste, an ion implantation, or the like, and the emitter layer may have a selective emitter structure. When the second conductive impurity ions are p-type, the impurity ions forming the emitter layer 304 may be boron (B).

4C, a predetermined thickness of the lower portion of the substrate 301 is etched and removed to expose the substrate 301 in a state in which the emitter layer 304 is formed at a predetermined depth on the entire surface of the substrate 301, The emitter layer 304 on the back surface is removed (S304). Then, an anti-reflection film 305 is formed on the entire surface of the substrate 301 using a material such as a silicon nitride film (SiN _x ) (S305).

The intrinsic layer 306 and the amorphous semiconductor layer (a-Si: H) 307 are sequentially stacked as shown in FIG. 4D in the state where the antireflection film 305 is formed (S306). Like the amorphous semiconductor layer 307, the intrinsic layer 306 is formed of an amorphous silicon thin film, and the amorphous semiconductor layer 307 is doped with p-type impurity ions. The intrinsic layer 306 and the amorphous semiconductor layer 307 serve to lower the recombination rate of carriers. At this time, when the substrate is n-type, the amorphous semiconductor layer 307 is doped with n-type impurity ions.

Next, a transparent conductive oxide layer 308 is deposited on the amorphous semiconductor layer 307. The transparent conductive oxide layer 308 serves to compensate the low electrical conductivity of the amorphous semiconductor layer 307 and is formed of ZnO, ITO, GZO, IGZO (Indium Gallium Zinc Oxide) ), IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide), and In2O3. At the same time, isolation trenches 313 are formed on the front and rear surfaces of the substrate 301 through laser irradiation or the like.

In this state, silver paste is applied to the portion where the n-electrode 310 is to be formed through a screen printing method or the like. At this time, the screen printing proceeds in the back surface direction of the substrate 301, thereby filling the via hole 302 with silver paste. Next, an aluminum paste is applied to a portion where the p-electrode 309 is to be formed on the rear surface of the substrate 301, and then cured at a low temperature of 50 to 300 ° C to form an n-electrode 310, a p- The via electrode 311 is completed (S307) (see Fig. 4E).

After the n-electrode 310 and the p-electrode 309 are formed, the antireflection film 305 at the portion where the grid line 312 is to be formed is selectively removed, silver paste is applied, Curing to form a grid line 312 (S308), a manufacturing method of a MWT type solar cell according to an embodiment of the present invention is completed (see FIG. 4F).

Meanwhile, the n-electrode 310 and the p-electrode may be formed through a plating process. In this case, each of the n-electrode 310 and the p-electrode may have a structure in which a first plating layer, a silicide layer, and a second plating layer are sequentially stacked. As the plating method, an electroless plating method or an electrolytic plating method Electro-plating may be used.

301: a crystalline silicon substrate of the first conductivity type
302: via hole 303: concave / convex
304: Emitter layer 305: Antireflection film
306: intrinsic layer 307: amorphous semiconductor layer
308: transparent conductive oxide film 309: p electrode
310: n electrode 311: via electrode
312: Grid line 313: Trench for isolation

Claims (5)

A p-type crystalline silicon substrate provided with a via hole;
A via electrode provided in the via hole;
An intrinsic layer and an amorphous semiconductor layer which are sequentially stacked on the rear surface of the substrate;
A transparent conductive oxide film provided on the amorphous semiconductor layer;
A p-electrode provided on the transparent conductive oxide film; And
And an n-electrode electrically connected to the via electrode,
An antireflection film and a grid line are provided on the front surface of the substrate, the grid line is connected to the via electrode,
An n-type emitter layer is formed on the entire surface of the substrate except the rear surface of the substrate to a predetermined depth,
Wherein the intrinsic layer and the amorphous semiconductor layer are formed of an amorphous silicon thin film,
The amorphous semiconductor layer is doped with p-type impurity ions,
Wherein the substrate, the intrinsic layer, and the amorphous semiconductor layer have a pic structure in a semiconductor conduction type regardless of the substrate position.
delete Preparing a p-type silicon substrate provided with a via hole;
Forming an emitter layer on the entire surface of the substrate by performing a diffusion process;
Removing the emitter layer formed on the back surface of the substrate;
Sequentially stacking an intrinsic layer, an amorphous semiconductor layer, and a transparent conductive oxide layer on the rear surface of the substrate; And
forming an n-electrode, a p-electrode, a via-electrode, and a grid line,
The forming of the n-electrode, the p-electrode, the via electrode, and the grid line may include:
forming an n-electrode, a p-electrode, and a via electrode by applying a conductive paste to a portion where the n-electrode is to be formed, a portion where the p-electrode is to be formed, and a via hole and then curing at a low temperature of 50 to 300 [
Forming a grid line by selectively removing an antireflection film at a portion where a grid line is to be formed, applying a conductive paste, and curing at a low temperature of 50 to 300 DEG C,
Wherein the intrinsic layer and the amorphous semiconductor layer are formed of an amorphous silicon thin film,
The amorphous semiconductor layer is doped with p-type impurity ions,
Wherein the substrate, the intrinsic layer, and the amorphous semiconductor layer have a pic structure in a semiconductor conduction type regardless of substrate positions.
delete The liquid crystal display according to claim 3, wherein each of the n-electrode and the p-
Forming a first plating layer;
Forming a silicide layer on the first plating layer;
And forming a second plating layer on the silicide layer,
Wherein the first plating layer and the second plating layer are formed through an electroless plating or an electroplating method.

Images