KR101558880B1 - A relaxation oscillator - Google Patents

Abstract

A relaxation oscillator is provided. The relaxation oscillator includes: a clock adjusting unit that receives a first set value from the outside and generates a first clock having a first frequency based on a first set value; an AOT (Adaptive On) unit that converts a first clock to a second clock A current cell for receiving a second set value different from the first set value from the outside and generating a first current whose amount of current is controlled by a second set value, A capacitor array that is provided with a second clock and a first current based on the first set value, a capacitor array that compares the first voltage supplied from the capacitor array with a second voltage provided from the reference voltage / And a third clock having a first duty ratio, wherein the second clock determines the charging time of the capacitor array.

Description

[0001] A RELAXATION OSCILLATOR [0002]

The present invention relates to a relaxation oscillator, and more particularly, to a relaxation oscillator capable of changing a duty ratio of a clock frequency and a clock frequency.

Generally, an oscillator is used as a signal generating circuit in the field of electronic circuits. That is, the oscillator generates a stable and periodically varying signal with respect to a change in time, and the generated signal is used as a clock signal for timing control of the system, or a carrier signal (modulation Signal).

Such an oscillator can be divided into a tuned oscillator and a relaxation oscillator called a charge / discharge oscillator according to the implementation method.

In particular, the relaxation oscillator generates an oscillation signal by charging / discharging a capacitor located between a threshold voltage determined internally in the circuit. That is, after charging the capacitor, the relaxation oscillator discharges the capacitor when the voltage across the capacitor reaches a certain threshold voltage level, thereby outputting the oscillation frequency at which the cycle is determined according to the charging / discharging time.

Korean Registered Patent No. 10-0938292 (Publication Date: June 05, 2004)

A problem to be solved by the present invention is to provide a relaxation oscillator capable of changing a clock frequency and a duty ratio of a clock by user setting.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a relaxation oscillator including a clock adjusting unit that receives a first set value from the outside and generates a first clock having a first frequency based on a first set value, An adaptive on time (AOT) circuit for converting a clock into a second clock, a second current value control circuit for receiving a second set value different from the first set value from the outside and generating a first current whose amount of current is controlled by the second set value, A capacitor array that receives a first set value from the outside and is charged by a second clock and a first current based on a first set value, And a comparator for generating a third clock having a first duty ratio as compared to a second voltage provided from the voltage / current generator, wherein the second clock determines the charging time of the capacitor array.

The first and second set values may be selected from a user.

The clock controller may include a clock generator for generating a first clock and a divider for adjusting a first clock provided from the clock generator to have a first frequency.

The first clock having the first frequency may have a duty ratio of 50%.

The second clock includes a fifth clock that inverts the fourth clock and the fourth clock, and the charge time of the capacitor array may be determined by the fifth clock.

The capacitor array is connected to the AOT circuit and is provided with a fourth clock, and the current cell can adjust the amount of the first current using the second current supplied from the reference voltage / current generator based on the second set value.

Wherein the switch is provided with a first current supplied from a current cell based on any one of the fourth clock and the fifth clock provided by the capacitor array Or not.

When the switch is provided with a fifth clock and the fifth clock provided is at a high level, the first current may pass through the switch and the capacitor array may be charged by the passed first current.

When the switch is provided with the fourth clock and the provided fourth clock is at the low level, the first current is cut off by the switch, and the capacitor array can be discharged.

The first voltage may include a triangular wave.

The first duty ratio of the third clock is determined by the slope of the first voltage combined with the second voltage, and the first set value may determine the number of capacitors to be charged by the first one of the capacitor arrays.

The slope of the first voltage is determined by a combination of the amount of current of the first current, the charging time of the capacitor array determined by the fifth clock, and the number of capacitors, and the number of capacitors can determine the total capacitor capacity of the capacitor array.

The high-level width of the fifth clock may be wider than the width of the low-level.

Other specific details of the invention are included in the detailed description and drawings.

The present invention controls the slope of the output voltage of the capacitor array by adjusting the capacitance, charging time, and current amount of the capacitor so that the duty ratio of the final clock can be determined. In addition, since the duty ratio of the clock can be controlled by the user in accordance with the application system, a wide application range can be provided.

1 is a block diagram illustrating a relaxation oscillator according to an embodiment of the present invention.
2 is a partial circuit diagram for explaining the current cell and the capacitor array of FIG.
3 is a flowchart illustrating an operation method of the relaxation oscillator of FIG.
4 is a block diagram illustrating a method of operating the relaxation oscillator of FIG.
5 and 6 are diagrams for explaining the operation of the AOT circuit of FIG.
FIG. 7 is a graph illustrating the duty ratio change of the third clock according to the slope of the first voltage in FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "with another element when it is directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, a relaxation oscillator according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

1 is a block diagram illustrating a relaxation oscillator according to an embodiment of the present invention. 2 is a partial circuit diagram for explaining the current cell and the capacitor array of FIG.

1 and 2, a relaxation oscillator 1 according to an embodiment of the present invention includes a clock regulator 10, an AOT circuit 20, a capacitor array 30, a reference voltage / current generator 40, A current cell 50, and a comparator 70, as shown in FIG.

The clock regulator 10 may include, for example, a clock generator 10a and a divider 10b. The clock controller 10 receives a first set value SEL [N: 0] from the outside and generates a first clock signal having a first frequency based on the first set value SEL [N: 0] CLK1 < / RTI > In the present invention, the outside may include a user, but the present invention is not limited thereto.

Specifically, the clock generator 10a receives the first set value SEL [N: 0] from the outside and can generate the first clock CLK1. Here, the first set value SEL [N: 0] may include information about the number of capacitors selected by the user of the capacitor array 30 and information about the first frequency, and the number of selected capacitors The total capacitor capacity (C total) can be set.

The clock generator 10a may also provide the first clock CLK to the divider 10b with information on the first frequency provided via the first set value SEL [N: 0]. Here, the first frequency may eventually be a key factor in determining the charging time (t charging) of the capacitor array 30.

The divider 10b may be connected to, for example, the clock generator 10a.

Specifically, the divider 10b can adjust the first clock CLK1 provided from the clock generator 10a to a clock having the first frequency. Here, the first frequency corresponds to the charging time t charging of the capacitor array 30, which will be described later, and may be a factor necessary for varying the duty ratio of the third clock CLK3. That is, the divider 10b can adjust the first clock CLK1 to have the first frequency based on the information about the first frequency provided from the clock generator 10a.

Also, the divider 10b may provide the first clock CLK1, which is set to have the first frequency, to the adaptive on time (AOT) circuit 20. In this case, the first clock CLK1 may have a first duty ratio D1 and the first duty ratio D1 may include a 50% duty ratio, but the present invention is not limited thereto.

The AOT circuit 20 can be connected to the divider 10b.

Specifically, the AOT circuit 20 is connected to the divider 10b and can convert the first clock CLK1 provided from the divider 10b into the second clock CLK2.

The second clock CLK2 converted in the AOT circuit 20 may be directly supplied to the switch 60 or inverted to be supplied to the second clock bar / CLK2. The second clock CLK2 is provided to the capacitor array 30 in the AOT circuit 20. A detailed description of the operation of the AOT circuit 20 will be given later.

The capacitor array 30 can be supplied with the second clock CLK2 from the AOT circuit 20. [

Specifically, the number of capacitors to be charged in the capacitor array 30 can be determined by the first set value SEL [N: 0] received from the outside, and the first set value SEL [N: 0] The capacitor C1 of the capacitor C1 of the determined capacitor array 30 can be charged by the first current I1 supplied from the current cell 50. [ That is, the number of capacitors selected by the first set value SEL [N: 0] represents the total capacitor capacitance C total, and the charging time t charging of each of the selected capacitors is the second clock Can be determined by the bar (/ CLK2). The charging of the capacitor array 30 will be described later in detail.

The capacitor array 30 may also output the first voltage V1.

Here, the first voltage V1 is a capacitor determined by the charging time t charging of the capacitor array 30 determined by the second clock bar / CLK2 and the first set value SEL [N: 0] (The total capacitor capacitance C total) and the amount of current of the first current I1 provided from the current cell 50 can be determined.

The reference voltage / current generator 40 may provide the second current I2 to the current cell 50 and provide the second voltage V2 to the comparator 70.

Specifically, the reference voltage / current generator 40 may provide a second current I2 to the current cell 50 to assist the current cell 50 to set the amount of current of the first current I1 . The reference voltage / current generator 40 may also provide a second voltage V2 to the comparator 70 to assist the comparator 70 to output the third clock CLK3.

The current cell 50 may generate and provide a first current I1 to the capacitor array 30. [

Specifically, the current cell 50 receives the second current I2 from the reference voltage / current generator (V / I generator) 40 and receives the second set value SW [N: 0] The amount of current of the first current I1 can be set using the second current I2. That is, for example, if the second set value SW [N: 0] selects two NMOSs, the second current I2 flows only to the selected two NMOSs, and the first current I1 is 2 * And may have an amount of current corresponding to the second current I2.

The current cell 50 may also provide the switch 60 with a first current I1 whose amount of current is set before providing it to the capacitor array 30.

The switch 60 may be connected to the AOT circuit 20, the capacitor array 30, and the current cell 50.

Specifically, the switch 60 is supplied with the second clock CLK2 from the AOT circuit 20 and can receive the first current I1 from the current cell 50. [ The switch 60 may also determine whether to provide the first current I1 provided from the current cell 50 to the capacitor array 30 based on the second clock CLK2 provided from the AOT circuit 20 have. More specifically, the switch 60 is supplied with the second clock CLK2 from the AOT circuit 20 and, when the second clock CLK2 supplied thereto is input at a low level, The movement of the current I1 is blocked, and the capacitor array 30 is discharged. When the second clock CLK2 supplied from the AOT circuit 20 is inverted by the inverter and the inverted second clock, that is, the second clock bar / CLK2 is input to the high level, The charging of the capacitor array 30 can be progressed by passing the charging current I1. Here, it can be said that the second clock bar / CLK2 determines the charging time of the capacitor array 30 because the capacitor array 30 is charged during the high level of the second clock bar / CLK2.

The comparator 70 may be provided with a first voltage V1 and a second voltage V2, for example.

Specifically, the first voltage V1 supplied from the capacitor array 30 may be the sum of the charging time t charging of the capacitor array 30 determined by the second clock bar / CLK2, (Total capacitance C total) determined by the value SEL [N: 0] and the amount of current of the first current I1 provided from the current cell 50. [ Here, the slope of the first voltage V1 can be defined by the following equation.

 <Slope of first voltage>

The slope of the first voltage V1 =

That is, the slope of the first voltage V1 is adjusted by adjusting the amount of current of the first current I1 after determining the charging time t charging and the total capacitor capacitance C total of the capacitor array 30 . The first voltage V1 whose slope is adjusted in this manner may include, for example, a triangle wave, but is not limited thereto.

The second voltage V2 provided from the reference voltage / current generator 40 may include, for example, a fourth clock CLK4 having a second duty ratio D2.

Specifically, since the second duty ratio D2 of the second voltage V2 is constant, the slope of the first voltage V1 coupled with the second voltage V2 causes the third voltage V2 of the third The duty ratio D3 can be determined. That is, the comparator 70 compares / combines the first voltage V1 supplied from the capacitor array 30 and the second voltage V2 supplied from the reference voltage / current generator 40 to generate a third clock CLK3 And the third duty ratio D3 of the third clock CLK3 may be determined by the slope of the first voltage V1 combined with the second voltage V2. More specifically, when the charging time t charging of the capacitor array 30 and the total capacitor capacitance C total are determined, by increasing or decreasing the amount of current of the first current I1, The ratio D3 can be increased or decreased.

The relaxation oscillator 1 according to an embodiment of the present invention controls the slope of the first voltage V1 output from the capacitor array 30 by adjusting the capacitance, charging time, and current amount of the capacitor, So that the third duty ratio D3 of the clock CLK3 can be determined. In addition, since the duty ratio of the clock can be controlled by the user in accordance with the application system, a wide application range can be provided.

Hereinafter, a method of operating the relaxation oscillator according to an embodiment of the present invention will be described with reference to FIGS. 3 to 7. FIG.

3 is a flowchart illustrating an operation method of the relaxation oscillator of FIG. 4 is a block diagram illustrating a method of operating the relaxation oscillator of FIG. 5 and 6 are diagrams for explaining the operation of the AOT circuit of FIG. FIG. 7 is a graph illustrating the duty ratio change of the third clock according to the slope of the first voltage in FIG.

Referring to FIGS. 3 and 4, a first set value SEL [N: 0] and a second set value SW [N: 0] are provided (S200).

Specifically, the first set value SEL [N: 0] and the second set value SW [N: 0] can be supplied from the outside. Herein, the outside may include, but is not limited to, a user.

The first frequency and the number of capacitors to be charged are determined (S210).

Specifically, the first frequency and the number of capacitors to be charged can be determined by the first set value SEL [N: 0]. That is, the first set value SEL [N: 0] may include information on the first frequency required by the relaxation oscillator 1 and information on the number of capacitors to be charged, Information may be provided to the clock generator 10a and information on the number of capacitors to be charged may be provided to the capacitor array 30. [ Also, the number of capacitors to be charged in the capacitor array 30 can be determined based on the information on the number of capacitors to be charged.

The amount of current of the first current I1 is determined (S212).

Specifically, the second set value SW [N: 0] is provided to the current cell 50 to determine the amount of current of the first current I1. That is, the current cell 50 is supplied with the second current I2 from the reference voltage / current generator (V / I generator) 40 and receives the second set value SW [N: 0] The amount of current of the first current I1 can be set using the second current I2. That is, for example, if the second set value SW [N: 0] selects two NMOSs, the second current I2 flows only to the selected two NMOSs, and the first current I1 is 2 * And may have an amount of current corresponding to the second current I2.

And provides a first clock CLK1 having a first frequency (S220).

Specifically, the clock generator 10a receives the first set value SEL [N: 0] from the outside and can generate the first clock CLK1. The clock generator 10a may also provide the first clock CLK to the divider 10b with information on the first frequency provided via the first set value SEL [N: 0].

The divider 10b can adjust the first clock CLK1 provided from the clock generator 10a to a clock having the first frequency. That is, the divider 10b can adjust the first clock CLK1 to have the first frequency based on the information about the first frequency provided from the clock generator 10a. The divider 10b may also provide the AOT circuit 20 with a first clock CLK1 having a first frequency.

And converts the first clock CLK1 into the second clock CLK2 (S230).

Specifically, the AOT circuit 20 is connected to the divider 10b and can convert the first clock CLK1 provided from the divider 10b into the second clock CLK2.

Referring to FIGS. 5 and 6, it can be seen that the AOT circuit 20 receives the first clock CLK1 from the divider 10b.

Specifically, the first clock CLK1 can be inverted by the inverter before reaching Vx.

When the inverted first clock CLK1 is input to the NMOS in a low level state, the NMOS is turned off and the AOT current IOT is supplied to the AOT capacitor C AOT connected to Vx. . Therefore, the voltage measured at Vx increases gradually at first, but remains constant after a certain time. This is because when the AOT capacitor C AOT is charged by the AOT current I AOT, the voltage measured at V x increases and then a constant value is maintained after the end of charging of the AOT capacitor C AOT.

On the other hand, when the inverted first clock CLK1 is input to the NMOS in a high level state, the NMOS is turned on and the AOT current IAO is supplied to the ground through the NMOS, ground (i.e., grounded). Therefore, the voltage measured at Vx is kept at 0 when the inverted first clock CLK1 is in a high level state.

The first clock CLK1 passed through Vx passes through an NMOS and an inverter. Here, the inverter serves as a buffer. Therefore, the increase region of Vx shown in FIG. (low level). As described above, it can be seen that the duty ratio of the first clock CLK1 at the delay point is reduced as compared with the initial state by recognizing the increase region according to the time of Vx as a low level.

The first clock CLK1 whose duty ratio is decreased and the inverted first clock CLK1 are combined in the AND block and the result of the combination of the first clock CLK1 and the second clock bar / CLK2 may be generated. Further, the second clock bar (/ CLK2) can be output to the second clock (CLK2) by passing through an inverter.

Here, the high level width of the second clock CLK2 may be narrower than the low level width. That is, the width of the high level is narrower than the width of the low level, which means that the duty ratio is low. In the case of the second clock CLK2, the switch 60 is input to the switch 60 to discharge the capacitor array 30, and in the case of the second clock bar / CLK2, So that the capacitor array 30 is charged. A detailed description thereof will be given later.

Referring again to FIGS. 3 and 4, a second clock CLK2 is provided (240).

Specifically, when the second clock CLK2 output from the AOT circuit 20 is provided to the switch 60 at a low level, the switch 60 is turned off and the first current I1 is turned off And can be cut off by the switch 60. Also, since the first current I1 is cut off by the switch 60, the capacitor array 30 can be discharged (S252).

The second clock CLK2 outputted from the AOT circuit 20 is inverted by the inverter and supplied to the switch 60 in the second clock bar / CLK2 state, and the second clock bar / CLK2 is input to the high level, the switch 60 is turned on and the first current I1 can pass through the switch 60. [ The first current I1 that has passed through the switch 60 is also provided to the capacitor array 30 in step S242 and the capacitor selected by the first set value SEL [N: 0] of the capacitor array 30 (S250).

The second clock bar / CLK2 is provided to the switch 60 and the second clock CLK2 is provided to the capacitor array 30 and is supplied to the capacitor array 30 when the capacitor array 30 is charged. , The NMOS connected to both ends of each of the capacitors C1 to CN can be zero. Thus, since the NMOS becomes zero, the first current I1 provided from the current cell 50 can charge the capacitor selected by the first set value SEL [N: 0]. Since the capacitors to be charged at this time are charged for a time corresponding to the high level of the second clock bar / CLK2 (i.e., the low level of the second clock CLK2), the second clock bar / It can be seen that the charging time of the array 30 is determined.

The first voltage V1 and the second voltage V2 are provided (S260).

Specifically, the first voltage V1 output from the capacitor array 30 may be provided to the comparator 70 together with the second voltage V2 output from the reference voltage / current generator 40.

That is, the first voltage V1 may be output from the capacitor array 30 charged by the first current I1, and the output first voltage V1 may include a triangular wave. However, the present invention is not limited thereto. The slope of the first voltage V1 is determined by the charging time t charging of the capacitor array 30 determined by the second clock bar / CLK2 and the first set value SEL [N: 0] (Total capacitance C total) of the first current I1 supplied from the current cell 50 and the number of capacitors (total capacitance C total)

In case of the second voltage V2, it may include the fourth clock CLK4 having the second duty ratio D2, and the second duty ratio D2 may be kept constant.

And generates a third clock CLK3 (270).

Referring to FIG. 7, the comparator 70 may compare and combine the provided first voltage V1 with the second voltage V2 to generate the third clock CLK3.

Specifically, the comparator 70 compares / combines the first voltage V1 supplied from the capacitor array 30 and the second voltage V2 supplied from the reference voltage / current generator 40 to generate a third clock CLK3 and the third duty ratio D3 of the third clock CLK3 may be determined by the slope of the first voltage V1 combined with the second voltage V2. That is, when the slope of the first voltage V1 increases, the third duty ratio D3 also increases, and when the slope of the first voltage V1 decreases, the third duty ratio D3 also decreases .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10a: clock generator 10b: divider
20: Adaptive on time (AOT) circuit 30: Capacitor array
40: reference voltage / current generator 50: current cell
60: Switch 70: Comparator

Claims (13)

A clock regulator receiving a first set value from an external source and generating a first clock having a first frequency based on the first set value;
An AOT circuit for converting the first clock to a second clock;
A current cell for receiving a second set value different from the first set value from the outside and generating a first current whose amount of current is controlled by the second set value;
A capacitor array that receives the first set value from the outside and is charged by the second clock and the first current based on the first set value;
And a comparator for comparing a first voltage provided from the capacitor array with a second voltage provided from a reference voltage / current generator to generate a third clock having a first duty ratio,
The second clock determines the charging time of the capacitor array,
The second voltage comprises a fourth clock,
Wherein the capacitor array is connected to the AOT circuit to receive the fourth clock,
Wherein the current cell adjusts the amount of current of the first current using a second current provided from the reference voltage / current generator based on the second set value. The method according to claim 1,
Wherein the first and second set values are selected from a user. The method according to claim 1,
Wherein the clock controller comprises: a clock generator for generating a first clock;
And a divider for adjusting the first clock provided from the clock generator to have the first frequency. The method according to claim 1,
Wherein the first clock having the first frequency has a duty ratio of 50%. The method according to claim 1,
Wherein the second voltage further comprises a fifth clock that inverts the fourth clock, and the charge time of the capacitor array is determined by the fifth clock. delete 6. The method of claim 5,
Further comprising a switch for receiving either the fourth clock or the fifth clock,
Wherein the switch determines whether to provide the first current provided from the current cell to the capacitor array based on either the provided fourth clock or the fifth clock. 8. The method of claim 7,
The first current being passed through the switch and the capacitor array being charged by the passed first current when the switch is provided with the fifth clock and the fifth clock provided is at a high level, . 8. The method of claim 7,
Wherein when the switch is provided with the fourth clock and the provided fourth clock is at a low level, the first current is blocked by the switch, and the capacitor array is discharged. 6. The method of claim 5,
Wherein the first voltage comprises a triangular wave. 11. The method of claim 10,
Wherein the first duty ratio of the third clock is determined by the slope of the first voltage combined with the second voltage,
Wherein the first set value determines the number of capacitors to be charged by the first current in the capacitor array. 12. The method of claim 11,
Wherein the slope of the first voltage is determined by a combination of the amount of current of the first current, the charging time of the capacitor array determined by the fifth clock, and the number of the capacitors,
Wherein the number of capacitors determines the total capacitance of the capacitor array. 6. The method of claim 5,
Wherein a width of the high level of the fifth clock is greater than a width of the low level.

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