JP2008079274A - Frequency comparator, frequency synthesizer, and associated method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog frequency comparator which sets an internal frequency on the basis of a voltage and compares the internal frequency with an external frequency, to provide an analog frequency synthesizer which synthesizes a clock signal according to the same principles as the analog frequency comparator, and to provide an associated method. <P>SOLUTION: The frequency comparator includes a frequency detection circuit which generates a reference signal on the basis of a first signal and an input voltage; a frequency generator which generates a second signal on the basis of the input voltage; a charge pump circuit which is coupled to the frequency detection circuit and the frequency generator, enables a charging current on the basis of one of the reference signal and the second signal to increase a voltage level, and further enables a discharging current on the basis of the other of the reference signal and the second signal to decrease the voltage level; and a decision logic which is coupled to the charge pump circuit and indicates a frequency relationship between the first signal and the second signal on the basis of the voltage level. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to clock signal processing, and more particularly to an analog frequency comparator that sets an internal frequency based on voltage and compares it with an external frequency, an analog frequency synthesizer that synthesizes a clock signal, and related methods.

  In an application field of an integrated circuit (IC), it is common to provide an external pin for receiving an external clock signal having a frequency different from that of an internally generated clock signal. Such an integrated circuit needs to have a function of determining the level of both frequencies and selecting a clock signal having a required frequency based on the determination result. According to the prior art, it is the combination of a phase frequency detector (PFD), a counter, and a plurality of digital logic that selects the frequency required for internal operation. However, the combination of a PFD, a counter, and a plurality of digital logic requires a large chip area, resulting in high cost.

  Please refer to FIG. FIG. 1 is an explanatory diagram showing a conventional frequency comparator 10. The conventional frequency comparator 10 includes a frequency detection circuit 11, a first counting circuit 12, a second counting circuit 13, and a decision logic 14. If the first clock signal IN1 and the second clock signal IN2 are simultaneously input to the frequency detection circuit 11, the first reset signal RST1 and the second reset signal RST2 corresponding to the first clock signal IN1 and the second clock signal IN2, respectively, It is transmitted to the first counting circuit 12 and the second counting circuit 13. Both reset signals RST1 and RST2 reset the first counting circuit 12 and the second counting circuit 13, respectively, and start counting the clock periods of the first clock signal IN1 and the second clock signal IN2. If the frequency of the first clock signal IN1 is higher than that of the second clock signal IN2, the overflow signal OF1 and the overflow signal OF2 are sequentially output and input to the decision logic 14. Accordingly, the decision logic 14 outputs a status signal indicating the frequency relationship between the first clock signal IN1 and the second clock signal IN2 based on both overflow signals OF1 and OF2. Otherwise, U.S. Pat. No. 6,834,093 lists another type of frequency comparator. For details, refer to the patent.

  After receiving the external frequency, the integrated circuit changes the external frequency to an arbitrary multiple and synthesizes the internal clock signal using this as the frequency of the internal clock signal, or uses the external frequency to generate a plurality of different phases. It is necessary to generate a clock signal. Therefore, a frequency synthesizer and a frequency multiplier are necessary.

  In order to solve the above-described problem, the present invention sets an internal frequency based on a voltage, compares the external frequency with an analog frequency comparator, and a frequency for synthesizing a clock signal using the principle of the analog frequency comparator. It is an object to provide a synthesizer and a related method.

  The present invention provides a frequency comparator that compares the frequencies of a first signal and a second signal. The frequency comparator includes a frequency detection circuit that generates a reference signal based on a first signal and an input voltage, a frequency generator that generates a second signal based on the input voltage, a frequency detection circuit, and a frequency generator. A combined charge pump that enables a charge current based on one of the reference signal and the second signal to increase the voltage level, and further enables a discharge current based on the other of the reference signal and the second signal to decrease the voltage level. And a decision logic coupled to the charge pump circuit and indicating a frequency relationship between the first signal and the second signal based on the voltage level.

  The present invention further provides a frequency synthesizer that generates a second signal based on the first signal. The frequency synthesizer includes a frequency detection circuit that generates a reference signal based on a first signal and a first input voltage, a frequency generator that generates a second signal based on a second input voltage, a frequency detection circuit, and a frequency Coupled to the generator to enable the charging current based on one of the reference signal and the second signal to increase the voltage level, and further to enable the discharge current based on the other of the reference signal and the second signal to The charge pump circuit is coupled to the charge pump circuit, the charge pump circuit, the frequency detection circuit, and the frequency generator, and adjusts the frequency detection circuit and the frequency generator based on the voltage level to adjust the frequency of the reference signal and the second signal. Adjustment circuit.

  The present invention further provides a frequency comparison method for comparing the frequencies of the first signal and the second signal. The method includes (a) generating a reference signal based on the first signal and the input voltage, (b) generating a second signal based on the input voltage, and (c) generating one of the reference signal and the second signal. Enabling the charging current to increase the voltage level, further enabling the discharging current based on the other of the reference signal and the second signal to decrease the voltage level, and (d) the first signal based on the voltage level The method includes steps indicating a frequency relationship between the second signals.

  The present invention further provides a frequency synthesis method for generating a second signal based on the first signal. The method includes (e) generating a reference signal based on the first signal and the first input voltage, (f) generating a second signal based on the second input voltage, and (g) the reference signal and the second signal. Enable the charging current based on one of the two to increase the voltage level, and further enable the discharging current based on the other of the reference signal and the second signal to decrease the voltage level, and (h) reference based on the voltage level And adjusting the frequency of the signal and the second signal.

  The present invention utilizes an analog frequency comparator and a frequency synthesizer instead of digital logic. Such a configuration has good integration with an analog circuit and eliminates the need for a plurality of digital logics and counters, and thus has the effect of reducing the required chip area and reducing costs.

  In order to elaborate on the features of such an apparatus and method, specific examples are given and described below with reference to the figures.

  As is well known to those skilled in the art, consumer electronic device manufacturers can refer to the same elements in terms different from those described in the specification and claims. Therefore, the present invention specifies an element exclusively by function, not by name. It should be understood that terms such as “including” and “having” used in the present specification and claims should not be construed restrictively, and are not limited to those exemplified. “Coupled” means direct electrical connection or indirect electrical connection. Thus, “the first device is coupled to the second device” means that both devices are directly connected to each other or to each other via other devices or connections.

Please refer to FIG. FIG. 2 is an explanatory diagram showing the frequency comparator 100 according to the present invention. The frequency comparator 100 is a device that compares the frequencies of the first signal S ₁ (ie, the external clock signal) and the second signal S ₂ (ie, the internal clock signal), and includes a frequency detection circuit 101, a frequency generator 102, It includes a pump circuit 103, decision logic 104 and a bias voltage generator 105. Frequency detection circuit 101 generates a reference signal _{S r} on the basis of the first signals _{S 1} and the input voltage _{V rosc,} frequency generator 102 generates a second signal _{S 2} based on the input voltage _{V rosc.} The charge pump circuit 103 coupled to the frequency detection circuit 101 and the frequency generator 102 enables the charging current I _c based on one of the reference signal S _r and the second signal S ₂ to increase the voltage level V _oset , and reference signal _{S r} and based on the other of the second signal _{S 2} to enable the discharge current _{I dc} lowering the voltage level _{V oset} with. Decision logic 104 coupled to the charge pump circuit 103 determines the frequency relationship between the first signal S ₁ and the second signal S ₂ based on the voltage level V _oset output from the charge pump circuit 103. A bias voltage generator 105 coupled to the frequency detection circuit 101 and the frequency generator 102 generates an input voltage V _rosc .

It should be noted, the charging operation of the present embodiment is controlled by the reference signal S _r, the discharge operation is controlled by the second signal S _2. However, this does not limit the present invention. For example, as another example, the charging operation is controlled by the second signal S _2, it is also possible to discharge operation is controlled by the reference signal S _r. The frequency relationship between the first signal S ₁ and the second signal S ₂ can be determined based on the voltage level V _oset .

The operation of the circuit element in the frequency comparator 100 will be described in detail below. In the embodiment shown in FIG. 2, the frequency detection circuit 101 is coupled to the first signals S _1, a first sawtooth generator 1011 which converts the first signals S ₁ to the first sawtooth wave signal S _w1, first coupled to the input voltage _{V rosc} a sawtooth signal _{S w1,} and a first comparator 1012 for generating a reference signal _{S r} by comparing the input voltage _{V rosc} a first sawtooth wave signal _{S w1.} The first sawtooth generator 1011, a single pulse generating circuit 1011a, a first capacitor _{C 1,} a first current source _{I 1,} a first switch _{W 1,} the second switch _{W 2,} switch control circuit 1011b Including. As shown in FIG. 2, the single pulse generating circuit 1011a is coupled to the first signals S ₁ generates one pulse signal for each period of the first signals S ₁ (i.e., S _p1). The first capacitor _{C 1} is coupled between the output node _{N 1} and the first reference voltage _{V ss} of the first sawtooth generator 1011 (i.e., ground voltage), a first current source _{I 1} and the second reference voltage _{V dd} ( Ie, the supply voltage). The first switch W ₁ coupled between the first current source I ₁ and the output node N ₁ of the first sawtooth generator 1011 switches the first current source I ₁ on the basis of the first switch control signal S _c1 . selectively coupled to one capacitance C _1, the output node N ₁ and the second switch W ₂ that is coupled between the first reference voltage V _ss of the first sawtooth generator 1011, the second switch control signal S _c2 selectively coupling the first capacitor C ₁ to the first reference voltage V _ss based on. The single pulse generating circuit 1011a, a first switch _{W 1,} and the switch control circuit 1011b is coupled to the second switch _{W 2} is the first switch control signal based on the output signal _{S p1} of the single pulse generating circuit 1011a _{S c1} And a second switch control signal _Sc2 .

Reference is again made to FIG. Frequency generator 102 is coupled to the second signal S _2, a second sawtooth generator 1021 which converts the second signal S ₂ to the second sawtooth wave signal S _w2, the second sawtooth wave signal S _w2 and the input voltage coupled to V _rosc, and a second comparator 1022 for generating a second signal _{S 2} by comparing the input voltage _{V rosc} a second sawtooth wave signal _{S w2.} Second sawtooth generator 1021 includes a second capacitor _{C 2,} a second current source _{I 2,} the third switch _{W 3,} a fourth switch _{W 4,} and a switch control circuit 1021a. Second capacitor C ₂ includes an output node N ₂ of the second sawtooth generator 1021 is coupled between the first reference voltage V _ss, the second current source I ₂ is coupled to the second reference voltage V _dd . Third switch W ₃ that is coupled between the output node N ₂ of the second current source I ₂ and the second sawtooth generator 1021, a second current source I ₂ No. based on the third switch control signal S _c3 selectively binds to double capacity C _2, the output node N ₂ and the fourth switch W ₄ that is coupled between the first reference voltage V _ss of the second sawtooth generator 1021, a fourth switch control signal S _c4 selectively coupling a second capacitor C ₂ to the first reference voltage V _ss based on. The switch control circuit 1021a coupled to the second signal S ₂ , the third switch W ₃ , and the fourth switch W ₄ receives the second signal S ₂ output from the output node N _{2 of} the second sawtooth wave generator 1021. Based on this, the third switch control signal S _c3 and the fourth switch control signal S _c4 are generated.

In addition, the decision logic 104 coupled to the voltage level V _oset and the third reference voltage V _r3 outputs an instruction signal V _id indicating the frequency relationship between the first signal S ₁ and the second signal S ₂ . Bias voltage generator 105 according to this embodiment includes a resistor _{R ref,} is coupled to resistor _{R ref,} based on the resistance value of the resistor _{R ref} and a reference voltage generating circuit 1051 to set the input voltage _{V rosc} . It should be noted that the reference voltage generation circuit 1051, the frequency detection circuit 101, the frequency generator 102, the charge pump circuit 103, and the decision logic 104 are all integrated on the same chip, and only the resistor R _ref is outside the chip. Is provided. In other words, the resistance value of the external resistor R is easy to adjust. In actual application, setting the input voltage V _rosc is completed immediately if the resistor R _ref is externally coupled to the reference voltage generation circuit 1051. The input voltage V _rosc determines the frequency f ₂ of the second signal S ₂ generated by the frequency generator 102, and the setting will be described in detail below.

Please refer to FIG. FIG. 3 is an explanatory diagram showing the bias voltage generator 105 shown in FIG. The fourth reference voltage V _r4 coupled to the resistor R _ref through the error amplifier 1052 and the pass transistor M ₁ connected as a closed loop generates a reference current I _ref (I _ref = V _r4 / R _ref ). The reference current I _ref is later mirrored by the current mirror 1053 and generated as a mirror current I _mirror . As is well known to those skilled in the art, the current mirror ratio N _mirror of the current mirror circuit 1053 can be set directly by PMOS transistors M ₂ , M ₃ or other possible means. Therefore, the input voltage V _rosc can be generated by _passing the mirror current I _mirror through the resistor R ₁ . It should be noted that the circuit configuration shown in FIG. 3 is only for explaining the present invention and does not limit the present invention.

The operation of the single pulse generating circuit 1011a, the first signal S ₁ is input, a single pulse generating circuit 1011a next to generate one pulse signal S _p1 for each cycle of the first signals S ₁ and outputs to the circuit, to stabilize the duty cycle of the first signal S _1. Please refer to FIG. FIG. 4 is an explanatory diagram showing the single pulse generation circuit 1011a shown in FIG. The single pulse generating circuit 1011a includes a plurality of inverters _Inv 1, Inv _2, a plurality of transistors _{M 4, M 5, M 6} , M 7, and the third transistor _{C 3,} a resistor _{R 2,} NAND gate NG Including. The first signal S ₁ is first delayed by a delay unit including the inverter Inv ₁ , the transistors M ₄ , M ₅ , M ₆ , M ₇ , the third transistor C ₃ , and the resistor R ₂ shown in FIG. S _delay is generated and input to the NAND gate NG. Thereafter, the NAND gate NG compares the delay signal S _delay with the first signal S ₁ and outputs a single pulse signal S _p1 as shown in FIG. FIG. 5 is a timing diagram of the delayed signal S _delay , the first signal S ₁ , the single pulse signal S _p1 , and the first sawtooth wave signal S _w1 shown in FIGS. 4 and 2. Since the operation of the delay unit is well known to those skilled in the art, the description thereof is omitted here. It should be noted that the circuit configuration shown in FIG. 4 is only for explaining the present invention and does not limit the present invention. In other words, all single pulse generation circuits that can generate the single pulse signal _Sp1 are suitable for the present invention.

Regarding the operation of the switch control circuit 1011b, the switch control circuit 1011b receives the single pulse signal S _p1 and converts it into a first switch control signal S _c1 and a second switch control signal S _c2 . Please refer to FIG. 5 and FIG. FIG. 6 is an explanatory diagram showing the first sawtooth wave generator 1011 shown in FIG. In simplified drawings shown in FIG. 6, the switch control circuit 1011b without performing any processing for a single pulse signal S _p1 input, functions simply as a transmission path. The first switch W ₁ and the second switch W ₂ are constituted by transistors M ₈ and M ₉ . However, the present invention is not limited thereto. When a single pulse signal S _p1 is a low level, to turn off the transistor M ₈ is turned on the transistor M _9, charging the output node N ₁ at a first current source I _1. When the impulse of a single pulse signal S _p1 appears on the transistor M ₉ off turn on the transistor M _8, to discharge the output node N ₁ to the ground voltage. Then, the first sawtooth wave signal _Sw1 as shown in FIG. 5 is obtained.

With respect to the operation of the first comparator 1012 shown in FIG. 2, the first comparator 1012 compares the first sawtooth signal S _w1 and the input voltage V _rosc to generate a reference signal S _r . In this embodiment, the input voltage _{V rosc} is coupled to the inverting terminal of the first comparator 1012 (i.e. N-), first sawtooth signal _{S w1} coupled to the non-inverting terminal of the first comparator 1012 (i.e. N +) Is done. If lower than the maximum voltage of the first sawtooth signal S _w1 is the input voltage V _rosc corresponding to the frequency of the first signal S _1, the reference signal S _r remains at a low voltage level. If the maximum voltage of the first sawtooth signal S _w1 corresponding to the frequency of the first signal S ₁ is exceeds the input voltage V _rosc, the reference signal S _r is a single with one pulse per cycle of the first signals S ₁ It is equivalent to a single pulse signal.

Reference is again made to FIG. To generate the clock signal, it is necessary feedback loop for feeding back the second signal S ₂ of the frequency generator 102 to the switch control circuit 1021a. After completion setting of the input voltage _{V rosc,} negative feedback characteristics of the frequency generator 102 induces a second signal _{S 2.} To explain the operation of the frequency generator 102 in more detail, the initial value of the second signal S ₂ is set to a low voltage level. Please refer to FIG. FIG. 7 is an explanatory diagram showing the second sawtooth wave generator 1021 shown in FIG. In simplified drawings shown in FIG. 7, the switch control circuit 1011a without performing any processing for the second signal S ₂ that is input, functions simply as a transmission path. The third switch W ₃ and the fourth switch W ₄ are constituted by transistors M ₁₁ and M ₁₀ . Accordingly, the second signal S ₂ is a transistor M ₁₀ to turn it off to turn on the transistor M _11, charges the second capacitor C ₂ by the second current source I ₂ via the output node N ₂ of the second capacitor C ₂ . Notably, similar inclination to the first sawtooth wave signal S _w1 (ramping, i.e. charging inclination) to produce a second sawtooth signal S _w2 having the second current source I _2, transistor M ₁₀ The transistor M ₁₁ and the second capacitor C ₂ must match the first current source I ₁ , the transistor M ₈ , the transistor M ₉ , and the first capacitor C _{1 of} the first sawtooth generator 1011a. When the second sawtooth wave signal S _w2 reaches the input signal V _rosc, the second comparator 1022 is at a high level to indicate the voltage level of the second signal S ₂ in FIG. 8. FIG. 8 is a timing chart of the second signal S ₂ , the second sawtooth signal S _w2 , and the input voltage V _rosc shown in FIGS. 7 and 2. As shown, the high voltage level of the second signal _{S 2} is fed back to the gate terminal of the transistor _{M 10, M 11,} to turn on the transistor _{M 10} and turns off the transistor _{M 11.} Then, the second current I ₂ increases the second signal voltage level of the S ₂ to charge the second capacitor C ₂ again, the second signal S ₂ is generated by it. It should be noted, the frequency of the second signal _{S 2} is input voltage _{V rosc,} the second capacitor _{C 2,} and is determined by the second current _{I 2,} the pulse time _{t 1} of the second signal _{S 2} and the second signal _{S 2} To the second sawtooth signal _Sw2 . In this embodiment, the input voltage V _rosc is set by the resistor R _ref . As another example, it is also possible to change the frequency of the second signal S ₂ by adjusting the second capacitor C ₂ or the second current I _2,. Such modifications are within the scope of the present invention.

When the frequency of the first signal S ₁ is higher than the second signal S ₂ , the maximum voltage of the first sawtooth signal S _w1 corresponding to the frequency of the first signal S ₁ is the input voltage set by the bias voltage generator 105. _Below V _rosc , the reference signal S _r remains at a low voltage level due to the action of the frequency detection circuit 101. In other words, the charging current I _c of the charge pump circuit 103 does not charge the fourth capacitor C ₄ in the charge pump circuit 103. Please refer to FIG. FIG. 9 is an explanatory diagram showing the charge pump circuit 103 shown in FIG. The charge pump 103 includes a plurality of transistors M _{12 to} M ₁₈ , a fifth switch W ₅ , a sixth switch W _6, and a fourth capacitor C ₄ . Among them, the transistors M ₁₃ and M ₁₈ are current mirrors that mirror the third current I ₃ as the charging current I _c , and the transistors M ₁₇ and M ₁₈ are other currents that mirror the third current I ₃ as the fourth current I _4. The transistors M ₁₆ and M ₁₂ are current mirrors that mirror the fourth current I ₄ as the discharge current I _dc . It should be noted that in this embodiment, the charging current I _c must match the discharging current I _dc . Further, since a method for obtaining a similar mirror current by setting an aspect ratio of a transistor is well known to those skilled in the art, a detailed description thereof is omitted here. Therefore, the voltage level V _oset decreases from the high voltage period t1 shown in FIG. 8 until it becomes lower than the third voltage V _r3 of the decision logic 104. Note that in this embodiment, the decision logic 104 is configured by a comparator, the voltage level V _oset is coupled to the inverting terminal (ie, N−) of the comparator shown in FIG. 2, and the third reference voltage V _r3 is Coupled to the non-inverting terminal (ie, N +) of the comparator shown in FIG. Thereafter, the output of decision logic 104 (ie, instruction signal V _id ) switches to a high voltage level. A state in which the instruction signal V _id of the decision logic 104 is at a high voltage level indicates that the frequency of the first signal S ₁ is higher than that of the second signal S ₂ .

By contrast, in the case where the frequency of the first signal S ₁ is less than the second signal S _2, the maximum voltage of the first sawtooth signal S _w1 corresponding to the frequency of the first signals S ₁ is set by the bias voltage generator 105 The reference signal S _r becomes _higher than the input voltage V _rosc and is equivalent to a single pulse signal having one pulse for each period of the first signal S ₁ due to the operation of the frequency detection circuit 101. Please refer to FIG. 8 and FIG. FIG. 10 is a timing chart of the reference signal S _r , the first sawtooth wave signal S _w1 , and the input voltage V _rosc shown in FIGS. 6 and 2. Notably, the high voltage cycle t2 of the pulse shown in FIG. 10 is related to the frequency of the first signal S _1, the high voltage cycle t1 of the pulse shown in FIG. 8 is associated with the loop response. The high voltage period t2 is not lower than the high voltage period t1. As a result, the voltage level _{V oset} is gradually increasing until it reaches the third reference voltage _{V r3,} the instruction signal _{V id} of the decision logic 104 switches to a low voltage level. This condition indicates that the frequency of the first signal S ₁ is less than the second signal S _2.

After the frequencies of the first signal S ₁ and the second signal S ₂ are determined by the frequency comparator 100 shown in FIG. 2, the instruction signal V _id of the decision logic 104 is in accordance with the design requirements according to the first signal S ₁ and those earlier out of the second signal S _2, or (functioning as or frequency selector) slowest selecting can. A frequency selector that selects one of a plurality of clock signals (for example, the first signal S ₁ and the second signal S ₂ ) based on the selection signal (for example, the instruction signal V _id ) is well known to those skilled in the art. Detailed explanation is omitted here.

Please refer to FIG. FIG. 11 is an explanatory diagram showing a frequency synthesizer 200 according to the present invention. The frequency synthesizer 200 that generates the second signal S ₂ based on the first signal S ₁ includes a frequency detection circuit 201, a frequency generator 202, a charge pump circuit 203, an adjustment circuit 204, a low-pass filter ( LPF) 205. The frequency detection circuit 201 generates a reference signal S _ref based on the first signal S ₁ and the first input voltage V _rosc1 , and the frequency generator 202 generates a second signal S ₂ based on the second input voltage V _rosc2. . The charge pump circuit 203 coupled to the frequency detection circuit 201 and the frequency generator 202 enables the charging current I _c ′ based on one of the reference signal S _ref and the second signal S ₂ to increase the voltage level V _oset , Further, the discharge current I _dc is enabled based on the other of the reference signal S _ref and the second signal S ₂ to lower the voltage level V _oset . In this embodiment, the charging operation is controlled by the second signal S _2. However, the present invention is not limited thereto. The adjustment circuit 204 coupled to the charge pump circuit 203, the frequency detection circuit 201, and the frequency generator 202 adjusts the frequency detection circuit 201 and the frequency generator 202 based on the voltage level V _oset , and the reference signal V _ref adjusting the frequency of the second signal S _2. The LPF 205 coupled to the charge pump circuit 203 and the adjustment circuit 204 filters the voltage level V _oset output from the adjustment circuit 204 to generate the first input voltage V _rosc1 . In the present embodiment, the LPF 205 extracts the DC level of the voltage level V _oset and _feeds it back to the adjustment circuit 204 as the first input voltage V _rosc1 .

In the embodiment shown in FIG. 11, the frequency detection circuit 201 is coupled to the first signals S _1, a first sawtooth generator 2011 which converts the first signals S ₁ to the first sawtooth wave signal S _{w1 ',} the one sawtooth signal _{S w1} 'and coupled to the first input voltage _{V Rosc1,} first sawtooth signal _{S w1'} and the first comparator 2012 for generating a reference signal _{V ref} as compared with the first input voltage _{V Rosc1} including. The first sawtooth wave generator 2011 includes a single pulse generation circuit 2011a, a first capacitor C ₁ ′, a first current source I ₁ ′, a first switch W ₁ ′, a second switch W ₂ ′, Switch control circuit 1011b. The single pulse generating circuit 2011a is coupled to the first signals _{S 1} generates one pulse signal _{S p1} for each cycle of the first signals _{S 1.} The first capacitor C ₁ ′ is coupled between the output node N ₁ ′ of the first sawtooth generator 2011 and the first reference voltage V _ss (ie, ground voltage), and the first current source I ₁ ′ is coupled to the second reference voltage V _ss. Coupled to voltage V _dd (ie, supply voltage). The first switch W ₁ ′ coupled between the first current source I ₁ ′ and the output node N ₁ ′ of the first sawtooth generator 2011 is based on the first switch control signal S _c1 ′. A second switch W ₂ ′ that selectively couples I ₁ ′ to the first capacitor C ₁ ′ and is coupled between the output node N ₁ ′ of the first sawtooth generator 2011 and the first reference voltage V _dd is provided. The first capacitor C ₁ ′ is selectively coupled to the first reference voltage V _dd based on the second switch control signal S _c2 ′. The switch control circuit 2011b coupled to the single pulse generation circuit 2011a, the first switch W ₁ ′, and the second switch W ₂ ′ is based on the output signal (ie, S _p1 ) of the single pulse generation circuit 2011a. A switch control signal S _c1 ′ and a second switch control signal S _c2 ′ are generated.

Frequency generator 202 is coupled to the second signal S _{2, 'and} a second sawtooth generator 2021 which converts the second sawtooth wave signal S _w2' a second signal S ₂ second sawtooth wave signal S _w2 and A second _{comparator 2022} coupled to the second input voltage V _rosc2 and comparing the second sawtooth signal S _w2 ′ with the second input voltage V _rosc2 to generate a second signal S ₂ . The second sawtooth wave generator 2021 includes a second capacitor C ₂ ′, a second current source I ₂ ′, a third switch W ₃ ′, a fourth switch W ₄ ′, and a switch control circuit 2021a. The second capacitor C ₂ ′ is coupled between the output node N ₂ ′ of the second sawtooth generator 2021 and the first reference voltage V _ss , and the second current source I ₂ ′ is coupled to the second reference voltage V _dd . Has been. The third switch W ₃ ′ coupled between the second current source I ₂ ′ and the output node N ₂ ′ of the second sawtooth generator 2021 is connected to the second current source based on the third switch control signal S _c3 ′. Is coupled to the second capacitor, and a fourth switch W ₄ ′ coupled between the output node N ₂ ′ of the second sawtooth generator 2021 and the first reference voltage V _ss has a fourth switch control signal. The second capacitor C ₂ ′ is selectively coupled to the first reference voltage V _ss based on S _c4 ′. The switch control circuit 2021a coupled to the second signal S ₂ ′, the third switch W ₃ ′, and the fourth switch W ₄ ′ has a second output from the output node N ₂ ′ of the second sawtooth generator 2021. Based on the signal S ₂ ′, a third switch control signal S _c3 ′ and a fourth switch control signal S _c4 ′ are generated.

In this embodiment, the adjustment circuit 204 is constituted by a voltage divider having _two resistors R ₁ and R ₂ connected in series with each other, and its input node N ₃ ′ is coupled to the first comparator 2012, Output node N ₄ ′ is coupled to a second comparator 2022. Note that, compared with the frequency comparator 100, the frequency synthesizer 200 is provided with an adjustment circuit 204, and an LPF 205 is provided instead of the decision logic 104. Other than that, since the frequency detection circuit 201, the frequency generator 202, and the charge pump circuit 203 of the frequency synthesizer 200 are all close to the frequency detection circuit 101, the frequency generator 102, and the charge pump circuit 103 of the frequency comparator 100, Detailed explanation is omitted here.

Reference is again made to the frequency synthesizer 200 shown in FIG. The first current source I ₁ ′ matches the second current source I ₂ ′, the first capacitor C ₁ ′ matches the second capacitor C ₂ ′, and the charging current I _c ′ matches the discharge current I _dc ′. ing. Input node N ₃ ′ is coupled to the inverting terminal of first comparator 2012 (ie, N−), and output node N ₄ ′ is coupled to the inverting terminal of second comparator 2022 (ie, N−). Therefore, the reference voltage of the second comparator 2022 (that is, the second input voltage V _rosc2 ) is determined by the resistance value ratio between the resistors R ₁ and R ₂ . According to the above, if the frequency of the first signal S ₁ (that is, the external clock signal) is not changed, the turn-on time in each cycle of the first signal S ₁ of the fifth switch W ₅ ′ of the charge pump circuit 203 is It is determined by the first input voltage V _rosc1 . In short, the resistance value ratio between the resistors R ₁ and R ₂ is 3 (R ₁ / R ₂ = 3). It should be noted that the resistance value ratio of the resistors R ₁ and R ₂ can be changed according to design requirements. In the frequency synthesizer 11 shown in FIG. 11, the resistor R ₁ , the first comparator 2012, the charge pump circuit 203, and the LPF 205 form a closed loop feedback system. Therefore, as shown in FIG. 12, the first input voltage V _rosc1 is fixed to the peak voltage of the first sawtooth signal S _w1 ′. FIG. 12 is a timing diagram of the first input voltage V _rosc1 , the first sawtooth wave signal S _w1 ′, and the second sawtooth wave signal S _w2 ′. Since the second input voltage V _rosc2 is a _quarter of the first input voltage V _rosc1 , as shown in FIG. 12, the frequency generator 202 quadruples the frequency of the first sawtooth signal S _w1 ′ (ie, 1 + R1). / R2) to generate the second sawtooth signal S _w2 ′. Therefore, in order to generate the second signal S ₂ having a frequency four times that of the first signal S ₁ , R1 / R2 = 3 may be set. It is also possible to generate the required second signal S _{2 by} setting the resistance value ratio of the resistors R ₁ and R ₂ to other arbitrary values. Similarly, the connection between the voltage divider and the comparators 2012 and 2022 can be adjusted so that the frequency synthesizer 200 operates as a frequency multiplier or a frequency divider. Of which the first signals S ₁ and the frequency relationship between the second signal S ₂ is set based on the voltage divider resistors.

It should be noted that the present invention is not limited to the resistance value ratio setting of the resistors R ₁ and R ₂ , but is a method capable of adjusting the charging slope of the first sawtooth wave signal S _w1 ′ and the second sawtooth wave signal S _w2 ′. All are within the scope of the present invention. For example, as one embodiment of the present invention, it is possible to set the first current source I ₁ ′ and the second current source I ₂ ′ using the first input voltage V _rosc1 and fix the required frequency, As another example, the first capacitor C ₁ ′ and the second capacitor C ₂ ′ can be set using the first input voltage V _rosc1 to fix the required frequency. _Setting the resistors R ₁ and R ₂ using the first input voltage V _rosc1 , setting the first capacitor C ₁ ′ and the second capacitor C ₂ ′ using the first input voltage V _rosc1 , _Setting the first current source I ₁ ′ and the second current source I ₂ ′ using the input voltage V _rosc1, and combinations of these methods are both between the first signal S ₁ and the second signal S ₂ . Since the frequency relationship can be controlled, it belongs to the scope of the present invention.

Please refer to FIG. FIG. 13 is a flowchart of the frequency comparison method according to the present invention. The method compares the frequencies of the first signal S ₁ and the second signal S ₂ shown in FIG. 2 as follows.

Step 302: Start.
Step 304: Receive a first signal _{S 1.}
Step 306: converting the first signals _{S 1} to the first sawtooth wave signal _{S w1.}
Step 308: the first sawtooth wave signal _{S w1} compares the input voltage _{V rosc,} generates a reference signal _{V ref.} Proceed to step 312.
Step 310: Generate a second signal _{S 2} corresponding to the input voltage _{V rosc.}
Step 312: The charging and discharging the charge pump type capacitance _{C 5} by the reference signal _{V ref} and the second signal _{S 2.}
Step 314: the shown one signals _{S 1} and the frequency relationship between the second signal _{S 2} with the decision logic 104.

  Since all of the steps 302 to 314 of the frequency comparison method have been introduced above, description thereof will be omitted here.

Refer to FIG. FIG. 13 is a flowchart of the frequency synthesis method according to the present invention. The method generates the frequency of the second signal S ₂ based on the first signal S ₁ shown in FIG. 11 as follows.

Step 402: Start.
Step 404: Receive a first signal _{S 1.}
Step 406: converting the first signals _{S 1} to the first sawtooth wave signal _{S w1.}
Step 408: The first input voltage V _rosc1 is set. Proceed to step 413.
Step 410: Set the second input voltage _Vrosc2 .
Step 412: Generate a second signal _{S 2.} Proceed to step 414.
Step 413: Generate a reference signal _Sref .
Step 414: The capacitor C ₅ ′ is charged and discharged by the charge pump method using the reference signal S _ref and the second signal S ₂ .
Step 416: Filter the voltage level V _oset in a low-pass manner to generate a first input voltage V _rosc1 . Proceed to step 408.

Since all the steps 402 to 416 of the frequency synthesis method have been introduced above, description thereof will be omitted here.

  The above is a preferred embodiment of the present invention and does not limit the scope of the present invention. Therefore, any modifications or changes that can be made by those skilled in the art, which are made within the spirit of the present invention and have an equivalent effect on the present invention, shall belong to the scope of the claims of the present invention. To do.

  The present invention is intended to use an analog circuit instead of a digital circuit. Such a method is feasible.

It is explanatory drawing showing the conventional frequency comparator. It is explanatory drawing showing the frequency comparator by this invention. It is explanatory drawing showing the bias voltage generator shown in FIG. FIG. 3 is an explanatory diagram illustrating a single pulse generation circuit illustrated in FIG. 2. FIG. 3 is a timing diagram of the delayed signal S _delay , the first signal S ₁ , the single pulse signal S _p1 , and the first sawtooth signal S _w1 shown in FIGS. 4 and 2. It is explanatory drawing showing the 1st sawtooth wave generator shown in FIG. It is explanatory drawing showing the 2nd sawtooth wave generator shown in FIG. FIG. 3 is a timing chart of the second signal S ₂ , the second sawtooth signal S _w2 , and the input voltage V _rosc shown in FIGS. 7 and 2. FIG. 3 is an explanatory diagram illustrating the charge pump circuit illustrated in FIG. 2. FIG. 3 is a timing diagram of the reference signal S _r , the first sawtooth signal S _w1 , and the input voltage V _rosc shown in FIGS. 6 and 2. It is explanatory drawing showing the frequency synthesizer by this invention. FIG. 6 is a timing diagram of a first input voltage V _rosc1 , a first sawtooth wave signal S _w1 ′, and a second sawtooth wave signal S _w2 ′. 3 is a flowchart of a frequency comparison method according to the present invention. 3 is a flowchart of a frequency synthesis method according to the present invention.

Explanation of symbols

10, 100 Frequency comparator 11, 101, 201 Frequency detection circuit 12, 13 Count circuit 14, 104 Decision logic 102, 202 Frequency generator 103, 203 Charge pump circuit 105 Bias voltage generator 200 Frequency synthesizer 204 Adjustment circuit 205 LPF
1011, 1021, 2011, 2021 Sawtooth wave generator 1011a, 2011a Single pulse generator circuit 1011b, 1021a, 2011b, 2021a Switch control circuit 1012, 1022, 2012, 2022 Comparator 1051 Reference voltage generator circuit 1052 Error amplifier 1053 Current mirror circuit

Claims (38)

A frequency comparator for comparing the frequency of the first signal and the second signal,
A frequency detection circuit for generating a reference signal based on the first signal and the input voltage;
A frequency generator for generating a second signal based on the input voltage;
Coupled to the frequency detection circuit and the frequency generator to enable the charge current based on one of the reference signal and the second signal to increase the voltage level and further enable the discharge current based on the other of the reference signal and the second signal And a charge pump circuit that lowers the voltage level,
A frequency comparator coupled to the charge pump circuit and including decision logic indicating a frequency relationship between the first signal and the second signal based on the voltage level. The frequency detection circuit includes:
A first sawtooth generator coupled to the first signal and converting the first signal to a first sawtooth signal;
The frequency of claim 1, further comprising a first comparator coupled to a first sawtooth signal and the input voltage to compare the first sawtooth signal and the input voltage to generate the reference signal. Comparator. The first sawtooth generator is
A single pulse generating circuit coupled to the first signal and generating one pulse signal for each period of the first signal;
A first capacitor coupled between an output node of the first sawtooth generator and a first reference voltage;
A first current source coupled to a second reference voltage;
A first switch coupled between the first current source and the output node of the first sawtooth generator and selectively coupling the first current source to the first capacitor based on a first switch control signal;
A second switch coupled between the output node of the first sawtooth generator and the first reference voltage and selectively coupling the first capacitance to the first reference voltage based on a second switch control signal;
A switch control circuit coupled to the single pulse generation circuit, the first switch, and the second switch, and generating the first switch control signal and the second switch control signal based on the output of the single pulse generation circuit. The frequency comparator according to claim 2. The frequency generator is
A second sawtooth generator coupled to the second signal and converting the second signal into a second sawtooth signal;
2. A second comparator coupled to a second sawtooth signal and the input voltage, the second sawtooth signal and a second comparator for comparing the input voltage to generate the second signal. Frequency comparator. The second sawtooth generator is
A second capacitor coupled between the output node of the second sawtooth generator and the first reference voltage;
A second current source coupled to a second reference voltage;
A third switch coupled between the second current source and the output node of the second sawtooth generator and selectively coupling the second current source to the second capacitor based on a third switch control signal;
A fourth switch coupled between the output node of the second sawtooth generator and the first reference voltage and selectively coupling the second capacitance to the first reference voltage based on a fourth switch control signal;
The third switch control signal and the fourth switch control signal are generated based on the second signal output from the output node of the second sawtooth wave generator, coupled to the second signal, the third switch, and the fourth switch. The frequency comparator according to claim 4, further comprising a switch control circuit that performs the operation.   2. The frequency comparator according to claim 1, wherein the decision logic has the voltage level and a third reference voltage, and outputs an instruction signal indicating a frequency relationship between the first signal and the second signal. The frequency comparator further includes
A resistor,
A reference voltage generation circuit coupled to the resistor and configured to set the input voltage based on a resistance value of the resistor, the reference voltage generation circuit, a frequency detection circuit, a frequency generator, a charge pump circuit, and a decision 2. The frequency comparator according to claim 1, wherein the logic is integrated into one chip, and the resistor is provided outside the chip. A frequency synthesizer that generates a second signal based on a first signal,
A frequency detection circuit that generates a reference signal based on the first signal and the first input voltage;
A frequency generator for generating a second signal based on a second input voltage;
Coupled to the frequency detection circuit and the frequency generator to enable the charge current based on one of the reference signal and the second signal to increase the voltage level and further enable the discharge current based on the other of the reference signal and the second signal And a charge pump circuit that lowers the voltage level,
A charge pump circuit, a frequency detection circuit, and a frequency generator are included, and the frequency detection circuit and the frequency generator are adjusted based on the voltage level, and include an adjustment circuit that adjusts the frequency of the reference signal and the second signal. A frequency synthesizer. The frequency synthesizer further includes:
9. A frequency synthesizer according to claim 8, further comprising a low-pass filter (LPF) coupled between the charge pump circuit and the regulator circuit and filtering the voltage level output to the regulator circuit in a low-pass manner. vessel. The frequency detection circuit includes:
A first sawtooth generator coupled to the first signal and converting the first signal to a first sawtooth signal;
And a first comparator coupled to the first sawtooth signal and the first input voltage to compare the first sawtooth signal and the first input voltage to generate the reference signal. 8. The frequency synthesizer according to 8. The first sawtooth generator is
A single pulse generating circuit coupled to the first signal and generating one pulse signal for each period of the first signal;
A first capacitor coupled between an output node of the first sawtooth generator and a first reference voltage;
A first current source coupled to a second reference voltage;
A first switch coupled between the first current source and the output node of the first sawtooth generator and selectively coupling the first current source to the first capacitor based on a first switch control signal;
A second switch coupled between the output node of the first sawtooth generator and the first reference voltage and selectively coupling the first capacitance to the first reference voltage based on a second switch control signal;
A switch control circuit coupled to the single pulse generation circuit, the first switch, and the second switch, and generating the first switch control signal and the second switch control signal based on the output of the single pulse generation circuit. The frequency synthesizer according to claim 10. The frequency generator is
A second sawtooth generator coupled to the second signal and converting the second signal into a second sawtooth signal;
And a second comparator coupled to the second sawtooth signal and the second input voltage to compare the second sawtooth signal and the second input voltage to generate the second signal. Item 12. A frequency synthesizer according to Item 11. The second sawtooth generator is
A second capacitor coupled between the output node of the second sawtooth generator and the first reference voltage;
A second current source coupled to a second reference voltage;
A third switch coupled between the second current source and the output node of the second sawtooth generator and selectively coupling the second current source to the second capacitor based on a third switch control signal;
A fourth switch coupled between the output node of the second sawtooth generator and the first reference voltage and selectively coupling the second capacitance to the first reference voltage based on a fourth switch control signal;
The third switch control signal and the fourth switch control signal are generated based on the second signal output from the output node of the second sawtooth wave generator, coupled to the second signal, the third switch, and the fourth switch. 13. The frequency synthesizer according to claim 12, further comprising: a switch control circuit that performs switching.   The first input voltage is different from the second input voltage, and the adjustment circuit adjusts the first input voltage and the second input voltage based on the voltage level output from a charge pump circuit. 13. The frequency synthesizer according to 13.   The adjustment circuit is a frequency divider having an input node coupled to one of the first comparator and the second comparator and an output node coupled to the other of the first comparator and the second comparator. 15. The frequency synthesizer according to claim 14, wherein:   The frequency divider includes a plurality of resistors, the frequency detection circuit, the frequency generator, and the charge pump circuit are integrated into one chip, and at least one resistor of the adjustment circuit is provided outside the chip. The frequency synthesizer according to claim 15.   The first input voltage coincides with the second input voltage, and the adjustment circuit adjusts the first input voltage and the second input voltage based on the voltage level output from a charge pump circuit. Item 14. A frequency synthesizer according to Item 13.   14. The first input voltage matches the second input voltage, and the adjustment circuit adjusts the first capacitance and the second capacitance based on the voltage level output from a charge pump circuit. The frequency synthesizer described. The frequency generator is
A second sawtooth generator coupled to the second signal and converting the second signal into a second sawtooth signal;
And a second comparator coupled to the second sawtooth signal and the second input voltage to compare the second sawtooth signal and the second input voltage to generate the reference signal. 8. The frequency synthesizer according to 8. The second sawtooth generator is
A second capacitor coupled between the output node of the second sawtooth generator and the first reference voltage;
A second current source coupled to a second reference voltage;
A third switch coupled between the second current source and the output node of the first sawtooth generator and selectively coupling the second current source to the second capacitor based on a third switch control signal;
A fourth switch coupled between the output node of the second sawtooth generator and the first reference voltage and selectively coupling the second capacitance to the first reference voltage based on a fourth switch control signal;
The third switch control signal and the fourth switch control signal are generated based on the second signal output from the output node of the second sawtooth wave generator, coupled to the second signal, the third switch, and the fourth switch. 20. The frequency synthesizer according to claim 19, further comprising: a switch control circuit that performs a switching operation. A frequency comparison method for comparing frequencies of a first signal and a second signal,
(A) generating a reference signal based on the first signal and the input voltage;
(B) generating a second signal based on the input voltage;
(C) enabling the charging current based on one of the reference signal and the second signal to increase the voltage level, further enabling the discharging current based on the other of the reference signal and the second signal, and decreasing the voltage level;
(D) A frequency comparison method comprising the steps of showing a frequency relationship between the first signal and the second signal based on the voltage level. The step (a)
Converting the first signal into a first sawtooth signal,
The frequency comparison method according to claim 21, further comprising the step of generating a reference signal by comparing a first sawtooth wave signal with the input voltage. Converting the first signal into a first sawtooth signal,
Generating one pulse signal for each period of the first signal;
Providing the first capacity,
Providing a first current source,
Selectively coupling the first current source to the first capacitor based on the first switch control signal;
Selectively coupling the first capacitor to the first reference voltage based on the second switch control signal;
23. The frequency comparison method according to claim 22, further comprising the step of generating the first switch control signal and the second switch control signal based on a pulse signal generated one for each period of the first signal. . The step (b)
Convert the second signal into a second sawtooth signal,
The frequency comparison method according to claim 21, further comprising the step of generating a second signal by comparing a second sawtooth wave signal with the input voltage. Converting the second signal into a second sawtooth signal,
Provide a second capacity,
Providing a second current source,
Selectively coupling the second current source to the second capacitor based on the third switch control signal;
Selectively coupling the second capacitor to the first reference voltage based on the fourth switch control signal;
The frequency comparison method according to claim 24, further comprising the step of generating the third switch control signal and the fourth switch control signal based on a second signal.   The step (d) includes a step of outputting an instruction signal indicating a frequency relationship between the first signal and the second signal based on the voltage level and the third reference voltage. Frequency comparison method. The frequency comparison method further includes:
Provide resistors,
The frequency comparison method according to claim 21, further comprising the step of setting the input voltage based on a resistance value of the resistor. A frequency synthesis method for generating a second signal based on a first signal,
(E) generating a reference signal based on the first signal and the first input voltage;
(F) generating a second signal based on the second input voltage;
(G) enabling the charging current based on one of the reference signal and the second signal to increase the voltage level, further enabling the discharging current based on the other of the reference signal and the second signal, and decreasing the voltage level;
(H) A frequency synthesizing method comprising adjusting the frequencies of the reference signal and the second signal based on the voltage level. The frequency synthesis method further includes:
29. The frequency synthesis method according to claim 28, further comprising the step of filtering the voltage level in a low-pass manner. The step (e)
Convert the first signal to the first sawtooth signal,
29. The frequency synthesis method according to claim 28, further comprising the step of comparing the first sawtooth signal and the first input voltage to generate the reference signal. Converting the first signal into a first sawtooth signal,
Generate one pulse signal for each period of the first signal,
Providing the first capacity,
Providing a first current source,
Selectively coupling the first current source to the first capacitor based on the first switch control signal;
Selectively coupling the first capacitor to the first reference voltage based on the second switch control signal;
31. The frequency synthesis method according to claim 30, further comprising the step of generating the first switch control signal and the second switch control signal based on a pulse signal generated for each period of the first signal. . The step (f)
Convert the second signal into a second sawtooth signal,
32. The frequency synthesis method according to claim 31, further comprising the step of comparing the second sawtooth signal and the second input voltage to generate the second signal. Converting the second signal into a second sawtooth signal,
Provide a second capacity,
Providing a second current source,
Selectively coupling the second current source to the second capacitor based on the third switch control signal;
Selectively coupling the second capacitor to the first reference voltage based on the fourth switch control signal;
The frequency synthesis method according to claim 32, further comprising the step of generating the third switch control signal and the fourth switch control signal based on a second signal.   The frequency synthesis of claim 33, wherein the first input voltage is different from the second input voltage, and the step (h) adjusts the first input voltage and the second input voltage based on the voltage level. Method.   The frequency of claim 33, wherein the first input voltage matches the second input voltage, and wherein the step (h) adjusts the first input voltage and the second input voltage based on the voltage level. Synthesis method.   The frequency synthesis method according to claim 33, wherein the first input voltage matches the second input voltage, and the adjustment circuit adjusts the first capacitance and the second capacitance based on the voltage level. The step (h)
Convert the second signal into a second sawtooth signal,
29. The frequency synthesis method according to claim 28, further comprising the step of comparing the second sawtooth signal and the second input voltage to generate the reference signal. The second signal is a second sawtooth signal,
Provide a second capacity,
Providing a second current source,
Selectively coupling the second current source to the second capacitor based on the third switch control signal;
Selectively coupling the second capacitor to the first reference voltage based on the fourth switch control signal;
The frequency synthesis method according to claim 37, further comprising the step of generating the third switch control signal and the fourth switch control signal based on a second signal.

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