CN112782473B - A frequency detection circuit and method - Google Patents

Abstract

The invention provides a frequency detection circuit and a frequency detection method, wherein during frequency detection, a constant current source outputs current to charge a variable capacitor for multiple periods. In the calibration mode, the capacitance value of the variable capacitor is adjusted according to the comparison result of the voltage across the variable capacitor and the reference voltage, so as to obtain a target capacitance value of the variable capacitor. In the monitoring mode, the operation frequency to be measured of the circuit to be measured is obtained according to the reference frequency and the voltage across the variable capacitor.

Description

A frequency detection circuit and method

Technical Field

The present invention relates to a frequency detection circuit and method, in particular to a frequency detection circuit and method applicable to an optical fiber transceiver, which can detect the circuit operating frequency in real time and dynamically.

Background technique

Digital data may be prone to noise when transmitted at high speed. Therefore, transceivers usually need a clock and data recovery circuit (CDR) to regenerate low-jitter frequency and restore low-noise data. Therefore, the clock and data recovery circuit plays an important role in the transmission and reception of data and frequency.

The frequency generated by the frequency data recovery circuit should preferably meet the following requirements: 1. The frequency must be the same as the data rate. 2. There must be a correct phase relationship between the frequency and the data. 3. The frequency itself must have small jitter.

When using a frequency data recovery circuit, it will be helpful for subsequent operations if the operating frequency of the frequency data recovery circuit can be detected.

Summary of the invention

The present invention provides a frequency detection circuit and method, which can detect the operating frequency of the circuit in real time and dynamically.

According to an embodiment of the present case, a frequency detection circuit is provided for detecting a frequency to be measured of a circuit to be measured, and the frequency detection circuit includes: an error amplifier for comparing a first reference voltage with a node voltage and outputting a first comparison result; a current mirror coupled to the error amplifier and outputting a reference current according to the first comparison result, wherein the reference current is used to generate the node voltage, and the current mirror further outputs an output current according to the reference current; a variable capacitor coupled to the current mirror, and the output current of the current mirror charges the variable capacitor; a comparator coupled to the variable capacitor and comparing a second reference voltage with a voltage across the variable capacitor to generate a second comparison result; and a control circuit coupled to the comparator and the variable capacitor, the control circuit outputting a control signal according to the second comparison result of the comparator to control a capacitance value of the variable capacitor, the control circuit further resets the voltage across the variable capacitor, and the control circuit receives a reference frequency and the frequency to be measured of the circuit to be measured. In a calibration mode, the control circuit receives the reference frequency, and in a plurality of calibration cycles, the output current of the current mirror charges the variable capacitor. At the end of each of the calibration cycles, the control circuit resets the cross voltage of the variable capacitor. At the end of each of the calibration cycles, the control circuit controls the control signal according to the second comparison result output by the comparator to control the capacitance value of the variable capacitor in the next calibration cycle. After the calibration mode ends, the control circuit determines a target capacitance value of the variable capacitor. In a monitoring mode, in a first monitoring cycle, the control circuit receives the reference frequency, and at the end of the first monitoring cycle, the cross voltage of the variable capacitor is measured as a first cross voltage. In a second monitoring cycle, the control circuit receives the frequency to be measured provided by the circuit to be measured, and at the end of the second monitoring cycle, the cross voltage of the variable capacitor is measured as a second cross voltage. The control circuit determines the frequency to be measured according to the reference frequency, the first cross voltage and the second cross voltage.

According to another embodiment of the present case, a frequency detection method is proposed to detect a frequency to be tested of a circuit to be tested. The frequency detection method includes: comparing a first reference voltage with a node voltage and outputting a first comparison result; outputting a reference current according to the first comparison result, wherein the reference current is used to generate the node voltage, and further outputting an output current according to the reference current; charging the variable capacitor with the output current; comparing a second reference voltage with a cross voltage of the variable capacitor to generate a second comparison result; and outputting a control signal according to the second comparison result to control a capacitance value of the variable capacitor and reset the cross voltage of the variable capacitor. In a calibration mode, a reference frequency is received, and in multiple calibration cycles, the output current charges the variable capacitor, and at the end of each of the calibration cycles, the cross voltage of the variable capacitor is reset, and at the end of each of the calibration cycles, the control signal is controlled according to the second comparison result to control the capacitance value of the variable capacitor in the next calibration cycle. After the calibration mode ends, a target capacitance value of the variable capacitor is determined. In a monitoring mode, the reference frequency is received in a first monitoring cycle, and at the end of the first monitoring cycle, the voltage across the variable capacitor is measured as a first voltage across the variable capacitor. In a second monitoring cycle, the frequency to be tested provided by the circuit to be tested is received, and at the end of the second monitoring cycle, the voltage across the variable capacitor is measured as a second voltage across the variable capacitor, and the frequency to be tested is determined according to the reference frequency, the first voltage across the variable capacitor, and the second voltage across the variable capacitor.

In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a functional block diagram of a frequency detection circuit according to an exemplary embodiment of the present invention.

FIG. 2 is a waveform diagram showing a frequency detection circuit operating in a calibration mode according to an exemplary embodiment of the present invention.

FIG. 3 is a waveform diagram showing a frequency detection circuit operating in a monitoring mode according to an exemplary embodiment of the present invention.

FIG. 4 is a flow chart showing a frequency detection method according to an exemplary embodiment of the present invention.

Reference numerals

100: Frequency detection circuit 50: Circuit to be tested

110: Error amplifier 120: Current mirror

R: resistance C: variable capacitance

130: Comparator 140: Control circuit

SW: switch N1: node

T1-T7: Cycle

410-490: Steps

Detailed ways

The technical terms used in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in the technical field can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

1 shows a functional block diagram of a frequency detection circuit according to an exemplary embodiment of the present invention. The frequency detection circuit 100 is used to detect the operating frequency of the circuit under test 50. The circuit under test 50 may be, for example, a clock and data recovery circuit (CDR), but the present invention is not limited thereto.

The frequency detection circuit 100 includes an error amplifier (EA) 110 , a current mirror 120 , a resistor R, a variable capacitor C, a comparator 130 , a control circuit 140 and a switch SW.

The error amplifier 110 is used to compare the first reference voltage VREF1 with the voltage of the node N1, wherein the voltage of the node N1 can be expressed as: VN1=IREF*R, IREF represents the reference current output by the current mirror 120, and R represents the resistance value of the resistor R (which is a predetermined value). The comparison result of the error amplifier 110 (also referred to as the "first comparison result") can be input to the current mirror 120 to adjust the reference current IREF output by the current mirror 120, that is, to adjust the voltage VN1 of the node N1. Through the operation of the error amplifier 110, the voltage VN1 of the node N1 can be close to the first reference voltage VREF1, that is, VREF=IREF*R. Therefore, it can be deduced that when the voltage VN1 of the node N1 is close to the first reference voltage VREF1, the reference current IREF output by the current mirror 120 can be expressed as: IREF=VREF/R.

The current mirror 120 is coupled to the error amplifier 110 and the resistor R. As described above, when the voltage VN1 of the node N1 is close to the first reference voltage VREF1, the reference current IREF output by the current mirror 120 can be expressed as: IREF=VREF/R. The current mirror 120 further outputs an output current IOUT, which can be expressed as: IOUT=M*IREF, where the parameter M represents the current amplification factor of the current mirror 120. The circuit architecture of the current mirror 120 is not particularly limited here. The current mirror 120 can also be called a constant current source.

The resistor R is coupled to the error amplifier 110 and the current mirror 120 , and the reference current IREF flows through the resistor R. The voltage across the resistor R is the voltage VN1 of the node N1 .

The variable capacitor C is coupled to the current mirror 120. The variable capacitor C can be a capacitor matrix. During a charging period, the output current IOUT of the current mirror 120 can charge the variable capacitor C to increase the voltage VOUT of the variable capacitor C. The longer the charging period, the higher the voltage VOUT of the variable capacitor C, and vice versa. In addition, if the capacitance of the variable capacitor C is larger, the rise/fall speed of the voltage VOUT of the variable capacitor C will naturally be slower, and vice versa. In the present embodiment, the voltage VOUT of the variable capacitor C can be measured.

The comparator 130 is coupled to the variable capacitor C. The comparator 130 is used to compare the second reference voltage VREF2 with the voltage across the variable capacitor C VOUT to generate a second comparison result. The second comparison result of the comparator 130 is input to the control circuit 140 .

The control circuit 140 is coupled to the comparator 130 and the variable capacitor C. The control circuit 140 outputs a control signal CTRL according to the output signal of the comparator 130 (i.e., the second comparison result) to control the capacitance value of the variable capacitor C. In addition, the control circuit 140 can output a reset signal RS to the switch SW to reset the voltage VOUT of the variable capacitor C. The control circuit 140 receives a reference frequency FREF and a frequency to be measured FTEST. The switch SW is coupled to the variable capacitor C and the control circuit 140.

Below, the control signal CTRL is taken as 4 bits as an example, but it should be known that the present case is not limited to this. The capacitance value of the variable capacitor C can be expressed as: C = CTRL * Cunit, where Cunit represents the unit capacitance. When the control signal CTRL is [1111], the capacitance value of the variable capacitor C has a maximum value; when the control signal CTRL is [0000], the capacitance value of the variable capacitor C has a minimum value. The rest can be deduced accordingly. Therefore, when the control signal CTRL increases, the capacitance value of the variable capacitor C increases accordingly; and vice versa.

The switch SW is controlled by the control circuit 140. When the control circuit 140 outputs a reset signal RS to the switch SW, the switch SW is turned on to discharge the voltage stored in the variable capacitor C (ie, to reset the voltage VOUT of the variable capacitor C).

FIG2 shows a waveform diagram of a frequency detection circuit operating in a calibration mode according to an exemplary embodiment of the present invention. The length of each period T1-T4 (also referred to as a calibration period T1-T4) is TREF=N/FREF (N is a positive integer), where FREF represents a reference frequency, which can be provided by the circuit under test 50 or by an external reference signal source (not shown).

As shown in FIG2 , in the first cycle T1, the control signal CTRL is set to [1000]. In the charging period TREF, the output current IOUT of the current mirror 120 charges the variable capacitor C, so that the voltage VOUT of the variable capacitor C increases. At the end of the charging period TREF, the control circuit 140 outputs a reset signal RS to the switch SW to reset the voltage VOUT of the variable capacitor C. At the end of the first cycle T1, the control circuit 140 can output the control signal CTRL to the variable capacitor C according to the comparison result of the comparator 130 to control the capacitance value of the variable capacitor C in the next cycle T2. That is, if the voltage VOUT of the variable capacitor C is higher than the second reference voltage VREF2 at the end of the first cycle T1, it means that the capacitance value of the variable capacitor C is lower. Therefore, in the next cycle, the control circuit 140 increases the value of the control signal CTRL (for example, from [1000] to [1100]) to increase the capacitance value of the variable capacitor C. It is worth noting that the present invention can increase (or decrease) the number of bits of the digital control signal CTRL according to the accuracy requirements. On the contrary, if the voltage VOUT of the variable capacitor C is lower than the second reference voltage VREF2 at the end of the first cycle T1, it means that the capacitance of the variable capacitor C is higher. Therefore, in the next cycle, the control circuit 140 reduces the value of the control signal CTRL (for example, from [1000] to [0111]) to reduce the capacitance of the variable capacitor C.

Taking FIG. 2 as an example, after the first cycle T1 ends, the voltage VOUT of the variable capacitor C is higher than the second reference voltage VREF2 (indicating that the capacitance value of the variable capacitor C is lower). In the next cycle T2, the control circuit 140 increases the value of the control signal CTRL (from [1000] to [1100]) to increase the capacitance value of the variable capacitor C.

Similarly, taking FIG. 2 as an example, after the second cycle T2 ends, the voltage VOUT of the variable capacitor C is lower than the second reference voltage VREF2 (indicating that the capacitance value of the variable capacitor C is higher). In the next cycle T3, the control circuit 140 reduces the value of the control signal CTRL (from [1100] to [1010]) to reduce the capacitance value of the variable capacitor C.

Similarly, taking FIG. 2 as an example, after the third cycle T3 ends, the voltage VOUT of the variable capacitor C is higher than the second reference voltage VREF2 (indicating that the capacitance value of the variable capacitor C is lower). In the next cycle T4, the control circuit 140 reduces the value of the control signal CTRL (from [1010] to [1011]) to reduce the capacitance value of the variable capacitor C.

After 4 cycles, the voltage VOUT of the variable capacitor C is closer to the second reference voltage VREF2, which means that the capacitance of the variable capacitor C is close to the target value CREF, wherein VOUT=(IOUT*TREF)/CREF, therefore, CREF=(IOUT*TREF)/VOUT.

That is, in the calibration mode, the target capacitance value of the variable capacitor C is determined (that is, the value of the control signal CTRL is determined). After the target capacitance value of the variable capacitor C is determined, the frequency detection circuit can enter the monitoring mode from the calibration mode. In the monitoring mode, the capacitance value of the variable capacitor C is the same as the capacitance value of the variable capacitor C in the last cycle in the calibration mode. In one embodiment, the present invention can selectively perform several more rounds of 4-cycle measurement cycles as needed.

FIG3 shows a waveform diagram of a frequency detection circuit operating in a monitoring mode according to an exemplary embodiment of the present invention. In FIG3, during period T5 (period T5 may also be referred to as a first monitoring period), the control circuit 140 receives a reference frequency FREF to control the length of period T5 to TREF=N/FREF (N is a positive integer). After period T5 ends, the voltage VOUT of the variable capacitor C is measured (its value is represented as VOUT_REF, or referred to as the first voltage) and reset.

During period T6 (period T6 may also be referred to as the second monitoring period), the control circuit 140 receives the test frequency FTEST provided by the test circuit 50, and controls the length of period T6 to be TTEST=N/FTEST (N is a positive integer). After period T6 ends, the voltage VOUT of the variable capacitor C is measured (its value is represented as VOUT_TEST, or referred to as the second voltage), and reset.

In the monitoring mode, since the capacitance of the variable capacitor C is fixed and known, and the output current IOUT of the current mirror 120 is also fixed and known, the voltage VOUT across the variable capacitor C will be proportional to the cycle length, that is, VOUT_TEST/VOUT_REF=TTEST/TREF. Since TREF=N/FREF and TTEST=N/FTEST, it can be deduced that VOUT_TEST/VOUT_REF=FREF/FTEST. Therefore, the frequency to be measured FTEST can be expressed as: FTEST=FREF/(VOUT_TEST/VOUT_REF).

As shown in FIG. 3 , if necessary, in the monitoring mode, the operating frequency of the circuit under test 50 can be monitored in real time (as shown in period T7 ).

As can be seen from the above, in the present embodiment, in the calibration mode, the capacitance value of the variable capacitor C is determined. In the monitoring mode, the operating frequency of the circuit under test 50 can be detected.

FIG4 shows a flow chart of a frequency detection method according to an exemplary embodiment of the present invention. In step 410, a first reference voltage is compared with a node voltage, and a first comparison result is output. In step 420, a reference current is output according to the first comparison result, wherein the reference current is used to generate the node voltage, and an output current is output according to the reference current. In step 430, the variable capacitor is charged with the output current. In step 440, a second reference voltage is compared with a cross-voltage of the variable capacitor to generate a second comparison result. In step 450, a control signal is output according to the second comparison result to control a capacitance value of the variable capacitor and reset the cross-voltage of the variable capacitor. In step 460, in a calibration mode, a reference frequency is received, and in a plurality of calibration cycles, the output current charges the variable capacitor, and at the end of each of the calibration cycles, the cross-voltage of the variable capacitor is reset, and at the end of each of the calibration cycles, the control signal is controlled according to the second comparison result to control the capacitance value of the variable capacitor in the next calibration cycle. In step 470, after the calibration mode ends, a target capacitance value of the variable capacitor is determined. In step 480, in a monitoring mode, in a first monitoring cycle, the reference frequency is received, and at the end of the first monitoring cycle, the cross-voltage of the variable capacitor is measured as a first cross-voltage. In step 490, in a second monitoring cycle, the frequency to be measured provided by the circuit to be measured is received, and at the end of the second monitoring cycle, the cross-voltage of the variable capacitor is measured as a second cross-voltage, and the frequency to be measured is determined according to the reference frequency, the first cross-voltage and the second cross-voltage.

In addition, in the present embodiment, the first reference voltage VREF1 and the second reference voltage VREF2 may be in a voltage-dividing relationship.

The present embodiment discloses a frequency detection circuit and method that can automatically sense the operating frequency of a circuit, which is applicable to devices such as optical fiber transceivers that need to detect the operating frequency of a circuit. The present embodiment uses the basic principle that current multiplied by charging time equals capacitor voltage to perform a multi-cycle charging and discharging process on the variable capacitor, and obtains the operating frequency of the circuit to be tested according to pre-set specific conditions.

In summary, although the present invention has been disclosed by way of embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various modifications and alterations without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the following claims.

Claims (9)

1. A frequency detection circuit for detecting a frequency to be detected of a circuit to be detected, the frequency detection circuit comprising:

an error amplifier for comparing a first reference voltage with a node voltage and outputting a first comparison result;

A current mirror coupled to the error amplifier for outputting a reference current according to the first comparison result, wherein the reference current is used for generating the node voltage, and the current mirror outputs an output current according to the reference current;

A variable capacitor coupled to the current mirror, the output current of the current mirror charging the variable capacitor;

A comparator coupled to the variable capacitor for comparing a second reference voltage with a voltage across the variable capacitor to generate a second comparison result; and

The control circuit is coupled to the comparator and the variable capacitor, outputs a control signal according to the second comparison result of the comparator so as to control a capacitance value of the variable capacitor, resets the voltage across the variable capacitor, and receives a reference frequency and the frequency to be measured of the circuit to be measured;

Wherein,

In a calibration mode, the control circuit receives the reference frequency, the output current of the current mirror charges the variable capacitor in a plurality of calibration periods, the control circuit resets the voltage across the variable capacitor when each calibration period is finished, and the control circuit controls the control signal according to the second comparison result output by the comparator to control the capacitance value of the variable capacitor in the next calibration period when each calibration period is finished;

After the calibration mode is finished, the control circuit determines a target capacitance value of the variable capacitor;

In a monitoring mode, the control circuit receives the reference frequency in a first monitoring period, and measures the voltage across the variable capacitor as a first voltage across the variable capacitor at the end of the first monitoring period; and

In a second monitoring period, the control circuit receives the frequency to be detected provided by the circuit to be detected, and measures the voltage across the variable capacitor as a second voltage across the variable capacitor at the end of the second monitoring period, and the control circuit determines the frequency to be detected according to the reference frequency, the first voltage across the variable capacitor and the second voltage across the variable capacitor.

2. The frequency detection circuit of claim 1, further comprising:

the resistor is coupled to the current mirror, the reference current flows through the resistor, and a voltage across the resistor is the node voltage; and

And a switch coupled to the variable capacitor and the control circuit, wherein the control circuit outputs a reset signal to the switch to reset the voltage across the variable capacitor when each calibration period is completed.

3. The frequency detection circuit of claim 1, wherein, in the calibration mode,

At the end of each calibration period, if the voltage across the variable capacitor is higher than the second reference voltage, the control circuit increases the control signal to increase the capacitance value of the variable capacitor in the next calibration period; and

At the end of each calibration period, if the voltage across the variable capacitor is lower than the second reference voltage, the control circuit decreases the control signal to decrease the capacitance value of the variable capacitor in the next calibration period.

4. The frequency detection circuit of claim 1, wherein the first reference voltage and the second reference voltage are in a divided relationship.

5. The frequency detection circuit of claim 1, wherein the reference frequency is provided by the circuit under test or by an external reference signal source.

6. A frequency detection method for detecting a frequency to be detected of a circuit to be detected, the frequency detection method comprising:

Comparing a first reference voltage with a node voltage and outputting a first comparison result;

Outputting a reference current according to the first comparison result, wherein the reference current is used for generating the node voltage, and outputting an output current according to the reference current;

Charging a variable capacitance with the output current;

comparing a second reference voltage with a voltage across the variable capacitor to generate a second comparison result; and

Outputting a control signal according to the second comparison result to control a capacitance value of the variable capacitor and reset the voltage across the variable capacitor;

Wherein,

In a calibration mode, receiving a reference frequency, charging the variable capacitor by the output current in a plurality of calibration periods, resetting the voltage across the variable capacitor when each calibration period is finished, and controlling the control signal according to the second comparison result to control the capacitance value of the variable capacitor in a next calibration period when each calibration period is finished;

after the calibration mode is finished, determining a target capacitance value of the variable capacitor;

in a monitoring mode, the reference frequency is received in a first monitoring period, and the voltage across the variable capacitor is measured as a first voltage across the variable capacitor at the end of the first monitoring period; and

And in a second monitoring period, receiving the frequency to be detected provided by the circuit to be detected, and measuring the voltage across the variable capacitor to be a second voltage across the variable capacitor when the second monitoring period is finished, and determining the frequency to be detected according to the reference frequency, the first voltage across the variable capacitor and the second voltage across the variable capacitor.

7. The method of claim 6, wherein, in the calibration mode,

At the end of each calibration period, if the voltage across the variable capacitor is higher than the second reference voltage, increasing the control signal to increase the capacitance of the variable capacitor in the next calibration period; and

At the end of each calibration period, if the voltage across the variable capacitor is lower than the second reference voltage, the control signal is lowered to lower the capacitance value of the variable capacitor in the next calibration period.

8. The method of claim 6, wherein the first reference voltage and the second reference voltage are in a voltage division relationship.

9. The method of claim 6, wherein the reference frequency is provided by the circuit under test or by an external reference signal source.