KR101470627B1 - Display device and driving method thereof - Google Patents

Abstract

The present invention relates to a display device and a driving method thereof, and more particularly, to a data driving circuit for supplying a video data signal to data lines; A gate driving circuit for sequentially supplying gate pulses to the gate lines; A first pulse having a wide pulse width is generated at the beginning of each frame period and a second pulse having a pulse width narrower than that of the first pulse is repeatedly generated at a period of one horizontal period to generate the first pulse and the second pulse A controller for generating a first control signal including a first control signal; And a control signal generator for generating a second control signal for delaying the first control signal to control a shift operation of the gate drive circuit and a third control signal for starting operation of the gate drive circuit.

Description

DISPLAY DEVICE AND DRIVING METHOD THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display device and a driving method thereof for reducing a control signal input to a gate driving circuit.

The display device is applied to various information devices, office machines, and the like as a delivery medium of visual information. Cathode Ray Tube or CRT, which is the most widely used display device, has a problem in weight and volume. Many types of flat panel displays capable of overcoming the limitations of the cathode ray tube have been developed.

The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode (OLED) ). Among them, the liquid crystal display device can meet the light and small trend of electronic products, and the mass productivity is improved, and the cathode ray tube is rapidly replaced in many applications. Particularly, an active matrix type liquid crystal display device which drives a liquid crystal cell by using a thin film transistor (hereinafter referred to as "TFT") has an advantage of high image quality and low power consumption, With the achievements of securing and R & D, it is rapidly developing with the enlargement and high resolution.

The flat panel display is arranged such that the data lines and the scan lines are orthogonal and the pixels are arranged in a matrix form. In a liquid crystal display device and an organic light emitting diode device, a scan line is sometimes referred to as a gate line because a gate electrode of a TFT is connected to scan lines. A video data voltage to be displayed is supplied to the data lines and a scan pulse (or gate pulse) is sequentially supplied to the scan lines. The video data voltage is supplied to the pixels of the display line to which the scan pulse is supplied and the video data is displayed while all the display lines are sequentially scanned by the scan pulse.

A gate driving circuit (or a scan driving circuit) for supplying a scan pulse to scan lines of a flat panel display device usually includes a plurality of scan integrated circuits (hereinafter referred to as "IC"). Since each scan IC must sequentially output scan pulses, it basically includes a shift register and may include circuits and output buffers for adjusting the output voltage of the shift register according to the driving characteristics of the display panel. These gate driving circuits operate in response to many control signals generated from the timing controller. Hereinafter, the gate drive circuit of the flat panel display device will be described, focusing on the gate drive circuit of the liquid crystal display device.

1 shows a gate IC of a gate driving circuit applied to a liquid crystal display device. 2 shows a control signal for controlling the gate driving circuit and an output signal of the gate driving circuit.

1 and 2, a gate IC of a liquid crystal display includes a shift register 10, a level shifter 12, and a plurality of AND gates (hereinafter referred to as " gate ") connected between a shift register 10 and a level shifter 12 , "AND gate") 11.

The shift register 10 successively shifts a gate start pulse (GSP) according to a gate shift clock (GSC) using a plurality of D flip-flops depending thereon. Each of the AND gates 11 generates an output by logically multiplying the non-inverted output signal of the D-flip flop of the shift register 10 and the inverted signal of the gate output enable (GOE). The enable signal GOE which is the gate output is inverted by the inverter 13 and input to one input terminal of the AND gate 11. [ The level shifter 12 shifts the output voltage swing width of the AND gate 11 to a swing width capable of operating the TFT of the liquid crystal display panel. The output signals G1 to Gk of the level shifter 12 are sequentially supplied to k (k is an integer) gate lines.

In order to control the gate IC, the timing controller must generate at least a gate start pulse (GSP), a gate shift clock (GSC) and a gate output enable signal (GOE). Therefore, it is difficult to reduce the number of pins and the number of connectors of the connector and the cable for transmitting the control signal between the timing controller and the gate IC. Such a problem has been a stumbling block in solving the simplification of the driving circuit and the cost reduction in the liquid crystal display device as well as other flat panel display devices.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a display device and a driving method thereof for reducing a control signal input to a gate driving circuit.

A display device according to an embodiment of the present invention includes: a display panel in which data lines and gate lines are crossed and pixels are arranged in a matrix form; A data driving circuit for supplying a video data signal to the data lines; A gate driving circuit for sequentially supplying gate pulses to the gate lines; A first pulse having a wide pulse width is generated at the beginning of each frame period and a second pulse having a pulse width narrower than that of the first pulse is repeatedly generated at a period of one horizontal period to generate the first pulse and the second pulse A controller for generating a first control signal including a first control signal; And a control signal generator for generating a second control signal for delaying the first control signal to control a shift operation of the gate drive circuit and a third control signal for starting operation of the gate drive circuit.

A method of driving a display device according to an embodiment of the present invention includes generating a first pulse having a wide pulse width at the beginning of a frame period for each frame period and thereafter generating a second pulse having a narrower pulse width than the first pulse, Generating a first control signal including a first pulse and a second pulse, the first control signal occurring repeatedly in a cycle; And generating a second control signal for delaying the first control signal to control a shift operation of the gate drive circuit and a third control signal for starting operation of the gate drive circuit.

The display device and the driving method thereof according to the embodiment of the present invention minimize the gate control signal generated in the timing controller and delay the gate control signal to generate other gate control signals to thereby reduce the gate control signal input to the gate driving circuit . Furthermore, the present invention minimizes the number of pins and the number of connectors and cables for transmitting a control signal between the timing controller and the gate IC by minimizing the gate control signal generated from the timing controller.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 3 to 12. FIG.

Referring to FIG. 3, the liquid crystal display according to the first embodiment of the present invention includes a liquid crystal display panel 30, a timing controller 31, a data driving circuit 32, and a gate driving circuit 33. The data driving circuit 32 includes a plurality of source ICs. The gate drive circuit 33 includes a plurality of gate ICs 331 to 335.

In the liquid crystal display panel 30, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 30 includes m x n liquid crystal cells Clc arranged in a matrix form by an intersection structure of m data lines 34 and n gate lines 35.

Data lines 34, gate lines 35, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel 30. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 30, a black matrix, a color filter, and a common electrode 2 are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The IPS (In Plane Switching) mode and the FFS (Fringe Field Switching) Mode is formed on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving method. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 30, a polarizing plate is attached, and an alignment film for setting a pre-tilt angle of liquid crystal is formed at an interface with the liquid crystal.

The timing controller 31 receives the timing signals such as the vertical / horizontal synchronizing signals Vsync and Hsync, the data enable signal DE and the clock signal CLK and supplies them to the data driving circuit 32 and the gate driving circuit 33 And the control signals for controlling the operation timing of the control signal. These control signals include a gate timing control signal and a data timing control signal. Further, the timing controller 31 supplies digital video data (RGB) and black data to the data driving circuit 32.

The gate timing control signal generated by the timing controller 31 includes only the gate output enable signal GOE. On the other hand, in the conventional liquid crystal display device, the timing controller generates a gate start pulse (GSP), a gate shift clock signal (GSC), etc. in addition to the gate output enable signal GOE. The gate start pulse GSP and the gate shift clock signal GSC in the liquid crystal display according to the embodiment of the present invention are generated in the first gate IC 331 that outputs the gate pulses first, To 335). The gate start pulse GSP indicates the start line from which the scan is started so that the first gate pulse is generated from the first gate IC 331. [ The gate shift clock signal GSC is a clock signal for shifting the gate start pulse GSP. The shift register of the gate ICs 331 to 335 shifts the gate start pulse GSP at the rising edge of the gate shift clock signal GSC. The second to fifth gate ICs 332 to 335 receive the final stage output of the previous gate IC with a gate start pulse GSP to generate a first gate pulse. The gate output enable signal GOE is commonly input to the gate ICs 331 to 335. The gate ICs 331 to 335 output the gate pulse during the low logic period of the gate output enable signal GOE, that is, just after the polling time of the pulse until just before the rising time of the next pulse. The output of the gate ICs 331 to 335 is cut off during the high logic period of the gate output enable signal GOE.

The data timing control signal generated by the timing controller 31 includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable Signal (Source Output Enable (SOE)). The source start pulse (SSP) indicates the starting pixel on the line where data is to be displayed. The source sampling clock SSC indicates the latching operation of data in the data driving circuit 32 based on the rising or falling edge. The polarity control signal POL controls the polarity of the analog video data voltage output from the data driving circuit 32. [ The source output enable signal SOE controls the output of the source IC.

Each of the data drive ICs of the data driving circuit 32 includes a shift register, a latch, a digital-analog converter, an output buffer, and the like. The data driving circuit 32 latches the digital video data RGB under the control of the timing controller 31. The data driving circuit 32 supplies the charge sharing voltage to the data lines 34 in response to the source output enable signal SOE and outputs the digital video data RGB and the digital video data RGB in response to the polarity control signal POL. And converts the black data to an analog positive / negative gamma compensation voltage to generate positive / negative analog data voltages and supplies the voltages to the data lines 34. [

Each of the gate ICs 331 to 335 of the gate drive circuit 33 includes a GSP & GSC generator, a shift register, an AND gate array, a level shifter, and the like. These gate ICs 331 to 335 are connected to the gate output enable signal GOE generated by the timing controller 31 and the gate stator pulse GSP generated in the first gate IC 331, And sequentially supplies gate pulses to the gate lines 35 in response to the clock GSC.

4 shows the GOE generator of the timing controller 31 and its input signals. 5 shows a gate output enable signal GOE output from the GOE generator.

4 and 5, the GOE generator includes a first GOE generator 41, a second GOE generator 42, and an OR gate 43 (hereinafter referred to as "OR gate").

The first GOE generator 41 counts the data enable signal DE on the basis of the clock signal CLK and outputs a result of the count as shown in FIG. 5, the width of t2 smaller than the pulse width of the data enable signal DE Gt; pulses < / RTI > The data enable signal DE is generated in a period of one horizontal period (1H). Therefore, a pulse is generated in the output signal P1 of the first GOE generator 41 in one horizontal period (1H) period. The output signal P1 of the first GOE generator 41 is substantially the same as the gate output enable signal of the prior art.

The second GOE generator 42 receives the vertical synchronization signal Vsync and the clock signal CLK and counts the vertical synchronization signal Vsync on the basis of the clock signal CLK. A pulse having a wider pulse width than the output signal Pl of the second GOE generator 42 is regularly generated. The vertical synchronization signal Vsync is generated in a period of approximately one frame period. Therefore, in the output signal P2 of the second GOE generator 42, a pulse is generated once at the beginning of one frame period, and is generated at a period of one frame period. The pulse width at the output signal P2 of the second GOE generator 42 is generated at t1 (? 2 * t2). That is, the pulse width t1 of the output signal P2 output from the second GOE generator 42 is wider than the pulse width t2 of the first GOE generator 41.

The OR gate 43 generates a gate output enable signal GOE by performing an OR of the output signal P1 of the first GOE generator 41 and the output signal P2 of the second GOE generator 42. [ The gate output enable signal GOE generates a pulse S1 having a large pulse width initially in every frame period and thereafter pulses S2 having a relatively small pulse width are generated in one horizontal period period.

6 shows a GSP & GSC generator 60 embedded in each of the gate ICs 331 to 335. Fig. 7 shows the input / output waveforms of the GSP & GSC generator 60 and the gate pulses output from the first gate ICs 331 to 335.

Referring to FIGS. 6 and 7, the GSP & GSC generator 60 includes a delay unit 61 and a D flip-flop 62.

The delay unit 61 delays the gate output enable signal GOE from the timing controller 31 by using the first to third delay circuits 611 to 613 to generate the delay signals GOE1 to GOE3 do. The first delay circuit 611 delays the gate output enable signal GOE by t3 to generate the first delay signal GOE1. t3 is a time greater than 0 and less than t2. The first delay signal GOE1 is used as the gate shift clock GSC. Hereinafter, the first delay signal GOE1 will be referred to as a gate shift clock GSC. The second delay circuit 612 delays the gate shift clock GSC by t3 to generate the second delay signal GOE2. The third delay circuit 613 delays the second delay signal GOE2 by t3 to generate the third delay signal GOE3. Therefore, the gate shift clock GSC is delayed by t3 from the gate output enable signal GOE from the timing controller 31, and the second delay signal GOE2 is delayed from the gate shift clock GSC in phase This is as late as t3. The third delay signal GOE3 is delayed in phase by t3 as compared with the second delay signal GOE2.

Each of the delay circuits 611 to 613 of the delay unit 61 includes a plurality of inverter pairs. The delay time of the delay circuits 611 to 613 is adjustable according to the number of inverter pairs. For example, the larger the number of inverter pairs connected in series, the longer the delay time of the input signal. The delay circuits 611 to 613 are not only a pair of inverters, but also any known delay circuits are possible.

The D flip-flop 62 receives the gate output enable signal GOE from the timing controller 31 through its input terminal D. The third delay signal G3 is input to the clock terminal of the D flip-flop 62 and the enable signal EN is input to the enable terminal of the D flip-flop 62. [ This D flip-flop 62 is driven when the enable signal EN (H) of the high logic is input to the enable terminal, and outputs the gate output enable signal GOE at the rising edge of the third delay signal GOE3 And generates a gate start pulse GSP. Since the D flip-flop 62 generates a rising edge of the first pulse in the third delay signal GOE3 while maintaining the high logic period of the gate output enable signal GOE as shown in FIG. 7, the gate enable signal Since the gate output enable signal GOE at the rising edge of the second pulse in the third delay signal GOE3 maintains the low logic after generating the pulse of the gate start pulse GSP by outputting the high logic of the first delayed signal GOE Outputs low logic. Then, the D flip-flop 62 outputs the low logic because the high logic section of the gate output enable signal in the rising edge of the pulses after the second pulse in the third delay signal GOE3 does not overlap as shown in FIG. 7 , And generates a gate start pulse GSP again when the rising edge of the third delay signal GOE3 and the high logic section of the gate output enable signal GOE overlap at the beginning of the next frame period. And is disabled when the low logic disable signal EN (L) is input to the enable terminal of the D flip-flop 62 to not generate an output.

7, the shift register of the gate ICs 331 to 335 shifts the gate start pulse GSP generated in the GSP & GSC generator 60 of the first gate IC 331 to the rising edge of the gate shift clock GSC Respectively. The gate ICs 331 to 335 supply the output of the shift register to the level shifter during the low logic period of the gate output enable signal GOE. As a result, the gate ICs 331 to 335 sequentially output the gate pulses. G2 is a gate pulse supplied to the second gate line, G3 is a gate pulse supplied to the third gate line, G4 is a gate pulse supplied to the third gate line, A gate pulse supplied to the fourth gate line, and a gate pulse supplied to the fifth gate line, respectively. The configuration and operation of the gate ICs 331 to 335 will be described in detail with reference to FIG.

8 shows the first and second gate ICs 331 and 332 in detail.

8, the gate ICs 331 and 332 include an OR gate 84 for outputting a logical sum signal of the output from the GSP & GSC generator 60, the signal from the GSP & GSC generator 60 and the carry signal input terminal, A shift register 80, a level shifter 82 and a plurality of AND gates 81 connected between the shift register 80 and the level shifter 82.

The GSP & GSC generator 60 of the first gate IC 331 inputs the enable signal EN (H) of the high logic voltage to the enable terminal of the D flip-flop 62, 31 to delay the gate output enable signal GOE to generate the gate shift clock GSC and the gate start pulse GSP. On the other hand, since the GSP & GSC generator 60 embedded in the gate ICs after the second gate IC 332 inputs the disable signal of the low logic voltage to the enable terminal of the D flip-flop 62, Does not occur.

The carry signal input terminal EIO1 of the first gate IC 331 is connected to the base low voltage and receives the low logic voltage. A carry signal is input to the carry signal input terminal formed in the gate ICs after the second gate IC 332, which is connected to the first gate IC 331, from the last stage of the shift register of the previous gate IC. The OR gate 84 of the gate ICs 331 and 332 has a first input terminal connected to the carry signal input terminal, a second input terminal to which the output signal of the GSP & GSC generator 60 is inputted, And an output terminal connected to the input terminal D of the first D flip-flop of FIG. Since the OR gate 84 of the first gate IC 331 continuously receives the low logic voltage at the carry signal input terminal, the output of the GSP & GSC generator 60, that is, the gate start pulse GSP, To the first D-type flip flop. Since the carry signal transferred from the shift register of the first gate IC 331 is input to the carry signal input terminal of the OR gate 84 of the second gate IC 332 and the GSP & GSC generator 60 is disabled, The carry signal from the input terminal is supplied to the first D-type flip-flop of the shift register 80 as it is.

The shift register 80 of the first gate IC 331 outputs the output of the GSP & GSC generator 60 input through the OR gate 84, that is, the gate start pulse GSP) for each edge of the gate shift clock from the GSP & Accordingly, the shift register 80 of the first gate IC 331 sequentially generates the output through the output nodes between the D flip-flops. The AND gates 81 of the first gate IC 331 generate an AND output of the output of the shift register and the gate output enable signal GOE inverted by the inverter 83. [ Therefore, the level shifter 82 receives the output of the shift register 80 when the gate output enable signal GOE from the timing controller 31 is low logic. The level shifter 82 of the first gate IC 331 shifts the output voltage swing width of the AND gate 81 to a swing width at which the TFT of the liquid crystal display panel 30 can operate. Gate pulses G1 to Gk generated from the level shifter 82 of the first gate IC 331 are sequentially supplied to k gate lines.

The shift register 80 of the second gate IC 332 receives a carry signal from the first gate IC 331 input through the OR gate 84 using a plurality of D flip- The start pulse GSP is shifted for each edge of the gate shift clock from the GSP & Thus, the shift register 80 of the second gate IC 332 sequentially generates an output through the output nodes between the D flip-flops. The AND gates 81 of the second gate IC 332 generate a logical product output of the output of the shift register 80 and the gate output enable signal GOE inverted by the inverter 83. [ Therefore, the level shifter 82 receives the output of the shift register 80 when the gate output enable signal GOE from the timing controller 31 is low logic. The level shifter 82 of the second gate IC 332 shifts the output voltage swing width of the AND gate 81 to the swing width at which the TFT formed in the pixel array of the liquid crystal display panel 30 can operate. Gate pulses Gk + 1 to G2k generated from the level shifter 82 of the second gate IC 332 are sequentially supplied to k gate lines. The gate ICs after the second gate IC 332 have substantially the same circuit configuration as the second gate IC 332 and the operation thereof is also substantially the same as that of the second gate IC 332, .

Fig. 9 shows the connection relationship of the input / output terminals of the gate ICs 331 to 335 shown in Fig.

Referring to FIG. 9, a gate output enable signal GOE is commonly input from the timing controller 31 to the GOE input terminal of the gate ICs 331 to 335. 3

The first gate IC 331 starts to operate by the gate start pulse GSP outputted through the D flip-flop of the built-in GSP & GSC generator 60, so that the EIO1 input terminal is supplied with a base voltage (GND) is supplied. Since the second to fifth gate ICs 312 to 315 receive the carry signal transmitted from the gate IC of the preceding stage as a gate start pulse and receive a carry signal from the CAR output terminal of the previous gate IC, .

Since the first gate IC 331 generates a gate start pulse through the D flip-flop of the built-in GSP & GSC generator 60, the power supply voltage VCCI of the high logic voltage is applied to the EN input terminal thereof. Since the D flip flop of the embedded GSP & GSC generator 60 must be disabled in the second to fifth gate ICs 312 to 315, the ground voltage GND is supplied to the EN input terminal thereof through the pull-down resistor R .

10 to 12 show a liquid crystal display device according to a second embodiment of the present invention.

Referring to FIG. 10, a liquid crystal display device according to a second embodiment of the present invention includes a liquid crystal display panel 30, a timing controller 31, a data driving circuit 32, and a gate driving circuit 103. The liquid crystal display panel 30, the timing controller 31, and the data driving circuit 32 are substantially the same as those of the first embodiment described above, and thus a detailed description thereof will be omitted.

In the gate drive circuit 103, the first gate IC 331 includes a GSP & GSC generator, a shift register, an AND gate array, a level shifter, and the like as shown in Figs. 6 and 7 as in the first embodiment . The first gate IC 331 delays the gate enable signal GOE from the timing controller 31 to generate a gate start pulse GSP and a gate shift clock GSC and outputs the control signals GSP and GSC, To the second gate IC 1032 as a carry signal.

Unlike the first embodiment, the second to fifth gate ICs 1032 to 1035 include a shift register, an AND gate array, a level shifter, and the like without a GSP & GSC generator. Therefore, the second to fifth gate ICs 1032 to 1035 are substantially the same as the gate drive IC of the prior art, so that they can be compatible with the gate drive IC of the prior art. The second gate IC 1032 receives the gate start pulse GSP and the gate shift clock GSC generated from the first gate IC 331 and shifts the gate start pulse GSP in accordance with the gate shift clock GSC. Thereby sequentially generating gate pulses. The third gate IC 1033 shifts the gate start pulse GSP transferred from the second gate IC 1032 according to the gate shift clock GSC from the first gate IC 331 to sequentially generate gate pulses do. The fourth gate IC 1034 shifts the gate start pulse GSP transferred from the third gate IC 1033 according to the gate shift clock GSC from the first gate IC 331 to sequentially generate gate pulses do. The fifth gate IC 1035 shifts the gate start pulse GSP transferred from the fourth gate IC 1034 in accordance with the gate shift clock GSC from the first gate IC 331 to sequentially generate gate pulses do. The gate ICs 331, 1032 to 1035 supply gate pulses to the gate lines during the low logic period of the gate output enable signal GOE.

4 and 5, the timing controller 31 generates pulses having a wide pulse width initially in every frame period using the GOE generator, and thereafter generates pulses having relatively small pulse widths in one horizontal period period. The output signal of the timing controller 31 generated in this manner controls the output of the gate ICs 331 and 1032 to 1035 and outputs a gate output enable signal GSP serving as a reference signal of the gate shift clock GSC Signal GOE.

11 shows the first and second gate ICs 331 and 1032 shown in FIG. 10 in detail. Since the third to fifth gate ICs 1033 to 1035 have substantially the same configuration as the second gate IC 1032, a detailed description thereof will be omitted.

11, the first gate IC 331 includes an OR gate 84 for outputting a logical sum signal of the output of the GSP & GSC generator 60, the output of the GSP & GSC generator 60 and the signal from the carry signal input terminal, And a plurality of AND gates 81 connected between the shift register 80 and the level shifter 82. The AND gate 81 is connected to the AND gate 81, The second gate IC 1032 includes a shift register 110, a level shifter 112 and a plurality of AND gates 111 connected between the shift register 110 and the level shifter 112. The second to fifth gate ICs 1032 to 1035 do not need the GSP & GSC generator 60 and the OR gate 84. [

Since the GSP & GSC generator 60 of the first gate IC 331 receives the enable signal EN (H) of the high logic voltage at the enable terminal of the D flip-flop 62, And delays the gate output enable signal GOE to generate a gate shift clock GSC and a gate start pulse GSP. The carry signal input terminal EIO1 of the first gate IC 331 is connected to the base low voltage and receives the low logic voltage. A carry signal is input from the last stage of the shift register of the previous gate IC to the carry signal input terminal formed in the gate ICs after the second gate IC 1032 which is connected to the first gate IC 331. Since the OR gate 84 of the first gate IC 331 continuously receives the low logic voltage at the carry signal input terminal, the output of the GSP & GSC generator 60, that is, the gate start pulse GSP, To the first D-type flip flop. The shift register 80 of the first gate IC 331 outputs the output of the GSP & GSC generator 60 input through the OR gate 84, that is, the gate start pulse GSP) for each edge of the gate shift clock from the GSP & Accordingly, the shift register 80 of the first gate IC 331 sequentially generates the output through the output nodes between the D flip-flops. The AND gates 81 of the first gate IC 331 generate an AND output of the output of the shift register and the gate output enable signal GOE inverted by the inverter 83. [ The level shifter 82 of the first gate IC 331 receives the output of the shift register 80 when the gate output enable signal GOE from the timing controller 31 is low logic. The level shifter 82 of the first gate IC 331 shifts the output voltage swing width of the AND gate 81 to a swing width capable of operating the TFT of the liquid crystal display panel. Gate pulses G1 to Gk generated from the level shifter 82 of the first gate IC 331 are sequentially supplied to k gate lines.

The shift register 110 of the second gate IC 1032 shifts the carry signal from the first gate IC 331, that is, the gate start pulse GSP, to the first gate IC 331 by using a plurality of D- Shifted every edge of the gate shift clock inputted from the IC 331. [ Thus, the shift register 110 of the second gate IC 1032 sequentially generates output through the output nodes between the D flip-flops. The AND gates 111 of the second gate IC 1032 generate an AND output of the output of the shift register and the gate output enable signal GOE inverted by the inverter. The level shifter 112 of the second gate IC 1032 receives the output of the shift register 110 when the gate output enable signal GOE from the timing controller 31 is low logic. The level shifter 112 of the second gate IC 1032 shifts the output voltage swing width of the AND gate 111 to a swing width at which the TFT of the liquid crystal display panel 30 can operate. Gate pulses Gk + 1 to G2k generated from the level shifter 112 of the second gate IC 1032 are sequentially supplied to k gate lines.

12 shows the connection relationship of the input / output terminals of the gate ICs 331 to 1035 shown in FIG.

Referring to FIG. 12, a gate output enable signal GOE is commonly input from the timing controller 31 to GOE input terminals of the gate ICs 331 and 1032 to 1035.

The first gate IC 331 starts to operate by the gate start pulse GSP outputted through the D flip-flop of the built-in GSP & GSC generator 60, so that the EIO1 input terminal is supplied with a base voltage (GND) is supplied. Since the second to fifth gate ICs 1032 to 1035 receive the carry signal transmitted from the gate IC of the preceding stage as a gate start pulse and receive a carry signal from the CAR output terminal of the preceding gate IC, .

Since the first gate IC 331 generates a gate start pulse through the D flip-flop of the built-in GSP & GSC generator 60, the power supply voltage VCCI of the high logic voltage is applied to the EN input terminal thereof. Since the second to fifth gate ICs 1032 to 1035 do not need the GSP & GSC generator 60, an EN input terminal is not required.

The second to fifth gate ICs 1032 to 1035 receive the gate shift clock GSC generated from the GSP & GSC generator 60 of the first gate IC 331 through the GSC input terminal.

In the liquid crystal display according to another embodiment of the present invention, the GSP & GSC generator 60 is separated from the gate ICs in the first embodiment, and the output terminals of the GSP & GSC generator 60 are controlled by corresponding gate ICs Connect to the signal input terminal. In this case, the gate drive ICs may be compatible with the gate ICs of the prior art. In the liquid crystal display according to another embodiment of the present invention, the GSP & GSC generator 60 is separated from the first gate IC in the second embodiment described above, and the output terminals of the GSP & Connect to the control signal input terminal.

The present invention can be applied to other flat panel display devices such as a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode (OLED) device. The present invention is also applicable to a gate drive circuit (or a scan drive circuit)

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a block diagram showing a gate IC of a gate driving circuit applied to a liquid crystal display device;

2 is a waveform diagram showing a control signal for controlling the gate drive circuit and an output signal of the gate drive circuit;

3 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention;

4 is a circuit diagram and waveform diagram showing the GOE generator of the timing controller shown in FIG. 3 and its input signals.

5 is a waveform diagram showing a gate output enable signal outputted from the GOE generator shown in Fig.

6 is a circuit diagram showing a GSP & GSC generator of the gate IC shown in FIG. 3;

FIG. 7 is a waveform diagram showing input / output waveforms of the GSP & GSC generator shown in FIG. 6 and gate pulses output from the first gate IC; FIG.

FIG. 8 is a circuit diagram showing details of the first and second gate ICs shown in FIG. 3; FIG.

FIG. 9 is a view showing input / output terminals of the gate ICs shown in FIG. 3; FIG.

10 is a block diagram showing a liquid crystal display device according to a second embodiment of the present invention.

11 is a circuit diagram showing details of the first and second gate ICs shown in FIG. 10;

12 is a view showing the connection relationship of the input / output terminals of the gate ICs shown in FIG. 10;

Description of the Related Art

31: timing controller 32: data driving circuit

33, 103: gate drive circuits 331 to 335, 1032 to 1035: gate IC

41: first GOE generator 42: second GOE generator

43, 84: OR gate 60: GSP & GSC generator

61: Delay unit 62: D flip-flop

80: Shift register 81: AND gate

82: Level shifter

Claims (9)

A display panel in which data lines and gate lines are crossed and pixels are arranged in a matrix form; A data driving circuit for supplying a video data signal to the data lines; A gate driving circuit for sequentially supplying gate pulses to the gate lines; A first pulse having a wide pulse width is generated at the beginning of each frame period and a second pulse having a pulse width narrower than that of the first pulse is repeatedly generated at a period of one horizontal period to generate the first pulse and the second pulse A controller for generating a first control signal including a first control signal; And And a control signal generator for generating a second control signal for delaying the first control signal to control the shift operation of the gate drive circuit and a third control signal for starting the operation of the gate drive circuit Device. delete The method according to claim 1, Wherein the control signal generator comprises: A delay unit delaying the first control signal to generate the second control signal, and delaying the second control signal to generate a delay signal; And And a D-flip-flop which is enabled by an enable signal and outputs the first control signal at the rising edge of the delay signal to generate the third control signal and is disabled in response to the disable signal. / RTI > The method of claim 3, Wherein the gate drive circuit includes a plurality of gate ICs, Each of the gate ICs includes: A shift register for sequentially shifting the third control signal according to the second control signal; A level shifter for converting a swing width of an output signal of the shift register; An AND gate for supplying an output signal of the shift register to the level shifter in response to the first control signal; And And an OR gate for outputting an output signal of said control signal generating section and said third control signal inputted from a shift register of said front gate IC, and outputting the resultant. 5. The method of claim 4, Wherein the control signal generating unit is incorporated in each of the driving circuits. The method of claim 3, Wherein the gate drive circuit includes a plurality of gate ICs, Each of the gate ICs includes: A shift register for sequentially shifting the third control signal according to the second control signal; A level shifter for converting a swing width of an output signal of the shift register; And And an AND gate for supplying an output signal of the shift register to the level shifter in response to the first control signal. The method according to claim 6, Wherein the control signal generator is incorporated only in the first driver IC that outputs the gate pulse first among the gate ICs. 8. The method of claim 7, Wherein the gate ICs which are connected to the first gate IC and sequentially generate the gate pulses following the first gate IC sequentially receive the second and third control signals from the control signal generator built in the first gate IC And receives a signal to operate. A display panel in which data lines and gate lines intersect and pixels are arranged in a matrix form, a data driving circuit for supplying a video data signal to the data lines, and a gate driving circuit for sequentially supplying gate pulses to the gate lines The method of driving a display device according to claim 1, A first pulse having a wide pulse width is generated at the beginning of each frame period and a second pulse having a pulse width narrower than that of the first pulse is repeatedly generated at a period of one horizontal period to generate the first pulse and the second pulse Generating a first control signal including a first control signal; And And generating a second control signal for delaying the first control signal to control the shift operation of the gate drive circuit and a third control signal for starting the operation of the gate drive circuit Driving method.

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