KR101411745B1 - Organic Light Emitting Display and Method of Driving the same - Google Patents

Abstract

A first switching transistor driven in response to a scan signal; a capacitor receiving a data signal as the first switching transistor is driven and storing a data signal as a data voltage; A display unit having a plurality of sub-pixels including a driving transistor to drive the driving transistor, an organic light emitting diode to emit light when the driving transistor is driven to emit light, and a second switching transistor to diode-connect the driving transistor in response to the control signal; A scan driver for supplying a scan signal and a control signal; And a data driver for supplying a data signal to the scan driver, wherein the scan driver diode-couples the drive transistor within a blank time during which the organic light emitting diode does not emit light, An electroluminescent display device is provided.

Organic electroluminescent display, threshold voltage, compensation

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting display,

The present invention relates to an organic light emitting display and a driving method thereof.

An organic electroluminescent device used in an organic electroluminescent display device is a self-luminous device in which a light emitting layer is formed between two electrodes located on a substrate.

In addition, the organic light emitting display device may include a top emission type, a bottom emission type, or a dual emission type depending on a direction in which light is emitted. It is divided into a passive matrix and an active matrix depending on the driving method.

In such an organic light emitting display, when a scan signal, a data signal, a power supply, and the like are supplied to a plurality of subpixels arranged in a matrix form, the selected subpixel emits light to display an image.

Meanwhile, in such an organic light emitting display device, the driving transistor must be continuously turned on in order for the organic light emitting diode to emit light. Therefore, when the driving signal is continuously supplied to the gate of the driving transistor, there is a problem that the threshold voltage Vth increases and the current flow decreases with time. If such a phenomenon continues, the performance of the driving transistor deteriorates and the organic light emitting diode can not be normally emitted, and the lifetime of the panel is also shortened and reliability is lowered.

SUMMARY OF THE INVENTION An object of the present invention is to provide an organic light emitting display device and a method of driving the same, which can improve the luminance unevenness between subpixels.

According to an aspect of the present invention, there is provided a data driver comprising: a first switching transistor driven in response to a scan signal; a capacitor receiving a data signal as the first switching transistor is driven and storing a data signal as a data voltage; And a second switching transistor for diode-connecting the driving transistor in response to a control signal, the driving transistor being driven in response to a data voltage, the organic light emitting diode being supplied with power when the driving transistor is driven, ; A scan driver for supplying a scan signal and a control signal; And a data driver for supplying a data signal to the scan driver, wherein the scan driver diode-couples the drive transistor within a blank time during which the organic light emitting diode does not emit light, An electroluminescent display device is provided.

The blank time may correspond to the sum of the width of the front polarity and vertical synchronizing signal of the vertical synchronizing signal supplied from the outside to the scan driver and the back porch of the vertical synchronizing signal.

The ground voltage supplied to the subpixel in the blank time can be switched from a level corresponding to the power supply voltage to a level corresponding to the ground voltage.

The sub-pixel includes a first switching transistor whose one end is connected to the data line to which the gate is connected to the scan wiring to which the scan signal is supplied and the data line to which the data signal is supplied, and the other end is connected to the first node A second switching transistor having a gate connected to a signal line to which a control signal is supplied, one end connected to the first node and the other end connected to the second node, a first switching transistor connected to the first power supply line, And a driving transistor having a gate connected to the first node, a first end connected to the second node, and a second end connected to the second power supply line.

The voltage applied to the second node before the second switching transistor is turned on may be set at a power supply voltage level at which the voltage supplied through the second power supply line is supplied through the first power supply line.

The voltage applied to the first node during the period in which the second switching transistor is turned on and the driving transistor is diode-connected may be sampled to the threshold voltage of the driving transistor as the voltage supplied to the second power supply wiring is switched to the ground voltage.

The transistors included in the sub-pixel may be N-type transistors.

According to another aspect of the present invention, there is provided a method of driving an organic light emitting diode (OLED) including a first switching transistor, a second switching transistor, a capacitor, a driving transistor, and an organic light emitting diode Connecting a driving transistor to a diode and setting a threshold voltage of the driving transistor; And causing the organic light emitting diode to emit light by using a driving transistor that turns on the first switching transistor, stores a data voltage corresponding to the sum of the threshold voltage and the data signal, and drives the data transistor in response to the data voltage stored in the capacitor. A method of driving an electroluminescent display device is provided.

The blank time can correspond to the sum of the widths of the front posit and vertical synchronous signals of the vertical synchronous signal and the back porch of the vertical synchronous signal.

The ground voltage supplied to the subpixel in the blank time can be switched from a level corresponding to the power supply voltage to a level corresponding to the ground voltage.

It is an object of the present invention to provide an organic light emitting display device and a method of driving the same, which can improve a phenomenon in which luminance between subpixels appears unevenly.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic plan view of an organic light emitting display according to an embodiment of the present invention.

As shown in FIG. 1, an organic light emitting display may include a display unit 120 in which a plurality of subpixels P are located. Since the plurality of sub-pixels P are vulnerable to moisture or oxygen, the display portion 120 can be sealed by the sealing substrate.

Meanwhile, a plurality of sub-pixels P may be driven by the driving units 140 and 150 to display an image.

The driving units 140 and 150 may include a scan driver 140 for supplying a scan signal to a plurality of subpixels P and a data driver 150 for supplying data signals to a plurality of subpixels P. [

The scan driver 140 receives a vertical synchronization signal Vsync from the outside and generates a scan signal and a control signal to supply the plurality of subpixels P with reference to the vertical synchronization signal Vsync. The scan driver 140 includes a shift register 141 receiving a vertical synchronization signal Vsync, a level shifter 142 for adjusting the level of a signal received from the shift register 141, a level shifter 142, And an output buffer 143 for outputting a signal received from the output buffer 143. However, the present invention is not limited thereto.

The data driver 150 may supply the horizontal synchronization signal Hsync and the video signals R, G, and B from the outside and generate a data signal or the like with reference to the horizontal synchronization signal Hsync. The data driver 150 includes a shift register 151 receiving a horizontal synchronizing signal Hsync and a latch for storing the video data signals R, G, and B referring to signals received from the shift register 151 And an output buffer 153 for converting signals received from the latch 152 and image data signals R, G, and B into analog signals (or digital signals) and outputting the signals.

A detailed description of subpixels that receive a scan signal, a control signal, and a data signal from the scan driver and the data driver, respectively, will be described in detail below with reference to the drawings.

Hereinafter, the structure of subpixels will be described in more detail with reference to cross-sectional illustrations of the subpixels described above.

2A is an exemplary cross-sectional view of the subpixel shown in FIG.

As shown in FIG. 2A, a buffer layer 105 is located on a substrate 110. Buffer layer 105 is selectively using, for example, to form to protect the transistor to be formed in a subsequent process from impurities such as alkali ions leaked from the substrate 110, silicon oxide (SiO _2), silicon nitride (SiNx) .

Here, the substrate 110 may be glass, plastic or metal.

The semiconductor layer 111 is located on the buffer layer 105. The semiconductor layer 111 may include amorphous silicon or crystallized polycrystalline silicon.

In addition, the semiconductor layer 111 may include a source region and a drain region including p-type or n-type impurities, and may include a channel region other than the source region and the drain region.

A first insulating film 115, which may be a gate insulating film, is located on the semiconductor layer 111. The first insulating film 115 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

The gate electrode 120c may be positioned at a position corresponding to a certain region of the semiconductor layer 111 located on the first insulating film 115, that is, a channel region when impurities are implanted. The scan line 120a and the capacitor lower electrode 120b may be positioned on the same layer as the gate electrode 120c.

The gate electrode 120c is formed of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper One or an alloy thereof.

The gate electrode 120c may be formed of a material selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy of any one selected from the above.

Further, the gate electrode 120c may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

The scan line 120a may be formed of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper One or an alloy thereof. The scan line 120a may be formed of one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy of any one selected from the above. Further, the scan line 120a may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

The second insulating film 125 to be an interlayer insulating film is positioned on the substrate 110 including the scan wiring 120a, the capacitor lower electrode 120b and the gate electrode 120c. The second insulating layer 125 may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof.

The contact holes 130b and 130c for exposing a part of the semiconductor layer 111 are located in the second insulating film 125 and the first insulating film 115. [

Drain electrodes and source electrodes 140c and 140d electrically connected to the semiconductor layer 111 through the contact holes 130b and 130c passing through the second insulating layer 125 and the first insulating layer 115 are formed in the pixel region Located.

The drain electrode and the source electrode 140c and 140d may be formed of a single layer or multiple layers and may be formed of a single layer of molybdenum (Mo), aluminum (Al), chromium (Cr) , Gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). When the drain electrode and the source electrodes 140c and 140d are multi-layered, a triple layer of molybdenum / aluminum-neodymium, molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum may be used.

The data line 140a, the capacitor upper electrode 140b, and the power supply line 140e may be positioned on the same layer as the drain electrode and the source electrodes 140c and 140d.

The data wiring 140a and the power supply wiring 140e located in the non-pixel region may be formed of a single layer or multiple layers. When the data wiring 140a and the power wiring 140e are single layers, the data wiring 140a and the power wiring 140e may be made of molybdenum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

When the data wiring 140a and the power wiring 140e are multilayered, they may be formed of a triple layer of molybdenum / aluminum-neodymium, molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum.

In addition, the data wiring 140a and the power wiring 140e may be formed of a triple layer of molybdenum / aluminum-neodymium / molybdenum.

The third insulating film 145 is located on the data wiring 140a, the capacitor upper electrode 140b, the drain and source electrodes 140c and 140d and the power supply wiring 140e. The third insulating film 145 may be a planarizing film for alleviating the step difference of the lower structure and may be formed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, And may be formed of an inorganic material such as SOG (spin on glass) which is cured and then cured.

Alternatively, the third insulating layer 145 may be a passivation layer, or may be a silicon nitride layer (SiNx), a silicon oxide layer (SiOx), or a multilayer thereof.

A via hole 165 is formed in the third insulating film 145 to expose either the drain or source electrode 140c or 140d and the drain and source electrodes 140c and 140c are formed on the third insulating film 145 through a via hole 165. [ And 140d, which are electrically connected to one another.

The first electrode 160 may be an anode, and may be a transparent electrode or a reflective electrode. Here, the first electrode 160 may be a transparent electrode when the structure of the organic light emitting display device is a back surface or a double-sided light emission. The first electrode 160 may be a transparent electrode such as indium tin oxide (ITO), indium zinc oxide (IZO) It can be either.

In addition, the first electrode 160 may be a reflective electrode when the structure of the organic light emitting display device is a front emission type, and aluminum (Al), silver (Ag), or the like may be formed under the layer of any one of ITO, IZO, Nickel (Ni), and in addition, a reflective layer may be included between two layers of any one of ITO, IZO, and ZnO.

A fourth insulating layer 155 is disposed on the first electrode 160 to insulate the first electrodes adjacent to the first electrode 160 and include an opening 175 for exposing a portion of the first electrode 160. The light emitting layer 170 is located on the first electrode 160 exposed by the opening 175.

The second electrode 180 is located on the light emitting layer 170. The second electrode 180 may be a cathode electrode and may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function.

Here, the second electrode 180 may be formed to have a thickness thin enough to transmit light when the organic light emitting display device has a front or both-side light emitting structure, and when the organic light emitting display device has a back light emitting structure, It can be formed thick enough to reflect light.

The above-described embodiments are based on a total of seven masks, namely, a semiconductor layer, a gate electrode (including a scan wiring and a capacitor lower electrode), contact holes, a source electrode and a drain electrode (including a data wiring, a power wiring, A structure of an organic light emitting display device using a mask in a process of forming a via hole, a first electrode and an opening has been described as an example.

Hereinafter, an embodiment in which an organic electroluminescent display device is formed using a total of five masks is disclosed. The description of the parts overlapping with those described above in the embodiments described below will be omitted.

2B is another cross-sectional exemplary view of the subpixel shown in FIG.

2B, the buffer layer 105 is located on the substrate 110, and the semiconductor layer 111 is located on the buffer layer 105. [ The first insulating film 115 is positioned on the semiconductor layer 111 and the gate electrode 120c, the capacitor lower electrode 120b and the scan wiring 120a are positioned on the first insulating film 115. [ And the second insulating film 125 is located on the gate electrode 120c.

The first electrode 160 is positioned on the second insulating layer 125 and the contact holes 130b and 130c are exposed to expose the semiconductor layer 111. [ The first electrode 160 and the contact holes 130b and 130c may be formed at the same time.

A source electrode 140d, a drain electrode 140c, a data wiring 140a, a capacitor upper electrode 140b, and a power supply wiring 140e are located on the second insulating film 125. [ Here, a part of the drain electrode 140c may be located on the first electrode 160. [

A third insulating layer 145 which may be a pixel defining layer or a bank layer is located on the substrate 110 on which the structure is formed and an opening 175 for exposing the first electrode 160 is formed on the third insulating layer 145 do. The light emitting layer 170 is located on the first electrode 160 exposed by the opening 175 and the second electrode 180 is located on the light emitting layer 170.

(Including a scan line and a capacitor lower electrode), a first electrode (including a contact hole), a source / drain electrode (including a data line, a power supply line, and a capacitor upper electrode) And the organic electroluminescent display device using a mask in the process of forming the openings has an advantage that the number of masks is reduced and the manufacturing cost is reduced and the efficiency of mass production is increased.

Meanwhile, the organic light emitting display device may have various methods in implementing a color image, and an implementation method thereof will be described with reference to FIGS. 3A to 3B.

3A and 3B are diagrams illustrating an example of implementing a color image of a subpixel.

3A shows a color image realization method in which a red light emitting layer 170R, a green light emitting layer 170G, and a blue light emitting layer 170B separately emit red light, green light, and blue light, respectively .

As shown in FIG. 3A, red light, green light, and blue light are provided from the respective light emitting layers 170R, 170G, and 170B, respectively, so that red light / green light / blue light are mixed to display a color image.

Here, an electron transport layer (ETL), a hole transport layer (HTL), and the like may be further included at the top and bottom of each of the emission layers 170R, 170G, and 170B.

The color image realization method shown in FIG. 3B is a color image realization method including a white light emitting layer 270W, a red color filter 290R, a green color filter 290G, and a blue color filter 290B.

The white light provided from the white light emitting layer 270W is transmitted through the red color filter 290R, the green color filter 290G and the blue color filter 290B while the red light / green light / Respectively, so that a color image can be displayed.

Here, the upper and lower portions of each white light emitting layer 270W may further include an electron transport layer (ETL), a hole transport layer (HTL), and the like, and the arrangement and structure thereof may be variously modified.

Here, the bottom emission structure is shown and described in FIGS. 3A and 3B, but the present invention is not limited thereto, and various modifications can be made to the arrangement and structure of the top emission structure.

In addition, although two types of driving methods have been shown and described with respect to the color image realizing method, the present invention is not limited thereto, and various modifications are possible as needed.

4 is a hierarchical structure diagram of an organic light emitting diode included in a subpixel.

Referring to FIG. 4, an organic light emitting diode according to an exemplary embodiment of the present invention includes a substrate 110, a first electrode 160 disposed on the substrate 110, a first electrode 160 disposed on the first electrode 160, A second electrode 180 located on the hole injection layer 171, the hole transport layer 172, the light emitting layer 170, the electron transport layer 173, the electron injection layer 174 and the electron injection layer 174 .

First, a hole injection layer 171 is formed on the first electrode 160. The hole injection layer 171 may function to smoothly inject holes from the first electrode 160 into the light emitting layer 170 and may be formed of at least one selected from the group consisting of CuPc (cupper phthalocyanine), PEDOT (poly (3,4) -ethylenedioxythiophene ), PANI (polyaniline) and NPD (N, N-dinaphthyl-N, N'-diphenyl benzidine).

The hole injection layer 171 described above can be formed by an evaporation method or a spin coating method.

The hole transport layer 172 plays a role of facilitating the transport of holes and may be formed by using NPD (N, N-dinaphthyl-N, N'-diphenyl benzidine), TPD (N, N'- , N'-bis- (phenyl) -benzidine), s-TAD and MTDATA (4,4 ', 4 "-tris (N-3-methylphenyl-N-phenylamino) But is not limited thereto.

The hole transport layer 172 can be formed by evaporation or spin coating. The light emitting layer 170 described above may be formed of a material that emits red, green, blue, and white light, and may be formed using phosphorescent or fluorescent materials.

When the light emitting layer 170 is red, it includes a host material containing carbazole biphenyl (CBP) or mCP (1,3-bis (carbazol-9-yl) wherein the dopant comprises at least one selected from the group consisting of iridium, iridium, PQIr (acac) (bis (1-phenylquinoline) acetylacetonate iridium), PQIr (tris (1-phenylquinoline) iridium) and PtOEP (octaethylporphyrin platinum) Or PBD: Eu (DBM) 3 (Phen) or Perylene. However, the present invention is not limited thereto.

When the light emitting layer 170 is green, it may be made of a phosphorescent material including a dopant material including a host material including CBP or mCP and containing Ir (ppy) 3 (fac tris (2-phenylpyridine) iridium) Alternatively, it may be made of a fluorescent material including Alq3 (tris (8-hydroxyquinolino) aluminum), but is not limited thereto.

When the light emitting layer 170 is blue, it may include a phosphorescent material including a dopant material including (4,6-F2ppy) 2Irpic including a host material including CBP or mCP.

Alternatively, the fluorescent material may include any one selected from the group consisting of spiro-DPVBi, spiro-6P, distyrylbenzene (DSB), distyrylarylene (DSA), PFO polymer, and PPV polymer. It is not limited.

Here, the electron transport layer 173 serves to smooth the transport of electrons, and may be any one or more selected from the group consisting of Alq3 (tris (8-hydroxyquinolino) aluminum), PBD, TAZ, spiro-PBD, BAlq and SAlq But is not limited thereto.

The electron transporting layer 173 can be formed by an evaporation method or a spin coating method. The electron transport layer 173 may also prevent holes injected from the first electrode from passing through the light emitting layer to the second electrode. That is, it may serve as a hole blocking layer and may serve to efficiently combine holes and electrons in the light emitting layer.

Here, the electron injection layer 174 serves to smooth the injection of electrons, and may use Alq3 (tris (8-hydroxyquinolino) aluminum), PBD, TAZ, spiro-PBD, BAlq or SAlq .

The electron injection layer 174 may be formed by vacuum evaporation of organic and inorganic materials forming the electron injection layer.

Here, the hole injection layer 171 or the electron injection layer 174 may further include an inorganic material, and the inorganic material may further include a metal compound. The metal compound may include an alkali metal or an alkaline earth metal. Metal compound including an alkali metal or alkaline earth metal LiQ, LiF, NaF, KF, RbF, CsF, FrF, BeF 2, MgF 2, CaF 2, SrF 2, BaF any one selected from the group consisting of ₂ and RaF ₂ or more But is not limited thereto.

That is, the inorganic material in the electron injection layer 174 facilitates hopping of electrons injected from the second electrode 180 into the light emitting layer 170, thereby balancing the holes and electrons injected into the light emitting layer, Can be improved.

The inorganic material in the hole injection layer 171 reduces the mobility of holes injected from the first electrode 160 into the light emitting layer 170 so as to balance the holes and electrons injected into the light emitting layer 170, .

Here, the present invention is not limited to FIG. 4, and at least one of the electron injection layer 174, the electron transport layer 173, the hole transport layer 172, and the hole injection layer 171 may be omitted.

Meanwhile, the method of manufacturing a sub-pixel, the structure, and the material of the organic light emitting display according to an embodiment of the present invention are not limited thereto.

Hereinafter, an organic light emitting display according to an embodiment of the present invention will be described in more detail with reference to a circuit configuration diagram of subpixels. However, for ease of explanation, FIG. 1 will be referred to together.

5 is a circuit block diagram of a subpixel according to an embodiment of the present invention.

As shown in FIG. 5, a subpixel according to an exemplary embodiment of the present invention includes a scan line SCAN to which a scan signal is supplied, a gate connected to the scan line SCAN, and a data line DATA to which a data signal is supplied. 1 switching transistor S1. The first switching transistor S1 may include a capacitor Cst, one end of which is connected to the other end of the first switching transistor S1 and the other end of which is connected to the first node (node A). The second switching transistor S2 includes a gate connected to the signal line CTL to which the control signal is supplied, one end connected to the node A, and the other end connected to the node B . The organic light emitting diode D may further include a first electrode connected to the first power supply line VDD and a second electrode connected to the second node B, The driving transistor T1 may include a gate connected to the first node (node A), one end connected to the second node (node B), and the other end connected to the second power supply line (VSS).

The circuit configuration of such a subpixel is implemented by three transistors, one capacitor, and one organic light emitting diode to illustrate an example of the embodiment, but is not limited thereto. In addition, to explain an example of the embodiment, the transistors S1, S2, and T1 included in the sub-pixel are implemented as N-type, but the present invention is not limited thereto.

The scan driver 140 is connected to the driving transistor T1 by diode connection during a blank time in which the organic light emitting diode D included in the subpixel does not emit light to set the threshold voltage of the driving transistor T1. (S2).

Here, the blank time is the sum of the width of the front porch of the vertical synchronizing signal Vsync supplied to the scan driver 140, the width of the vertical synchronizing signal Vsync and the width of the back electrode of the vertical synchronizing signal Vsync Porch) can be accommodated.

If the threshold voltage of the driving transistor Tl included in the subpixel is set within the blanking time at which the organic light emitting diode D does not emit light, It is possible to increase the light emitting time than to set the threshold voltage of the transistor T1.

On the other hand, when setting the threshold voltage of the driving transistor Tl within the blank time, the voltage supplied to the second power supply line VSS of the subpixel changes from the power supply voltage level supplied to the first power supply line VDD to the ground voltage Level.

This will be described in more detail as follows.

First, before the second switching transistor S2 is turned on, the ground voltage supplied through the second power supply line VSS is raised to a level corresponding to the power supply voltage supplied through the first power supply line VDD, Lt; / RTI > That is, the second power supply line VSS is pulled up to the power supply voltage level supplied to the first power supply line VDD. Then, the voltage of the second node (node B) may be set to a high voltage corresponding to a difference between the power supply voltage supplied through the first power supply line VDD and the threshold voltage of the organic light emitting diode D .

Thereafter, the voltage of the second power supply line VSS, which is pulled up to the power supply voltage, is switched to the ground voltage in the section where the second switching transistor S2 is turned on and the driving transistor T1 is diode-connected. Then, the high voltage applied to the second node (node B) is dischanned through the other end (source) through one end (drain) of the driving transistor Tl. At this time, the gate voltage of the driving transistor Tl is lower than the threshold voltage The first node (node A) can be programmed to the threshold voltage of the driving transistor Tl.

In this manner, the process of setting the threshold voltage of the driving transistor Tl may be performed by all the subpixels simultaneously or may be performed for each subpixel.

Thereafter, when the first switching transistor S1 is turned on, the capacitor Cst can store the data voltage. However, a scan signal for turning on the first switching transistor S1 may be sequentially supplied to all the sub-pixels.

In this process, the first node (node A) can have a voltage of "Vdata + Vth" which is the sum of the data signal and the threshold voltage of the driving transistor Tl due to the coupling phenomenon of the capacitor Cst. Therefore, the data voltage stored in the capacitor Cst may be "Vdata + Vth ".

According to this driving method, the amount of current flowing in the driving transistor Tl can be set independently of the threshold voltage of the driving transistor Tl. The current equation of the driving transistor Tl can be expressed by the following equation Lt; / RTI >

In Equation 1 above, I _{ds_ DRTFT} : The drain current of the driving transistor T1 and the current flowing through the source, I _OLED : Current flowing through the organic light emitting diode (D), V _GS : It may be a voltage across the second power supply line (VSS): threshold voltage, V _DATA of the drive transistor (T1):: data voltage, VSS driving transistor voltage across the gate and the source of the (T1), V _th.

According to Equation 1, since the current flowing through the organic light emitting diode D can maintain a constant value regardless of the threshold voltage change of the driving transistor Tl, the luminance of the display portion of the organic light emitting display device can be uniformly improved .

Hereinafter, the driving method of the organic light emitting display device described above will be described in more detail. However, in order to facilitate the understanding of the explanation, the above-mentioned FIG. 1 and FIG. 5 will be referred to together.

6 is a diagram illustrating an example of a driving waveform according to an embodiment of the present invention.

As shown in FIG. 6, the driving method according to an embodiment of the present invention can be roughly divided into a blank time and an emission time.

First, the second switching transistor S2 is turned on within a blank time during which the organic light emitting diode D of the subpixel does not emit light, and the driving transistor T1 is diode-connected to set the threshold voltage of the driving transistor T1 to Perform the setting step.

Here, the blank time refers to the width of the front porch and the vertical synchronization signal Vsync of the vertical synchronization signal Vsync supplied to the scan driver, and the width of the vertical synchronization signal Vsync, It is possible to cope with the combined width of back porch.

The ground voltage Vss supplied to the second power supply line VSS is set to the power supply voltage Vdd supplied to the first power supply line VDD in order to set the threshold voltage of the driving transistor Tl included in the sub- To a level corresponding to the ground voltage Vss.

That is, the second power supply line VSS is pulled up to the level of the power supply voltage Vdd supplied to the first power supply line VDD. Then, the voltage of the second node (node B) is set to a high voltage corresponding to the difference between the power supply voltage Vdd supplied through the first power supply line VDD and the threshold voltage of the organic light emitting diode D .

Then, within the blank time, the scan driver may supply the control signal Ctl to the second switching transistor S2. Thus, when the driving transistor Tl is diode-connected, the voltage of the second power supply line VSS which has been pulled up to the power supply voltage Vdd is switched to the ground voltage Vss. Then, the high voltage applied to the second node (node B) is dischanned through the other end (source) through one end (drain) of the driving transistor Tl. At this time, the gate voltage of the driving transistor Tl is lower than the threshold voltage The first node (node A) can be programmed to the threshold voltage of the driving transistor Tl.

Here, the process of setting the threshold voltage of the driving transistor Tl may be performed by all the subpixels simultaneously or may be performed on a subpixel-by-subpixel basis.

Next, a driving transistor Tl which turns on the first switching transistor S1, stores a data voltage corresponding to the sum of the threshold voltage and the data signal in the capacitor Cst, and drives the data voltage corresponding to the data voltage stored in the capacitor Cst The organic light emitting diode D is caused to emit light.

The scan driver may sequentially supply the scan signals Scan1..sub.scan [n] to each subpixel to turn on the first switching transistor S1 included in the subpixel, The data signal Data1.Data [n] can be supplied to the sub-pixel in which the transistor S1 is turned on.

When the first switching transistor S1 is turned on, the capacitor Cst may receive the data signal Data1 through the turned-on first switching transistor S1. At this time, the first node (node A) can have a voltage of "Vdata + Vth" which is the sum of the data signal Data1 and the threshold voltage of the driving transistor T1 due to the coupling phenomenon of the capacitor Cst. Therefore, the data voltage stored in the capacitor Cst may be "Vdata + Vth ".

According to such a driving method, the amount of current flowing in the driving transistor Tl can be set independently of the threshold voltage of the driving transistor Tl. If the current equation of the driving transistor Tl is expressed by the mathematical expression, Can be described as Equation (1).

Thereafter, when the turned-on first switching transistor S1 is turned off, the driving transistor T1 can be driven in response to the data voltage stored in the capacitor Cst. Then, the organic light emitting diode D can emit light corresponding to the voltage applied to the gate of the driving transistor Tl.

If the threshold voltage of the driving transistor Tl included in the subpixel is set within the blanking time at which the organic light emitting diode D does not emit light as described above, The light emitting time can be increased more than the threshold voltage of the driving transistor T1.

The present invention is capable of programming the threshold voltages of all the subpixels of the display unit within a blank time of one frame period with a simple structure of subpixels including three transistors and one capacitor. The gate voltage of the driving transistor may have a value obtained by summing the data voltage and the threshold voltage by supplying the data signal through the normal supply of the scan signal. By this process, the sub-pixel included in the organic light emitting display device can improve the luminance unbalance problem due to the change of the threshold voltage of the driving transistor.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

1 is a schematic plan view of an organic light emitting display according to an embodiment of the present invention.

FIG. 2A is an exemplary cross-sectional view of the subpixel shown in FIG. 1; FIG.

FIG. 2B is another cross-sectional exemplary view of the subpixel shown in FIG. 1; FIG.

FIGS. 3A and 3B illustrate a color image of a subpixel; FIG.

4 is a hierarchical view of an organic light emitting diode included in a subpixel;

5 is a circuit configuration diagram of a subpixel according to an embodiment of the present invention.

6 is a diagram illustrating a driving waveform according to an embodiment of the present invention;

DESCRIPTION OF THE REFERENCE NUMERALS

120: Display section 140:

150: Data driver P: Sub-pixel

Claims (10)

A first switching transistor driven in response to a scan signal; a capacitor receiving a data signal as the first switching transistor is driven and storing the data signal as a data voltage; And a second switching transistor for diode-connecting the driving transistor in response to a control signal, wherein the driving transistor includes a plurality of sub-pixels, ; A scan driver for supplying the scan signal and the control signal; And And a data driver for supplying the data signal, Wherein the scan driver supplies the control signal to the second switching transistor to diode-couple the driving transistor within a blank time during which the organic light emitting diode does not emit light to set a threshold voltage of the driving transistor, Wherein a voltage supplied to a second power supply line connected to the other end of the driving transistor switches from a power supply voltage level to a ground voltage level within the blank time. The method according to claim 1, The blank time may be, And a width of a front porch and a vertical synchronizing signal of a vertical synchronizing signal supplied from the outside to the scan driver and a back porch of a vertical synchronizing signal. delete The method according to claim 1, The sub- A first switching transistor having a gate connected to a scan wiring to which the scan signal is supplied and a first end connected to a data line to which the data signal is supplied, and a second switching transistor having one end connected to the other end of the first switching transistor, The second switching transistor having a gate connected to a signal line to which the control signal is supplied and a first end connected to the first node and a second end connected to a second node; And the driving transistor including a gate connected to the first node, one end connected to the second node, and the other end connected to the second power supply line, the organic light emitting diode being connected to the second node, And the organic electroluminescent display device. 5. The method of claim 4, Wherein the voltage across the second node before the second switching transistor is turned on, And switches the ground voltage to the power supply voltage level for a predetermined period of time. 6. The method of claim 5, Wherein the voltage applied to the first node during a period in which the second switching transistor is turned on and the driving transistor is diode- Wherein the threshold voltage of the driving transistor is sampled as the voltage supplied to the second power supply wiring is switched from the power supply voltage to the ground voltage. The method according to claim 1, The transistors included in the sub- N-type transistor. A first switching transistor; a capacitor for receiving the data signal as the first switching transistor is driven and storing the data signal as a data voltage; a driving transistor driven in response to the data voltage stored in the capacitor; An organic light emitting diode (OLED) display device having a display unit including a plurality of subpixels including an organic light emitting diode that emits light by being powered by a transistor and a second switching transistor that diodes the driving transistor in response to a control signal, , The method comprising: Turning on the second switching transistor in a blank time during which the organic light emitting diode does not emit light to diode-connect the driving transistor and set a threshold voltage of the driving transistor; And The organic light emitting diode is driven to emit light by using the driving transistor which turns on the first switching transistor, stores the data voltage corresponding to the sum of the threshold voltage and the data signal in the capacitor, and drives the data voltage corresponding to the data voltage stored in the capacitor. The method comprising the steps of: 9. The method of claim 8, The blank time may be, Wherein a width of a front porch and a vertical synchronizing signal of a vertical synchronizing signal and a back porch of a vertical synchronizing signal are combined. 9. The method of claim 8, Wherein a voltage supplied to a second power supply line connected to the other end of the driving transistor is switched from a power supply voltage level to a ground voltage level within the blank time.

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