KR101374105B1 - Thin Film Transistor Substrate And Manufacturing Method Thereof - Google Patents

Abstract

The present invention relates to a thin film transistor substrate and a method of manufacturing the same that can improve aperture ratio and reduce cost.

A thin film transistor substrate according to an embodiment of the present invention includes a gate line formed on the substrate; A data line crossing the gate line and a gate insulating layer therebetween to form a sub pixel region; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor and formed in the sub pixel area; A common electrode forming a horizontal electric field with the pixel electrode; A common line connected to the common electrode to supply a common voltage to the common electrode; And a storage capacitor formed adjacent to the data line in a direction parallel to the data line to maintain the pixel signal charged in the pixel electrode.

Description

Thin Film Transistor Substrate And Manufacturing Method Thereof {Thin Film Transistor Substrate And Manufacturing Method Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate applied to a display element and a method of manufacturing the same, and more particularly, to a thin film transistor substrate and a method of manufacturing the same, which can improve aperture ratio and reduce cost.

The liquid crystal display device displays an image by adjusting the light transmittance of liquid crystal having dielectric anisotropy using an electric field. Such a liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

Among the liquid crystal display devices, the horizontal field type liquid crystal display device drives the liquid crystal in the in-plane switch mode by a horizontal electric field between the pixel electrode and the common electrode arranged side by side on the lower substrate.

Specifically, as shown in FIG. 1, the horizontal field application type liquid crystal display includes gate lines 10, data lines 20 crossing the gate lines 10 to provide a sub pixel region, and a gate. A common line 26 parallel to the line 10, a thin film transistor 70 formed at an intersection of the gate line 10 and the data lines 20, and a pixel connected to the thin film transistor 70. The electrode 22, the common electrode 26 forming a horizontal electric field with the pixel electrode 22, and the storage capacitor C which prevents the fluctuation | variation of the pixel signal charged in the pixel electrode 22 are provided.

The storage capacitor C is formed by overlapping the storage line 74 parallel to the gate line 10 and the drain electrode of the thin film transistor 70 with at least one insulating layer therebetween.

The storage line 74 is formed of the same metal as the gate line 10 and adjacent to the gate line 10. The storage line 74 and the gate line 10 should be spaced apart from each other in order to prevent shorting of the adjacent storage line 74 and the gate line 10. The aperture ratio of the sub pixel region is reduced by the distance, and the aperture ratio of the sub pixel region is reduced by the area of the storage line 74 occupied in the sub pixel region.

In order to prevent the aperture ratio from decreasing, the passivation layer protecting the thin film transistor 70 is formed of an organic insulating material such as photo acryl. Since the passivation layer formed of the organic insulating material has a small dielectric constant, the data line 20 and the common electrode 46 may be formed to overlap each other with the passivation layer interposed therebetween, thereby increasing the aperture ratio of the sub pixel region. However, organic insulating materials such as photoacryl have a problem that the price of the organic insulating material is about 16 times higher than that of the inorganic insulating material, and the rework process is impossible due to defects generated during the coating process and the patterning process.

In addition, the conventional storage line 74 is formed in parallel with the gate line 10. In this case, as the liquid crystal display moves toward the larger screen, the length of the gate line 10 becomes longer, and the storage line 74 also becomes longer. The resistance value of the storage line 74 is increased by the length of the storage line 74, so that the storage voltage or the common voltage supplied through the storage line 74 varies depending on the location. In addition, a storage voltage or a common voltage supplied through the storage line 74 by a parasitic capacitor formed between the conventional storage line 74 and the data line 20 receives the pixel signal supplied through the data line 20. Swing along. Accordingly, there is a problem that the storage voltage or the common voltage supplied through the storage line 74 is unstable.

In order to solve the above problems, the present invention is to provide a thin film transistor substrate and a method of manufacturing the same that can improve the aperture ratio without increasing the cost and can also reduce the cost.

A thin film transistor substrate according to an embodiment of the present invention for achieving the above object is a gate line formed on the substrate; A data line crossing the gate line and a gate insulating layer therebetween to form a sub pixel region; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor and formed in the sub pixel area; A common electrode forming a horizontal electric field with the pixel electrode; A common line connected to the common electrode to supply a common voltage to the common electrode; And a storage capacitor formed adjacent to the data line in a direction parallel to the data line to maintain the pixel signal charged in the pixel electrode.

In order to achieve the above technical problem, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of forming a thin film transistor connected to a gate line and a data line to form a sub pixel region by crossing the gate insulating film between the substrate; Wow; Forming a pixel electrode connected to the thin film transistor in the sub pixel area; Forming a common electrode in the sub-pixel region that forms a horizontal electric field with the pixel electrode and is supplied with a common voltage through a common line; And forming a storage capacitor adjacent to the data line in a direction parallel to the data line to maintain the pixel signal charged in the pixel electrode.

The thin film transistor substrate and the manufacturing method thereof according to the present invention have the following effects.

First, the thin film transistor substrate according to the present invention increases the capacitance of the entire storage capacitor by forming the storage capacitor using at least one of a common electrode adjacent to the data line and a common line parallel to the data line. As a result, the area of the storage electrode included in the storage capacitor can be reduced, and the aperture ratio can be improved without using an organic insulating material such as photoacryl. The non-use of organic insulating materials can reduce costs and reduce yields due to organic insulating materials.

Second, in the thin film transistor substrate according to the present invention, data lines of adjacent subpixels are formed adjacent to each other, and different data lines and corresponding subpixels share one common line, thereby increasing the aperture ratio by about 18 to 20% or more. Done. As the aperture ratio is improved, the number of backlights can be reduced, and the brightness enhancing film can be removed, thereby reducing costs.

Third, in the thin film transistor substrate according to the present invention, a common supply line is formed to be parallel to a data line having a length shorter than that of a gate line, which becomes longer as the liquid crystal display device moves toward a large screen. That is, when the liquid crystal display is a 16: 9 wide screen, the length of the data line corresponds to 9/16 times the gate line, so that the common supply line parallel to the data line is 9/16 compared to the common line parallel to the conventional gate line. As can reduce the line resistance. Accordingly, it is possible to reduce the RC delay composed of the product of the parasitic capacitor and the line resistance. In addition, since the thin film transistor substrate according to the present invention does not require a separate storage line, a parasitic capacitor between the conventional storage line and the data line is not formed. Accordingly, fluctuations in the common voltage due to line resistance and parasitic capacitors can be prevented, so that the common voltage is uniformly distributed throughout the panel, thereby preventing deterioration of image quality such as afterimage and horizontal crosstalk.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

2 is a plan view illustrating a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 3 illustrates the thin film transistor substrate illustrated in FIG. 2 as follows: I1-I1 ', I2-I2', I3-I3 ', I4-. Sectional drawing cut along the line I4 '.

2 and 3 include a thin film transistor 130 connected to each of the gate line 102 and the data line 104, a pixel electrode 122 formed in a sub pixel region having an intersecting structure, and a thin film transistor 130. And a common electrode 124 forming a horizontal electric field with the pixel electrode 122, and first and second storage capacitors Cst1 and Cst2 for stably maintaining the pixel signal charged in the pixel electrode 122. .

The data line 104 is formed to cross the gate line 102 and supplies a pixel signal to the source electrode 108 of the thin film transistor 130. The distance L between the data line 104 and the common electrode 124 located on both sides of the data line 104 should be maintained at the same interval as in the prior art, for example, 12 to 14 μm.

The gate line 102 supplies a scan signal to the gate electrode 106 of the thin film transistor 130. The step causing portion 117 is formed at the intersection of the gate line 102 and the data line 104. The step causing portion 117 is a structure in which the active layer 114 and the ohmic contact layer 116 are stacked on the gate insulating layer 112, and increases the separation distance between the data line 104 and the gate line 102. Capacitive values of the parasitic capacitors between the two lines 102 and 104, which are inversely proportional to the separation distance between the two lines 102 and 104, are reduced to prevent coupling between the scan signal and the pixel signal. In addition, when the common line 126 is formed as a gate metal layer on the lower substrate 101, the step induction unit 117 is also formed at an intersection area between the common line 126 and the data line 104. Since the step inducing unit 117 increases the separation distance between the common line 126 and the data line 104, the coupling phenomenon between the common voltage and the pixel signal is prevented.

The thin film transistor 130 causes a pixel signal supplied to the data line 104 to be charged and held in the pixel electrode 122 in response to a scan signal supplied to the gate line 102. The thin film transistor 130 includes a gate electrode 106, a source electrode 108, a drain electrode 110, an active layer 114, and an ohmic contact layer 116.

The gate electrode 106 is connected to the gate line 102 so that a scan signal from the gate line 102 is supplied. The source electrode 108 is connected to the data line 104 so that the pixel signal from the data line 104 is supplied. The drain electrode 110 is formed to face the source electrode 108 with the channel portion of the active layer 114 interposed therebetween and supplies a pixel signal from the data line 104 to the pixel electrode 122. The active layer 114 overlaps the gate electrode 106 with the gate insulating film 112 interposed therebetween to form a channel portion between the source and drain electrodes 108 and 110. The ohmic contact layer 116 is formed on the active layer 114 between the source electrode 108 and the drain electrode 110 and the active layer 114, The ohmic contact layer 116 serves to reduce electrical contact resistance between each of the source and drain electrodes 108 and 110 and the active layer 114.

The pixel electrode 122 is connected to the drain electrode 110 of the thin film transistor 130 through the pixel contact hole 120. Accordingly, the pixel electrode 122 is supplied with the pixel signal from the data line 104 through the thin film transistor 130. [ The pixel electrode 122 includes a finger portion 122A parallel to the data line 104, a first horizontal portion 122B parallel to the gate line 102, and a second horizontal portion overlapping the common line 126 ( 122C).

The common electrode 124 is formed of the same material on the same plane as the pixel electrode 122 or of a different material or the same material on a plane different from the pixel electrode 122. In the first embodiment of the present invention, a case in which the common electrode 124 and the pixel electrode 122 are formed on the protective film 118 as a transparent conductive film will be described as an example. The common electrode 124 is connected through a common contact hole 128 and a common line 126 formed of a gate metal layer on a substrate to supply a common voltage through the common line 126. The common electrode 124 positioned on both sides of each of the sub-pixels of the common electrode 124 and adjacent to the data line 104 shields the pixel signal from the data line 104 to prevent the data line 104 and the pixel electrode 122. ) To prevent coupling phenomenon.

The common electrode 124 is formed to be parallel to the finger portion 122A of the pixel electrode 122. Accordingly, a horizontal electric field is formed between the pixel electrode 122 supplied with the pixel signal and the common electrode 124 supplied with the common voltage. The horizontal electric field causes liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate to rotate by dielectric anisotropy. In addition, the light transmittance through the sub-pixel region varies according to the degree of rotation of the liquid crystal molecules, thereby realizing an image.

The first and second storage capacitors Cst1 and Cst2 can stably maintain the pixel signal charged in the pixel electrode 122 until the next signal is charged.

The first storage capacitor Cst1 overlaps the second storage electrode 134 connected to the common line 126 with the first storage electrode 132 connected to the pixel electrode 122 interposed with the gate insulating layer 112 therebetween. It is formed.

The first storage electrode 132 is formed as a gate metal layer on the lower substrate 101 and passes through the storage contact hole 136 through the gate insulating layer 112 and the passivation layer 118. ) Is connected. The first storage electrode 132 completely overlaps the common electrode 124 with a narrower width than the common electrode 124 positioned at both sides of each pixel, that is, the common electrode 124 positioned at both sides of the data line 104. Is formed. Accordingly, the first storage electrode 132 to which the pixel signal is supplied is shielded by the common electrode 124, thereby preventing a coupling phenomenon between the first storage electrode 132 and the data line 104. In addition, since the first storage electrode 132 is formed in parallel with the data line 104, the first storage electrode 132 is longer than the storage electrode formed in parallel with the conventional gate line. Accordingly, the total area of the first storage electrode 132 is increased compared to the prior art, thereby increasing the capacity value of the first storage capacitor formed by the first storage electrode 132.

The second storage electrode 134 is formed to overlap the common electrode 124 positioned at both sides of each sub pixel, that is, the common electrode 124 adjacent to the data line 104. The second storage electrode 134 is formed of a data metal layer on the gate insulating layer 112 and passes through the common contact hole 128 through the gate insulating layer 112 and the passivation layer 118. 124 is connected.

The second storage capacitor Cst2 is formed by overlapping the common line 126 and the second horizontal portion 122C of the pixel electrode 122 with the gate insulating layer 112 and the passivation layer 118 interposed therebetween.

As described above, the thin film transistor substrate according to the first embodiment of the present invention forms the first storage capacitor Cst1 by using the common electrodes 124 positioned at both sides of the data line 104 to shield the pixel signal. The first storage capacitor Cst1 increases the area of the storage capacitor of each subpixel, thereby increasing the capacity value of the entire storage capacitor of each pixel. Accordingly, if the capacitance value of the storage capacitor is formed in the same manner as in the related art, the area of the first and second storage electrodes 132 and 134 can be reduced, thereby improving the aperture ratio. As the aperture ratio is improved, it is not necessary to use expensive photo acrylic, the number of backlights can be reduced, and the brightness enhancement film (DBEF) can be removed, thereby reducing costs. In addition, since the thin film transistor substrate according to the first embodiment of the present invention forms the first and second storage capacitors Cst1 and Cst2 without a storage line, the parasitic capacitor between the storage line and the data line is not formed. Accordingly, the thin film transistor substrate according to the first embodiment of the present invention can prevent variations in common voltages due to parasitic capacitors, and thus common voltages are uniformly distributed throughout the panel, thereby preventing deterioration of image quality such as afterimages and horizontal crosstalk. .

4A and 4B illustrate a plan view and a cross-sectional view for describing a method of manufacturing a gate metal pattern in a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

A gate metal pattern including a gate line 102, a gate electrode 106, a first storage electrode 132, and a common line 126 is formed on the lower substrate 101.

Specifically, a gate metal layer is formed on the lower substrate 101 through a deposition method such as a sputtering method. As the gate metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, Mo-Ti alloy, etc. is used as a single layer or a double layer or more is laminated using the metal. It is used as a structure. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process to form a gate metal pattern including the gate line 102, the gate electrode 106, the first storage electrode 132, and the common line 126.

5A and 5B illustrate a plan view and a cross-sectional view for describing a method of manufacturing a semiconductor pattern in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

The gate insulating layer 112 is formed on the lower substrate 101 on which the gate metal pattern is formed, and the semiconductor pattern 115 including the active layer 114 and the ohmic contact layer 116 and the step causing portion 117 are formed thereon. Is formed.

Specifically, the gate insulating layer 112, the amorphous silicon layer, and the amorphous silicon layer doped with impurities (n + or p +) are sequentially formed on the lower substrate 101 on which the gate metal pattern is formed. The amorphous silicon layer and the amorphous silicon layer doped with impurities (n + or p +) are patterned by a photolithography process and an etching process to cause the semiconductor pattern 115 and the step of forming the active layer 114 and the ohmic contact layer 116. The part 117 is formed.

6A and 6B illustrate a plan view and a cross-sectional view for describing a method of manufacturing a data metal pattern in a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

A data metal pattern including the data line 104, the source electrode 108, the drain electrode 110, and the second storage electrode 134 is formed on the lower substrate 101 on which the semiconductor pattern and the step inducing portion are formed.

In detail, the data metal layer is formed on the lower substrate 101 on which the semiconductor pattern and the step inducing part are formed. The data metal layer is patterned by a photolithography process and an etching process to form a data metal pattern including the data line 104, the source electrode 108, the drain electrode 110, and the second storage electrode 134. Subsequently, the active layer 114 is exposed by removing the ohmic contact layer 116 exposed between the source electrode 108 and the drain electrode 118 using the source electrode 108 and the drain electrode 110 as a mask.

7A and 7B are a plan view and a cross-sectional view illustrating a method of manufacturing a protective film in a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention.

The passivation layer 118 including the pixel contact hole 120, the storage contact hole 136, and the common contact hole 128 is formed on the lower substrate on which the data metal pattern is formed.

Specifically, the protective film 118 is formed on the gate insulating film 112 on which the data metal pattern is formed by a method such as CVD or PECVD. As the protective film 118, an inorganic insulating material such as a gate insulating film 112 formed by a method such as CVD or PECVD is used. The passivation layer 118 is patterned by a photolithography process and an etching process to form the pixel contact hole 120, the storage contact hole 136, and the common contact hole 128.

The pixel contact hole 120 penetrates the passivation layer 118 to expose the drain electrode 110, and the storage contact hole 136 and the common contact hole 128 each pass through the gate insulating layer 112 and the passivation layer 118. The first storage electrode 132 and the common line 126 are exposed.

8A and 8B illustrate a plan view and a cross-sectional view for describing a method of manufacturing a transparent conductive pattern in a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

A transparent conductive pattern including the pixel electrode 122 and the common electrode 124 is formed on the lower substrate 101 on which the passivation layer 118 is formed.

Specifically, a transparent conductive film is formed on the lower substrate 101 on which the protective film 118 is formed through a deposition method such as a sputtering method. As the transparent conductive film, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), SnO ₂ , amorphous-indium tin oxide (a-ITO) . Subsequently, the transparent conductive film is patterned by a photolithography process and an etching process to form a transparent conductive pattern including the pixel electrode 122 and the common electrode 124. In addition to the transparent conductive film, the pixel electrode 122 and the common electrode 124 may be formed of a single layer of a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, Mo-Ti alloy, or the like. Alternatively, the metal may be formed in a structure in which two or more layers are laminated.

Meanwhile, the thin film transistor substrate according to the present invention has been described using 5 masks for forming each of the gate metal pattern, the semiconductor pattern, the data metal pattern, the passivation layer, and the transparent conductive pattern as an example. 4 masks or less can be formed.

9 is a plan view illustrating a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIG. 10 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 9 taken along lines II1-II1 'and II2-II2'. to be.

9 and 10 except that the thin film transistor substrate shown in FIGS. 2 and 3 has a larger distance between the data line 104 and the second storage electrode 134 than the thin film transistor substrate illustrated in FIGS. With the same components. Accordingly, detailed description of the same constituent elements will be omitted.

The first storage capacitor Cst1 overlaps the second storage electrode 134 connected to the pixel electrode 122 with the first storage electrode 132 connected to the common electrode 124 interposed with the gate insulating layer 112 therebetween. It is formed.

The first storage electrode 132 is formed to overlap the common electrode 124 positioned at both sides of each sub-pixel, that is, the common electrode 124 positioned at both sides of the data line 104. The first storage electrode 132 is formed as a gate metal layer on the lower substrate 101 and extends from the common line 126. The common line 126 is connected to the common electrode 124 through the common contact hole 128 that passes through the gate insulating layer 112 and the passivation layer 118.

The second storage electrode 134 is formed of a data metal layer on the gate insulating layer 112. The second storage electrode 134 adjacent to the data line 104 of the corresponding sub pixel extends from the drain electrode 110, and the second storage electrode 134 adjacent to the data line 104 of the adjacent sub pixel is formed of a passivation layer. It is connected to the first horizontal portion 122B of the pixel electrode 122 through the storage contact hole 136 penetrating 118.

The second storage electrode 134 has a narrower width than that of the common electrode 124 positioned at both sides of each sub-pixel, that is, the common electrode 124 and the second storage electrode 132 adjacent to the data line 104. And overlap with 124. In this case, the separation distance D2 between the second storage electrode 134 and the data line 104 is the separation distance D1 between the second storage electrode 134 and the data line 104 illustrated in FIGS. 2 and 3. Greater than That is, the separation distance between the second storage electrode 134 and the data line 104 is longer than the separation distance between the first storage electrode 132 and the data line 104. Accordingly, a short failure between the second storage electrode 134 and the data line 104 formed on the gate insulating layer 112 can be prevented, and the coupling phenomenon between the second storage electrode 134 and the data line 104 can be prevented. Can also be minimized.

As described above, in the thin film transistor substrate according to the second embodiment of the present invention, the capacitance value of the entire storage capacitor of each sub-pixel is increased by the first storage capacitor Cst1. Accordingly, if the capacitance value of the storage capacitor is formed in the same manner as in the related art, the area of the first and second storage electrodes 132 and 134 can be reduced, thereby improving the aperture ratio. As the aperture ratio is improved, it is not necessary to use expensive photo acrylic, the number of backlights can be reduced, and the brightness enhancing film can be removed, thereby reducing costs. In addition, since the thin film transistor substrate according to the second embodiment of the present invention does not have a storage line, a parasitic capacitor between the conventional storage line and the data line is not formed. Accordingly, the thin film transistor substrate according to the second embodiment of the present invention can prevent the variation of the pixel signal and the common voltage from the data line 104 due to the parasitic capacitor.

11A to 15B illustrate a plan view and a cross-sectional view for describing a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention.

First, a gate metal layer is entirely deposited on the lower substrate 101, and then the gate metal layer is patterned to form the gate line 102, the gate electrode 106, and the first storage electrode (as shown in FIGS. 11A and 11B). A gate metal pattern is formed that includes 132 and common line 126.

Subsequently, a gate insulating layer 112 is formed on the lower substrate 101 on which the gate metal pattern is formed, and an amorphous silicon layer and an amorphous silicon layer doped with impurities (n + or p +) are sequentially formed thereon. The amorphous silicon layer and the amorphous silicon layer doped with impurities (n + or p +) are patterned by a photolithography process and an etching process to cause the semiconductor pattern 115 and the step of forming the active layer 114 and the ohmic contact layer 116. The part 117 is formed.

Subsequently, a data metal layer is formed on the lower substrate 101 on which the semiconductor pattern 115 and the step causing portion 117 are formed. The data metal layer is patterned by a photolithography process and an etching process to form a data metal pattern including the data line 104, the source electrode 108, the drain electrode 110, and the second storage electrode 134. Subsequently, the active layer 114 is exposed by removing the ohmic contact layer 116 exposed between the source electrode 108 and the drain electrode 118 using the source electrode 108 and the drain electrode 110 as a mask.

Subsequently, a passivation layer 118 is formed on the lower substrate 101 on which the data metal pattern is formed. The passivation layer 118 is patterned by a photolithography process and an etching process to form the pixel contact hole 120, the storage contact hole 136, and the common contact hole 128.

Subsequently, a transparent conductive film is formed on the lower substrate 101 on which the protective film 118 is formed through a deposition method such as a sputtering method. The transparent conductive film is patterned to form a transparent conductive pattern including the pixel electrode 122 and the common electrode 124.

FIG. 16 is a plan view illustrating a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 17 illustrates III1-III1 ', III2-III2', III3-III3 ', and III4-III4 substrates of the thin film transistor substrate of FIG. Is a cross-sectional view taken along a line.

The thin film transistor substrates shown in FIGS. 16 and 17 have a common parallel with the data lines 104 as well as the data lines 104 of adjacent sub-pixels are formed adjacent to each other in comparison to the thin film transistor substrates shown in FIGS. 2 and 3. It has the same components except having a supply line 154. Therefore, detailed description of the same constituent elements will be omitted.

Data lines 104 of adjacent sub-pixels are formed adjacent to each other. Accordingly, one side of the sub-pixel positioned on the left side of the data line 104 is surrounded by the common supply line 154, and the other side is surrounded by the data line 104. The sub-pixel is positioned on the right side of the data line 104. One side of the located sub-pixel is surrounded by the data line 104 and the other side is surrounded by the common supply line 154.

The common supply line 154 is formed on the same plane as the data line 104 and the same metal, and is formed in parallel with the data line 104. The common supply line 154 is formed to form a mesh with the common line 126. To this end, the common supply line 154 is connected through a common contact line 126 formed of a transparent conductive metal and a supply contact hole 148 penetrating through the passivation layer 118.

In addition, a step causing portion 117 is formed at an intersection of at least one of the common supply line 154, the gate line 102, and the common line 126. The step inducing unit 117 increases the separation distance between at least one of the common line 126 and the gate line 102 and the common supply line 154, so that at least one of the common voltage and the scan signal is coupled to the pixel signal. The phenomenon is prevented.

Meanwhile, an upper end portion of the common supply line 154 positioned between adjacent sub pixels overlaps the third storage electrode 152B of the sub pixel positioned on the right side with respect to the common supply line 154 and the common supply line 154. ) Overlaps with the third storage electrode 152A of the sub-pixel positioned on the left side of the common supply line 154.

Here, the third storage electrodes 152A and 152B corresponding to the sub pixels positioned on the left and right sides of the common supply line 154 are formed of the same metal and gate metal layers, and are spaced apart from each other.

The first storage capacitor Cst1 is formed such that the first storage electrode 142 connected to the common line 126 overlaps the second storage electrode 144 with the gate insulating layer 112 and the passivation layer 118 interposed therebetween. .

The first storage electrode 142 is formed at a line width of about 3 to 5 μm at the outermost side of each sub pixel to be adjacent to the data line 104. The first storage electrode 142 is formed of a gate metal layer on the lower substrate 101 and is connected to the common line 126 through the first storage contact hole 136. Here, the common line 126 is formed of a transparent conductive layer on the passivation layer 118, and the first storage contact hole 136 is formed to pass through the gate insulating layer 112 and the passivation layer 118 to form the first storage electrode ( 142 is formed to expose.

The second storage electrode 144 is formed on the passivation layer 118 as a transparent conductive layer and overlaps the first storage electrode 142. In this case, the second storage electrode 144 is formed to have a wider width than the first storage electrode 142 so that the first storage electrode 142 is located in the area of the second storage electrode 144. The second storage electrode 144 extends from the first horizontal portion 122B of the pixel electrode 122 to be parallel to the common electrode 124. As such, the second storage electrode 144 to which the pixel signal is supplied is shielded by the first storage electrode 142.

Here, although the first storage electrode 142 is connected to the common line 126 and the second storage electrode 144 is connected to the pixel electrode 122 as an example, the first storage electrode 142 is a pixel electrode ( 122 and the second storage electrode 144 may be connected to the common line 126.

The second storage capacitor Cst2 is formed by overlapping the common supply line 154 and the third storage electrode 152A with the gate insulating layer 112 interposed therebetween. The third storage electrode 152A is formed of a gate metal layer and is connected to the horizontal portion 122B of the pixel electrode 122 through the second storage contact hole 140. The second storage contact hole 140 is formed to penetrate the gate insulating layer 112 and the passivation layer 118 to expose the third storage electrode 152A. The third storage electrode 152A is formed to be covered by the common supply line 154 and the common electrode 124. That is, since the pixel signal supplied to the second storage electrode 152A is shielded by the common supply line 154 and the common electrode 124, the coupling phenomenon between the adjacent pixel electrode 122 and the second storage electrode 152A is prevented. Is prevented.

As described above, in the thin film transistor substrate according to the third embodiment of the present invention, the capacitance value of the entire storage capacitor of each sub-pixel is increased by the second storage capacitor formed by using the common supply line 154. Accordingly, if the total capacitance value of the storage capacitor is formed in the same manner as before, the line width (area) of the first to third storage electrodes 142, 144, and 152 and the common supply line 154 can be reduced, thereby improving the aperture ratio. As the aperture ratio is improved, it is not necessary to use expensive photo acrylic, the number of backlights can be reduced, and the brightness enhancement film can be removed, thereby reducing costs. In addition, since the thin film transistor substrate according to the third embodiment of the present invention does not have a storage line, a parasitic capacitor between the conventional storage line and the data line is not formed. Accordingly, the thin film transistor substrate according to the third embodiment of the present invention can prevent the fluctuation of the pixel signal and the common voltage from the data line DL due to the parasitic capacitor.

18 is a plan view illustrating a thin film transistor substrate according to a fourth exemplary embodiment of the present invention, and FIG. 19 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 18 taken along lines IV1 -IV1 'and IV2-IV2'. .

The thin film transistor substrates illustrated in FIGS. 18 and 19 form different distances between the first and second storage electrodes 142 and 144 and the data lines 104 as compared to the thin film transistor substrates illustrated in FIGS. 16 and 17. Except that it has the same components. Accordingly, detailed description of the same constituent elements will be omitted.

In the first storage capacitor Cst1, the first storage electrode 142 connected to the pixel electrode 122 and the second storage electrode 144 extending from the common line 126 are formed of the gate insulating layer 112 and the passivation layer 118. Overlapping is formed.

The first storage electrode 142 is formed as a gate metal layer on the lower substrate 101, and the first horizontal portion of the pixel electrode is formed through the storage contact hole 136 penetrating the gate insulating layer 112 and the passivation layer 118. 122B).

The second storage electrode 144 is formed on the passivation layer 118 as a transparent conductive layer. The second storage electrode 144 extends from the common line 126 to the sub pixel area. The second storage electrode 144 is formed farther from the data line than the first storage electrode.

Here, the first storage electrode 142 is described with the pixel electrode 122 and the second storage electrode 144 connected to the common line 126 as an example. In addition, the first storage electrode 142 is a common line ( 126 and the second storage electrode 144 may be connected to the pixel electrode 122. Preferably, in order to prevent coupling between any one of the storage electrodes 142 and 144 connected to the pixel electrode 122 and the data line 104, the storage electrodes 142 and 144 connected to the pixel electrode 122 are connected to the common line. It must be shielded by the storage electrodes 142 and 144 connected to 126.

Meanwhile, the first storage electrode 142 is a gate metal layer, and the second storage electrode 144 is formed by using a transparent conductive film as an example. However, the first storage electrode 142 is formed on different planes as follows.

When the first storage electrode 142 is formed of the gate metal layer on the lower substrate 101, the second storage electrode 144 is formed of the data metal layer on the gate insulating layer 112, and the first storage electrode 142 is formed of the gate metal layer. When the data metal layer is formed on the gate insulating layer 112, the second storage electrode 144 is formed as a transparent conductive layer on the gate metal layer or the protective layer 118 on the lower substrate 101, and the first storage electrode 142. Is formed of a transparent conductive film on the passivation layer 118, the second storage electrode 144 is formed of a gate metal layer on the lower substrate 101 or a data metal layer on the gate insulating layer 112.

20 is a plan view illustrating a thin film transistor substrate according to a fifth embodiment of the present invention, and FIG. 21 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 20 taken along a line VV ′.

20 and 21, the thin film transistor substrate includes the same components except that the first storage capacitor Cst1 overlaps the common electrode 124 as compared with the thin film transistor substrate illustrated in FIGS. 16 and 17. Equipped. Accordingly, detailed description of the same constituent elements will be omitted.

The first storage capacitor Cst1 is formed such that the first storage electrode 142 connected to the pixel electrode 122 overlaps the second storage electrode 144 with the gate insulating layer 112 interposed therebetween.

The first storage electrode 142 is formed to overlap the common electrode 124 adjacent to the data line 104. The first storage electrode 142 is formed as a gate metal layer on the lower substrate 101, and the horizontal portion 122B of the pixel electrode is formed through the storage contact hole 136 penetrating the gate insulating layer 112 and the passivation layer 118. Connected with.

The second storage electrode 144 is formed to overlap with the first storage electrode and the gate insulating layer 112 therebetween. The second storage electrode is formed of a data metal layer on the gate insulating layer 112 and is connected to the common line 126 through the common contact hole 128 penetrating the passivation layer 118. The second storage electrode 144 connected to the common line 126 shields the pixel signal supplied to the first storage electrode 142 together with the common electrode 124 to form a gap between the data line 104 and the pixel electrode 122. Prevent coupling phenomenon.

FIG. 22 is a plan view illustrating a thin film transistor substrate according to a sixth embodiment of the present invention, and FIG. 23 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 22 taken along a line VI-VI '.

The thin film transistor substrate shown in FIGS. 22 and 23 has a data line 104 and a second storage electrode positioned on the same plane as the data line 104 as compared to the thin film transistor substrate shown in FIGS. 20 and 21. The same components are provided except that the separation distance of 144 is large. Accordingly, detailed description of the same constituent elements will be omitted.

The first storage capacitor Cst1 is formed such that the first storage electrode 142 connected to the common line 126 overlaps the second storage electrode 144 with the gate insulating layer 112 interposed therebetween.

The first storage electrode 142 is formed to overlap the common electrode 124 adjacent to the data line 104. The first storage electrode 142 is formed as a gate metal layer on the lower substrate 101 and is connected to the common line 126 through a common contact hole 128 penetrating through the gate insulating layer 112 and the passivation layer 118. .

The second storage electrode 144 is formed to overlap with the first storage electrode 142 and the gate insulating layer 112 therebetween. The second storage electrode 144 is formed of a data metal layer on the gate insulating layer 112, and is connected to the horizontal portion 122B of the pixel electrode through the storage contact hole 136 that passes through the passivation layer 118. The pixel signal supplied to the second storage electrode 144 connected to the horizontal portion 122B of the pixel electrode is shielded by the first storage electrode 142 and the common electrode 124 formed to overlap each other, thereby the data line 104. Coupling between the pixel electrode 122 and the pixel electrode 122 is prevented.

In addition, the second storage electrode 144 is formed to have a narrower width than the first storage electrode 142. In this case, the separation distance between the second storage electrode 144 and the data line 104 is greater than the separation distance between the second storage electrode 144 and the data line 104 illustrated in FIGS. 20 and 21. Accordingly, short failure between the second storage electrode 144 and the data line 104 formed on the gate insulating layer 112 can be prevented, and the coupling phenomenon between the second storage electrode 144 and the data line 104 can be prevented. Can also be minimized.

Meanwhile, since the capacitance value of the first storage capacitor Cst1 is large enough to stably maintain the pixel signal charged in the pixel electrode 122, as shown in the thin film transistor substrate illustrated in FIG. 24, the thin film transistor substrate according to the present invention is used. The second storage capacitor Cst2 illustrated in FIGS. 16, 18, 20, and 22 may be omitted.

In the meantime, each pixel of the liquid crystal display panel according to the present invention includes three sub-pixels, for example, a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. It is arranged in the direction parallel to 104. In addition, as illustrated in FIGS. 25 and 26, each pixel further includes a white (W) subpixel in addition to the red (R) subpixel, the green (G) subpixel, and the blue (B) pixel to improve luminance. . Here, among the red (R), green (G), and blue (B) subpixels, the green (G) subpixel having the lowest light efficiency is disposed adjacent to the white (W) subpixel to improve the light efficiency of the green (G) subpixel. Compensate. Here, the common supply line 154 is formed in a stripe shape as shown in FIG. 25 or in a mesh shape as shown in FIG. 26.

In the meantime, the pixel electrode and the common electrode of the liquid crystal display according to the present invention have been described as an example of a Chevron structure that is bent once, but may be formed of a structure or stripe structure that is bent many times. In addition, the liquid crystal display according to the present invention has been described using a horizontal electric field type liquid crystal display as an example, but is also applicable to a vertical alignment (VA) type liquid crystal display.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a plan view illustrating a conventional thin film transistor substrate.

2 is a plan view illustrating a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 3 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along lines I1-I1 ', I2-I2', I3-I3 ', and I4-I4'.

4A and 4B are plan and cross-sectional views illustrating a method of manufacturing the gate metal pattern shown in FIGS. 2 and 3.

5A and 5B are a plan view and a cross-sectional view for describing a method of manufacturing the semiconductor pattern and the step difference generating unit illustrated in FIGS. 2 and 3.

6A and 6B are plan views and cross-sectional views illustrating a method of manufacturing the data metal pattern shown in FIGS. 2 and 3.

7A and 7B are plan views and cross-sectional views for describing a method of manufacturing the protective film shown in FIGS. 2 and 3.

8A and 8B are a plan view and a cross-sectional view for describing a method of manufacturing the transparent conductive pattern illustrated in FIGS. 2 and 3.

9 is a plan view illustrating a thin film transistor substrate according to a second exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 9 taken along lines II1-II1 'and II2-II2'.

11A and 11B are plan and cross-sectional views illustrating a method of manufacturing the gate metal pattern shown in FIGS. 9 and 10.

12A and 12B are a plan view and a cross-sectional view for describing a method of manufacturing the semiconductor pattern and the step difference generating unit illustrated in FIGS. 9 and 10.

13A and 13B are plan views and cross-sectional views illustrating a method of manufacturing the data metal pattern shown in FIGS. 9 and 10.

14A and 14B are a plan view and a sectional view for explaining a method of manufacturing the protective film shown in FIGS. 9 and 10.

15A and 15B are a plan view and a cross-sectional view for describing a method of manufacturing the transparent conductive pattern illustrated in FIGS. 9 and 10.

16 is a plan view illustrating a thin film transistor substrate according to a third exemplary embodiment of the present invention.

FIG. 17 is a cross-sectional view of the thin film transistor substrate of FIG. 16 taken along lines III1-III1 ', III2-III2', III3-III3 ', and III4-III4'.

18 is a plan view illustrating a thin film transistor substrate according to a fourth exemplary embodiment of the present invention.

FIG. 19 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 18 taken along lines IV1-IV1 ′ and IV2-IV2 ′.

20 is a plan view illustrating a thin film transistor substrate according to a fifth embodiment of the present invention.

FIG. 21 is a cross-sectional view of the thin film transistor substrate of FIG. 20 taken along the line VV ′.

22 is a plan view illustrating a thin film transistor substrate according to a sixth exemplary embodiment of the present invention.

FIG. 23 is a cross-sectional view of the thin film transistor substrate of FIG. 22 taken along a line VI-VI '.

24 is a plan view illustrating a thin film transistor substrate according to a seventh exemplary embodiment of the present invention.

FIG. 25 is a plan view illustrating a first embodiment of a red, green, blue, and white color filter structure of each sub-pixel illustrated in FIG. 16.

FIG. 26 is a plan view illustrating a second embodiment of a red, green, blue, and white color filter structure of each sub-pixel illustrated in FIG. 16.

Description of the Related Art

101: lower substrate 102: gate line

104: data line 106: gate electrode

108: source electrode 110: drain electrode

112 gate insulating film 114 active layer

116: ohmic contact layer 117: step causing portion

118: protective film 120,128,136,138,140,148: contact hole

122: pixel electrode 130: thin film transistor

132, 134, 142, 144, 152: storage electrode 154: common supply line

Claims (19)

A gate line formed on the substrate; A data line crossing the gate line and a gate insulating layer therebetween to form a sub pixel region; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor and formed in the sub pixel area; A common electrode forming a horizontal electric field with the pixel electrode; A common line connected to the common electrode to supply a common voltage to the common electrode; And a storage capacitor formed adjacent to the data line in a direction parallel to the data line to maintain the pixel signal charged in the pixel electrode. The method of claim 1, The storage capacitor A first storage electrode connected to at least one of the pixel electrode and the common line and adjacent to the data line; And a second storage electrode connected to the other one of the pixel electrode and the common line and overlapping the first storage electrode with at least one insulating layer therebetween. The method of claim 2, The second storage electrode is a thin film transistor substrate, characterized in that formed on the at least one insulating layer formed to cover the first storage electrode having a wider width than the first storage electrode. The method of claim 2, The separation distance between the second storage electrode and the data line is longer than the separation distance between the first storage electrode and the data line. The method according to claim 3 or 4, And the first and second storage electrodes overlap the common electrode adjacent to the data line. 6. The method of claim 5, And a common supply line connected to the common line and formed in a direction parallel to the data line. The method according to claim 6, The data lines of the adjacent sub-pixels are formed adjacent to each other. The method of claim 7, wherein And a third storage electrode overlapping the common supply line with at least one insulating layer therebetween to form a second storage capacitor. 9. The method of claim 8, An upper end of the common supply line positioned between the adjacent sub pixels overlaps the third storage electrode of a sub pixel positioned on the right side of the common supply line, and a lower end of the common supply line defines the common supply line. The thin film transistor substrate of claim 1, wherein the thin film transistor is overlapped with the third storage electrode of the sub pixel positioned on the left side. 9. The method of claim 8, Intersection of at least one of the intersection of the gate line and the data line, the intersection of the common supply line and the common line, the intersection of the common supply line and the gate line, and the intersection of the data line and the common line Further provided with a step causing portion formed between the parts, And the step inducing portion is formed by sequentially stacking the same material as each of the active layer and the ohmic contact layer of the thin film transistor on the gate insulating layer. Forming a thin film transistor connected to the gate line and the data line crossing the gate insulating layer between the substrate to form a sub pixel region; Forming a pixel electrode connected to the thin film transistor in the sub pixel area; Forming a common electrode in the sub-pixel region that forms a horizontal electric field with the pixel electrode and is supplied with a common voltage through a common line; And forming a storage capacitor adjacent to the data line in a direction parallel to the data line so as to maintain the pixel signal charged in the pixel electrode. The method of claim 11, Forming the storage capacitor Forming a first storage electrode connected to at least one of the pixel electrode and the common line and adjacent to the data line; And forming a second storage electrode connected to the other one of the pixel electrode and the common line and overlapping the first storage electrode with at least one insulating layer interposed therebetween. . 13. The method of claim 12, The second storage electrode is formed on the at least one insulating layer formed to cover the first storage electrode having a wider width than the first storage electrode. 14. The method of claim 13, The separation distance between the second storage electrode and the data line is longer than the separation distance between the first storage electrode and the data line. The method according to claim 13 or 14, The first and second storage electrodes overlap with the common electrode adjacent to the data line. 16. The method of claim 15, And forming a common supply line in a direction parallel to the data line and connected to the common line. 17. The method of claim 16, The data lines of the adjacent sub-pixels are formed adjacent to each other. The method of claim 11, And forming a third storage electrode overlapping the common supply line with at least one insulating layer therebetween to form a second storage capacitor. 17. The method of claim 16, The intersection of the gate line and the data line, the intersection of the common supply line and the common line, the intersection of the common supply line and the gate line, and the data line, at the same time as the active layer and the ohmic contact layer of the thin film transistor are formed. A method of manufacturing a thin film transistor substrate further comprising the step of forming a step causing portion between at least one of the intersection of the common line.

Images