KR100923673B1 - Transverse electric field mode liquid crystal display device - Google Patents

Abstract

In the transverse electric field mode liquid crystal display device of the present invention, the aperture ratio of the liquid crystal display device is improved while forming the set storage capacitance. In the present invention, an additional common line is arranged in the non-display area blocked by the black matrix to form a new storage capacitor, and the aperture ratio can be improved by reducing the width of the common line arranged in the pixel by the corresponding storage capacitor. It becomes possible.

Transverse electric field mode, black matrix, aperture ratio, storage capacitance, common line, pixel electrode line

Description

Transverse electric field mode liquid crystal display device {IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE}

1 is a plan view showing the structure of a conventional transverse electric field mode liquid crystal display device.

(A) is sectional drawing along the II 'line | wire of FIG.

Figure 2 (b) is an enlarged view of portion A of Figure 1;

3 is a plan view of a transverse electric field mode liquid crystal display device according to the present invention.

(A) is sectional drawing along the II-II 'line | wire of FIG.

(B) is sectional drawing along the III-III 'line | wire of FIG.

5 is an enlarged view of a portion B of FIG. 3;

Explanation of symbols on the main parts of the drawings

103: gate line 105: data line

106: common electrode 107: common line

108: pixel electrode 109: pixel electrode line

110: thin film transistor 111: gate electrode

112: semiconductor layer 113: source electrode

114: drain electrode 120,130: substrate

122: gate insulating layer 124: protective layer                 

132: black matrix 140: liquid crystal layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field mode liquid crystal display device, and in particular, an additional common line is disposed in a black matrix area disposed outside the pixel, and the pixel electrode line is arranged to overlap with the additional common line and the gate line. The present invention relates to a transverse electric field mode liquid crystal display device capable of improving the aperture ratio by reducing the width of common lines arranged in the pixel.

Recently, with the development of various portable electronic devices such as mobile phones, PDAs, and notebook computers, there is a growing demand for flat panel display devices for light and thin applications. Such flat panel displays are being actively researched, such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), and VFD (Vacuum Fluorescent Display). Liquid crystal display devices (LCDs) are in the spotlight for reasons of implementation.

Such liquid crystal display devices have various display modes according to the arrangement of liquid crystal molecules. However, TN mode liquid crystal display devices are mainly used because of the advantages of easy monochrome display, fast response speed, and low driving voltage. In such a TN mode liquid crystal display device, liquid crystal molecules aligned horizontally with the substrate are almost perpendicular to the substrate when a voltage is applied. Therefore, there is a problem that the viewing angle is narrowed upon application of voltage due to the refractive anisotropy of the liquid crystal molecules.

In order to solve this viewing angle problem, liquid crystal display devices of various modes having wide viewing angle characteristics have recently been proposed, but among them, the liquid crystal display device of the lateral field mode (In Plane Switching Mode) is applied to actual production. It is produced. The IPS mode liquid crystal display device aligns liquid crystal molecules in a plane by forming at least one pair of electrodes arranged in parallel in a pixel to form a transverse electric field substantially parallel to the substrate.

The structure of the IPS mode liquid crystal display device described above is shown in FIG. As shown in the figure, the pixels of the liquid crystal panel 1 are defined by gate lines 3a and 3b and data lines 5a and 5b arranged vertically and horizontally. Although only the (n, m) th pixels are shown in the drawing, in the actual liquid crystal panel 1, n and m gate lines and data lines are arranged, respectively, n n m over the entire liquid crystal panel 1. Pixels are formed. The thin film transistor 10 is formed at the intersection of the gate line 3a and the data line 5a in the pixel. The thin film transistor 10 includes a gate electrode 11 to which a scan signal is applied from a gate line 3a, and a semiconductor layer formed on the gate electrode 11 and activated as a scan signal is applied to form a channel layer ( 12 and a source electrode 13 and a drain electrode 14 formed on the semiconductor layer 12 and to which an image signal is applied through the data line 5a, and applying an image signal input from the outside to the liquid crystal layer. do. In the pixel, a plurality of common electrodes 6a to 6c and pixel electrodes 8a and 8b are arranged substantially parallel to the data lines 5a and 5b. Also, a common line 7 connected to the common electrodes 6a to 6c is disposed in the middle of the pixel, and a first pixel electrode line connected to the pixel electrodes 8a and 8b is disposed on the common line 7. 9a) is disposed and overlaps with the common line 7. The width t1 of the common line 7 and the width t2 of the first pixel electrode line 9a may be formed in any size, but the first pixel electrode line 9a may be formed in the common line 7. Since the width t1 of the common line 7 must be equal to or larger than the width t2 of the first pixel electrode line 9a, it is preferable to completely overlap with the width of the first pixel electrode line 9a. In the pixel, a second pixel electrode line 9b overlapping a part of the gate line 3b of the adjacent pixel (that is, the n + 1th pixel) is disposed.

FIG. 2A is a cross-sectional view taken along line II ′ of FIG. 1 and illustrates overlap between the common line 7, the first pixel electrode line 9a, the gate line 3b, and the second pixel electrode line 9b. It is shown for illustration. As shown in the figure, a common line 7 and a gate line 3b of the n + 1th pixel are formed on the lower substrate 20, and a gate insulating layer 22 is stacked thereon. The first pixel electrode line 9a and the second pixel electrode line 9b are formed on the gate insulating layer 22 on the common line 7 and the gate line 3b, and the protective layer 24 is formed thereon. Is laminated. As described above, the common line 7 and the first pixel electrode line 9a and the gate line 3b and the second pixel electrode line 9b overlap each other with the gate insulating layer 22 interposed therebetween. Accumulation capacity is formed.

The black matrix 32 is formed on the upper substrate 30. The black matrix 32 is formed in an area in which the liquid crystal molecules do not operate by an electric field (or an area in which the liquid crystal molecules operate abnormally due to electric field distortion) to prevent light from leaking to a corresponding area. It is mainly formed in the regions of the transistor 10, the gate lines 3a and 3b and the data lines 5a and 5b. In addition, a color filter layer 34 of R (Red), G (Green), and B (Blue) is formed on the upper substrate 30 to realize actual colors, and the lower substrate 20 and the upper substrate ( The liquid crystal layer 40 is formed between 30 to complete the IPS mode liquid crystal display device.

On the other hand, in the IPS mode liquid crystal display device having the above structure, a voltage of -5V is generally applied to the gate line 3b of the n + 1th pixel and a voltage of + 5V is applied to the common electrodes 6a to 6c. An unwanted electric field is formed between the gate line 3b and the common electrodes 6a to 6c. This electric field is a different electric field from the transverse electric field formed between the common electrodes 6a to 6c and the pixel electrodes 8a and 8b. The gate line 3b and the common electrode 6a are normally black mode. It becomes the cause of light leakage between -6c). In order to solve this problem, it is necessary to block the leaking light by forming a black matrix in the light leakage area.

FIG. 2B is an enlarged view of region A of FIG. 1 in which the black matrix 32 is formed in the light leakage region. As shown in the figure, an optical leakage region 17 having a width d1 of about 5 μm is formed in the pixel by an electric field between the gate line 3b and the common electrodes 6a to 6c. Therefore, the black matrix 32 must extend from the gate line 3b in the same manner as the width d1 of the light leakage region 17 to block the light leakage region 17, but in practice, the lower substrate 20 It is preferable to form a black matrix 32 having an extension width d3 larger than the width d1 of the light leakage region 17 due to the bonding margin of the upper substrate 30 and the upper substrate 30. The extension width d3 of the black matrix 32 does not mean the entire width of the black matrix 32. The width of the actual black matrix 32 will be the sum of the width for blocking the gate line 3b and the extension width d3. In the conventional IPS mode liquid crystal display device, the extension width d3 of the black matrix 32 is formed to about 9 μm.

In the drawing, reference numeral d2 denotes an interval between the gate line 3b and the common electrodes 6a to 6c, and the size thereof is about 10 mu m.

In the liquid crystal display device, the storage capacitor improves the voltage holding characteristic applied to the liquid crystal, improves the stability of the gradation display, and reduces flicker and residual images. Therefore, securing the set storage capacity is a very important factor in manufacturing the liquid crystal display device.

In general, an IPS mode liquid crystal display device is classified into a storage on gate (SOG) method and a storage on common (SOC) method according to a method of forming a storage capacitor. In the SOG type liquid crystal display device, the pixel electrode lines are arranged to overlap the gate line to form a storage capacitor by the pixel electrode line and the gate line. Arranged so as to overlap each other to form a storage capacitor by the pixel electrode line and the common line.

However, the above-described SOG and SOC liquid crystal display devices have the following problems. First, in the SOG type liquid crystal display device, since the gate lines are formed to have a predetermined width, the overlap area between the gate lines and the pixel electrode lines is inevitably limited, and as a result, a sufficient amount of storage capacitance cannot be formed. Second, in the SOC type liquid crystal display device, the overlap region of the common line and the pixel electrode line can be controlled to increase the width of the common line and the pixel electrode line so that a sufficient amount of storage capacitance is generated. There is a problem that the aperture ratio of the positive display element is lowered by the common line and the pixel electrode line.

Accordingly, in order to solve the above problems, a hybrid IPS mode liquid crystal display device having a combination of advantages of the SOG method and the SOC method has been recently proposed, and the ISP mode liquid crystal display device shown in FIG. Type liquid crystal display device. That is, two pixel electrode lines 9a and 9b are formed so that the first pixel electrode line 9a overlaps the common line 7 and the second pixel electrode line 9b overlaps the gate line 3b. It is to ensure a sufficient storage capacity of the mode liquid crystal display device.

However, even in the hybrid type IPS mode liquid crystal display device as described above, in order to secure sufficient storage capacity, the widths t1 and t2 of the common line 7 and the first pixel electrode line 9a must be formed to be greater than or equal to the set width, respectively. Therefore, there was a limit in preventing opening ratio fall.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and a first common layer formed in a pixel by arranging a second common line overlapping with a pixel electrode line in a non-display area of a pixel blocked by a black matrix to generate new storage capacitance. It is an object of the present invention to provide a transverse electric field mode liquid crystal display device capable of improving the aperture ratio by reducing the width of a line.                         

Another object of the present invention is to form two common lines connected to the common electrode, even if disconnection occurs in one common line by connecting the common electrode through another common line to prevent the failure by disconnection of the common line To provide a transverse electric field mode liquid crystal display device.

In order to achieve the above object, the transverse electric field mode liquid crystal display device according to the present invention comprises a plurality of pixels defined by gate lines and data lines, driving elements disposed in each pixel, and along the gate lines and data lines. A formed black matrix, at least one common electrode and a pixel electrode disposed substantially parallel in each pixel to form a transverse electric field, at least one first common line disposed in each pixel and connected to the common electrode, and each pixel At least one first pixel electrode line disposed within and overlapping the first common line and connected to the pixel electrode, at least one second common line disposed below the black matrix and connected to the common electrode; And a second pixel electrode connected to the electrode and overlapping at least a portion of the second common line and at least a portion of the gate line.

The black matrix extends to the light leakage region due to the electric field generated between the common electrode and the gate line. Since the light leakage region is about 5 μm and the width of the second common line is 4 to 5 μm, the black matrix is formed. It is preferable to extend 9 to 10 mu m from the gate line.

The present invention provides an IPS mode liquid crystal display device capable of improving the aperture ratio while securing a sufficient storage capacity. In particular, the present invention provides a modified hybrid type IPS mode liquid crystal display device. To this end, in the present invention, a second common line is formed and placed in a dead region (region where no information is displayed on the screen) of the liquid crystal display device, and a desired storage capacitance is obtained by overlapping the pixel electrode line with the second common line. It can be formed. At this time, since the second common line is formed in the light leakage region blocked by the black matrix, the reduction of the aperture ratio by the formation of the second common line does not occur. Rather, since the width of the first common line disposed in the pixel can be reduced by the amount corresponding to the storage capacitance generated by the second common line and the pixel electrode line, the aperture ratio can be improved.

In addition, in the present invention, since the common line is formed of two common lines as described above, even when one common line is disconnected, the common electrode is connected to the other common line. It can be prevented from occurring.

Hereinafter, an IPS mode liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view showing the structure of an IPS mode liquid crystal display device according to the present invention. As shown in the figure, a thin film transistor 110 is formed in a pixel defined by the gate lines 103a and 103b and the data lines 105a and 105b, and the data lines 105a and 105b are formed in the pixel. The plurality of common electrodes 106a to 106c and the pixel electrodes 108a and 108b arranged in substantially parallel are arranged.                     

The thin film transistor 110 includes a gate electrode 111 connected to the gate line 103a, a semiconductor layer 112 formed on the gate electrode 111, and a source electrode 113 connected to the data line 105a. ) And the drain electrode 114.

As the scan signal input from an external driving circuit (not shown) is input to the gate electrode 111 of the thin film transistor 110 through the gate line 103a, the semiconductor layer 112 is activated to form a channel layer. At the same time, a data signal input to the data line 105a from an external driving circuit is applied to the pixel electrodes 108a and 108b through the source electrode 113 and the drain electrode 114, and the common electrodes 106a to 106c and the common electrode 106a to 106c. A transverse electric field is formed between the pixel electrodes 108a and 108b.

Meanwhile, a first common line 107a and a second common line 107b connected to the common electrodes 106a to 106c are disposed in the pixel. In this case, the first common line 107a is disposed at the center of the pixel, and the second common line 107b is disposed near the gate line 103b of the adjacent n + 1th pixel. A plurality of common electrodes 106a to 106c are connected to the first common line 107a and the second common line 107b, respectively. In the pixel, a first pixel electrode line 109a and a second pixel electrode line 109b connected to the pixel electrodes 108a and 108b are arranged. The first pixel electrode line 109a overlaps the first common line 107a, and the second pixel electrode line 109b overlaps the gate line 103b and the second common line 107b of the adjacent pixel. have.

As described above, when the common electrodes 106a to 106c are connected to a double common line (i.e., the first common line 107a and the second common line 107b), they are disconnected to one common line. In addition, since the common electrodes 106a to 106c are connected to each other by a common line, it is possible to prevent defects caused by disconnection of the common line.

On the other hand, the second common line 107b is not formed in the effective display area of the element. In other words, the second common line 107b is formed in the dead area of the pixel. Therefore, the opening ratio of the liquid crystal display device is not lowered by the formation of the second common line 107b. The second pixel electrode line 109b completely overlaps with the second common line 107b, while only part of the second pixel electrode line 109b overlaps the gate line 103b.

As shown in FIG. 4A, the common electrodes 106a to 106c are formed on the lower substrate 120 made of a transparent material such as glass, and the pixel electrodes 108a and 108b are formed on the lower substrate 120. It is formed on the stacked gate insulating layer 122. Although not shown in the drawings, a gate electrode 111 of the thin film transistor 110 is formed on the lower substrate 120, and a semiconductor layer 112 is formed on the gate insulating layer 122. The source electrode 113 and the drain electrode 114 are formed on the 112. As described above, the common electrodes 106a to 106c and the gate electrode 111 are formed on the lower substrate 120, and sputtering or evaporation of a metal such as Cu, Cr, Mo, Al, or Al alloy It is formed of a single layer or a plurality of layers laminated and etched in the method. Of course, at this time, the common electrodes 106a to 106c and the gate electrode 111 may be made of different metals. However, for the sake of simplicity, the common electrodes 106a to 106c and the gate electrodes 111 may be made of the same metal.

In addition, the pixel electrodes 108a and 108b, the source electrode 113 and the drain electrode 114 of the thin film transistor 110 are formed on the semiconductor layer 112 and the gate insulating layer 122, respectively. The pixel electrodes 108a and 108b, the source electrode 113, and the drain electrode 114 are formed by stacking metals such as Cr, Mo, Cu, Al, and Al alloys by sputtering or vapor deposition, and etching by a etchant. As a layer or a plurality of layers, the same material may be formed by laminating and etching the same process, but different materials may be formed through different processes.

Meanwhile, the upper substrate 130 facing the lower substrate 120 has a black matrix 132 for preventing light from leaking between pixels and the thin film transistor 110, and a color filter layer for implementing actual colors. 134 is formed, and the liquid crystal layer 140 is formed between the lower substrate 120 and the upper substrate 130. Although not shown in the drawing, an overcoat layer may be formed on the color filter layer 134 to improve surface stability and to improve flatness. In general, the liquid crystal layer 140 is formed by injecting liquid crystal between the lower substrate 120 and the upper substrate 130 bonded by the vacuum injection method, but on the lower substrate 120 or the upper substrate 130. After dropping the liquid crystal directly, the lower substrate 120 and the upper substrate 130 may be formed by a liquid crystal dropping method in which the liquid crystal is distributed over the entire substrate.

As shown in FIG. 4B, the first common line 107a and the second common line 107b are formed on the lower substrate, and the first pixel electrode line 109a and the second pixel electrode line 109b. Is formed over the gate insulating layer 122. In this case, the first pixel electrode line 109a overlaps the first common line 107a with the gate insulating layer 122 interposed therebetween, and the second pixel electrode line 109b is connected to the second common line 107b and It overlaps with the gate line 103b. As shown in the drawing, since the width t1 of the first common line 107a is larger than the width t2 of the first pixel electrode line 109a, the first pixel electrode line 109a is completely formed. It overlaps with the 1st common line 107a. On the other hand, since the width t4 of the second pixel electrode line 109b is larger than the width t3 of the second common line 107b, the second common line 107b is formed from the second pixel electrode line 109b. Not only is it completely overlapping, but a part of the gate line 103b is also overlapped with the second pixel electrode line 109b. In addition, the width t5 of the black matrix is greater than the width t4 of the second pixel electrode line such that the black matrix extends to an optical leakage region between the gate line and the common electrode, and the second common line and the gate. Completely overlap the line and the second pixel electrode line.
As described above, the first storage capacitor Cst1 is formed in the pixel by the overlap of the first common line 107a and the first pixel electrode line 109a, and the second common line 107b and the second pixel electrode line are formed in the pixel. The second storage capacitor Cst2 is formed by the overlap of 109b. In addition, a third storage capacitor Cst3 is formed by the overlap of the second pixel electrode line 109b and the gate line 103b to form a total storage capacitor Cst = Cst1 + Cst2 + Cst3.

delete

In the conventional IPS mode liquid crystal display device shown in FIGS. 1 and 2, a total of two overlap regions (that is, overlap regions of the common electrode and the first pixel electrode line and overlap regions of the gate line and the second pixel electrode line) are used. While the storage capacitor Cst is generated, in the IPS mode liquid crystal display device of the present invention, the total storage capacitor Cst is generated by three overlap regions. Assuming that the overlap area between the gate line and the second pixel electrode line is the same in the conventional IPS mode liquid crystal display device and the IPS mode liquid crystal display device of the present invention, eventually, the first and second of the IPS mode liquid crystal display device according to the present invention. Accumulation capacity (Cst1 + Cst2) due to overlap of common line (107a, 107b) and first pixel electrode line (109a, 109b) is equal to that of the common line and the first pixel electrode line of conventional IPS mode liquid crystal display device. Will be the same.

Meanwhile, in the present invention, the second common line 107b is formed in the dead area of the pixel in which information is not displayed. Therefore, it is the first common line 107a and the first pixel electrode line 109a which are arranged in the center area of the pixel (strictly the actual display area of the pixel) that affect the aperture ratio of the liquid crystal display element. The storage capacitor Cst1 generated by the first common line 107a and the first pixel electrode line 109a is viewed from the storage capacitors generated by the common line and the first pixel electrode line of the conventional IPS mode liquid crystal display device. This is an amount obtained by subtracting the storage capacitor Cst2 generated by the second common line 107b and the second pixel electrode line 109b of the present invention. In other words, the storage capacitance generated by the electrode line formed in the pixel center region of the IPS mode liquid crystal display device of the present invention is significantly reduced compared to the conventional IPS mode liquid crystal display device, and thus the electrode line formed in the pixel center region (i.e., As a result, the widths t1 and t2 of the first common line 107a and the first pixel electrode line 109a can be significantly reduced as compared with the prior art, thereby improving the aperture ratio.

FIG. 5 is an enlarged view of region B of FIG. 3. As shown in the figure, a black matrix 132 is provided on the upper substrate 130 to prevent light leakage due to an electric field generated between the gate line 103b of the n + 1th pixel and the common electrodes 106a to 106c. Is formed along the gate line 103b. The second common line 107b is disposed under an area (no image display area) blocked by the black matrix 132. Accordingly, the second common line 107b forms the storage capacitor Cst2 but does not affect the aperture ratio of the IPS mode liquid crystal display device. In general, when the second common line 107b is disposed near the gate line 103b, the second common line 107b and the second common line 107b may be used to prevent the short circuit between the second common line 107b and the gate line 103b. The distance d4 of the gate line 103b must be 5 µm or more.

Meanwhile, the black matrix 132 extends about 9 μm from the gate line 103b in consideration of the bonding margin between the lower substrate 120 and the upper substrate 130. Therefore, in order to maximize the storage capacity without affecting the opening ratio, it is preferable to form the width t3 of the second common line 107b disposed below the black matrix 132 at about 4 μm. At this time, the width t3 of the second common line 107b is not an absolute value. For example, when extending from the gate line 103b of the black matrix 132 to about 10 μm and the width t3 of the second common line 107b is about 5 μm, the first common line 107a is formed. Since the width t1 can be reduced, the aperture ratio of the entire pixel is improved. In practice, since the common electrodes 106a to 106c are about 10 mu m away from the gate line 103b, the width of the second common line 107b is formed to be 4 to 5 mu m, and the black matrix 132 is formed of the gate line (132). It is most preferable to extend about 9-10 탆 from 103b).

In the above embodiment, the IPS mode liquid crystal display device of the present invention has a specific structure. For example, the gate line, the common electrode, and the common line are formed on the lower substrate, and the data line, the pixel electrode, and the pixel electrode line are formed on the gate insulating layer. However, the present invention is not limited to the above specific structure. For example, a structure in which a common electrode is formed on a protective layer and connected to a common line through a contact hole, a structure in which a common electrode and a pixel electrode are formed on the same layer as a gate insulating layer or a protective layer, and a common electrode The IPS mode liquid crystal display device having all possible structures, such as a structure formed over the silver gate insulating layer and the pixel electrode formed over the protective layer, may be applied to the present invention. In addition, an IPS mode liquid crystal display device having a structure in which two or more common lines are formed under the black matrix may be applied to the present invention. In other words, if two common electrodes are formed and one common electrode is formed in the dead area under the black matrix, the set storage capacity can be secured and the aperture ratio can be improved. Will be applicable.

As described above, in the IPS mode liquid crystal display device of the present invention, an additional common line is arranged under the black matrix arranged along the gate line region and overlaps with the pixel electrode line, thereby ensuring the set storage capacity and being arranged in the pixel. Since the width of the common line can be reduced, the aperture ratio of the IPS mode liquid crystal display device can be improved.

In addition, in the present invention, since the common lines to which the common electrodes are connected are arranged in double, even when a disconnection occurs in one common line, the common electrodes may be connected to the other common lines. Can be prevented.

Claims (16)

A first substrate and a second substrate; A plurality of pixels defined by gate lines and data lines formed on the first substrate; A drive element disposed in each pixel; A black matrix formed on the second substrate and disposed along the gate line and the data line; At least one common electrode and a pixel electrode disposed substantially parallel to each pixel of the first substrate to form a transverse electric field; A first common line disposed in each pixel of the first substrate and connected to the common electrode and extending over a plurality of pixels along an extension direction of the gate line; A first pixel electrode line disposed in each pixel of the first substrate and overlapping the first common line and connected to the pixel electrode; A second common line connected to the common electrode and extending over the plurality of pixels in an extension direction of the gate line; And A second pixel electrode line connected to the pixel electrode and overlapping an entirety of the second common line and a part of the gate line; The width t1 of the first common line is greater than the width t2 of the first pixel electrode line such that the first common line completely covers the first pixel electrode line and the width t4 of the second pixel electrode line is It is formed larger than the width t3 of the second common line so that the second pixel electrode line completely covers the second common line, and the width t5 of the black matrix is larger than the width t4 of the second pixel electrode line. And the black matrix extends to an optical leakage region between the gate line and the common electrode so that the black matrix completely covers the second common line and the second pixel electrode line and partially covers the gate line, and the first common And a line and a second common line extend all over the pixel area in parallel with the gate line of the first substrate. delete delete delete The transverse electric field mode liquid crystal display device according to claim 1, wherein the light leakage region is 5 mu m. The transverse electric field mode liquid crystal display device according to claim 1, wherein the width of the second common line is 4 to 5 탆. The transverse electric field mode liquid crystal display device according to claim 5 or 6, wherein the black matrix extends 9 to 10 mu m from a gate line. The transverse electric field mode liquid crystal display device of claim 1, wherein the driving device is a thin film transistor. The method of claim 8, wherein the thin film transistor, A gate electrode formed on the substrate; A gate insulating layer stacked over the entire substrate on which the gate electrode is formed; A semiconductor layer formed on the insulating layer; A source electrode and a drain electrode formed on the semiconductor layer; And A transverse electric field mode liquid crystal display device comprising a protective layer stacked over the entire substrate on which the source and drain electrodes are formed. The transverse electric field mode liquid crystal display device of claim 9, wherein the first common line and the second common line are arranged on a substrate. The transverse electric field mode liquid crystal display device of claim 9, wherein the first pixel electrode line and the second pixel electrode line are formed on a gate insulating layer. 10. The transverse electric field mode liquid crystal display device of claim 9, wherein the common electrode is formed on a substrate, a gate insulating layer, or a protective layer. 10. The transverse electric field mode liquid crystal display device of claim 9, wherein the pixel electrode is formed on a substrate, a gate insulating layer, or a protective layer. delete delete delete

Images