KR101354432B1 - Liquid Crystal Display and Driving Method Thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for driving the same, which improve display quality by controlling a timing controller to compensate for line luminance differences.

According to an exemplary embodiment of the present invention, an LCD device includes: an image display unit including a plurality of data lines and a plurality of gate lines, a plurality of liquid crystal cells arranged in a matrix form, and including a thin film transistor at the intersection; A gate driving circuit supplying scan pulses to the gate lines in response to gate control signals; a data driving circuit supplying data voltages to the data lines; A memory for storing position information of a specific position of the image display unit and count value information indicating a pulse width of a scan pulse supplied to a gate line of the specific position; And controlling a pulse width of a scan pulse to be supplied to a specific position of the image display unit differently from those of scan pulses to be supplied to gate lines other than the specific position based on the position information and the count value information. A timing controller is provided.

Description

Liquid Crystal Display and Driving Method Thereof

1 is a block diagram of a general liquid crystal display device.

2 is a timing diagram illustrating scan pulses generated according to a gate control signal.

3 is a view showing a difference in charge amount due to the characteristic difference of the liquid crystal.

4 is a view illustrating an example of a line dim phenomenon due to a difference in filling amount of FIG. 3.

5 is a block diagram of a liquid crystal display device according to the present invention;

6 is a schematic view of the gate driving circuit of FIG.

FIG. 7 is a schematic view of the data driving circuit of FIG. 5. FIG.

8 is a timing diagram of a modulation gate control signal MGDC and a plurality of scan pulses SP generated thereby according to a first embodiment of the present invention.

9 is a view for explaining the charge compensation of the data voltage (Vd) in the liquid crystal cell according to the first embodiment of the present invention.

10 is a timing diagram of a modulation gate control signal MGDC and a plurality of scan pulses SP generated thereby according to a second embodiment of the present invention.

FIG. 11 is a view for explaining charge compensation of a data voltage Vd in a liquid crystal cell according to a second embodiment of the present invention; FIG.

12 is a view showing an image display unit in which a luminance difference for each line is compensated for;

13 is a flowchart for explaining a method of driving a liquid crystal display device according to the present invention;

Description of the Related Art

110: interface 112: memory

114: timing controller 116: reference voltage generation circuit

118: data driving circuit 120: gate driving circuit

122: liquid crystal panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof in which a display quality is improved by controlling a timing controller to compensate for a line luminance difference.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal cells according to a video signal. Among them, an active matrix type liquid crystal display device is advantageous in that a switching element is formed for each liquid crystal cell to display a moving image.

1 is a block diagram of a general liquid crystal display device.

Referring to FIG. 1, first, the interface unit 10 includes a digital data signal RGB data and a control signal (for example, an input clock CLK, a horizontal synchronization signal Hsync), input from a driving system such as a personal computer. The vertical synchronization signal Vsync and the data enable signal DE are supplied to the timing controller 12. The interface unit 10 mainly uses a low voltage differential signal (LVDS) interface and a TTL interface for signal transmission with a driving system. The interface unit 10 may be integrated into a single chip together with the timing controller 12.

The timing controller 12 controls the driving timing of the gate driving circuit 20 and the data control signal DDC for controlling the driving timing of the data driving circuit 18 using the control signal input through the interface unit 10. The gate control signal GDC is controlled. In addition, the timing controller 12 transmits the digital data signal RGB input from the interface unit 10 to the data driving circuit 18.

The gate driving circuit 20 generates a scan pulse in response to the gate control signal GDC and sequentially supplies the gate pulses to the gate lines GL of the liquid crystal panel 22.

The reference voltage generation circuit 16 generates various gamma reference voltages GMA set based on the transmittance-voltage characteristic of the panel and supplies the generated gamma reference voltages GMA to the data driving circuit 18.

The data driving circuit 18 converts the digital data signal RGB into an analog data signal (hereinafter referred to as a "data voltage") based on the gamma reference voltages GMA in response to the data control signal DDC. The data driving circuit 18 supplies the data voltage to the data lines DL of the liquid crystal panel 22 whenever the scan pulse is supplied.

In the liquid crystal panel 22, a gate line GL and a data line DL intersect each other, and a thin film transistor (hereinafter, referred to as TFT) for driving the liquid crystal cell Clc is formed at an intersection thereof. . The TFT supplies the data voltage supplied through the data line DL to the pixel electrode of the liquid crystal cell Clc in response to the scan pulse supplied through the gate line GL. For this purpose, the gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc. The liquid crystal cell Clc is charged with a potential difference between the data voltage and the common voltage Vcom, and the arrangement of the liquid crystal molecules is changed by the electric field formed by the potential difference to control the amount of light transmitted or to block the light. The illustrated storage capacitor Cst maintains the charging voltage of the liquid crystal cell Clc for one frame.

In the liquid crystal display device having such a configuration, the timing controller 12 generates predetermined control signals DDC and GDC for driving the liquid crystal display device in response to the control signals input as described above. In general, the timing controller 12 generates a data control signal DDC and a gate control signal GDC by counting the clock CLK based on the edge Edge of the data enable signal DE. Control signals generated from the timing controller 12 may be different depending on the type of the data driving circuit 18 and the gate driving circuit 20. Here, the types and timings of the control signals that are commonly used except for the specially required signals will be described.

The data control signal DDC includes a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, and a polarity signal POL. The source start pulse SSP is a signal for notifying the latch or sampling start of the digital data during one horizontal period. The source sampling clock SSC is used as a sampling clock for latching digital data in the data driving circuit 18 and determines a driving frequency of the data driving circuit 18. The source output enable signal SOE indicates an output time point at which digital data latched by the source sampling clock SSC is supplied to the liquid crystal panel 22. The polarity signal POL is a signal for driving the liquid crystal to positive and negative polarities for inversion driving.

When the data driving circuit 18 recognizes the "High" input of the source start pulse SSP at the rising edge of the source sampling clock SSC, the data driving circuit 18 latches the digital data signal input in response to the source sampling clock SSC. The latched digital data signal is decoded into a data voltage according to the source output enable signal SOE and then supplied to the liquid crystal panel. At this time, according to the polarity signal POL, the output voltage of the positive decoder higher than the common voltage or the output voltage of the negative decoder lower than the common voltage is selected so that the liquid crystal cell Clc is positive / negative. It will run inversion.

The gate control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse GSP is a signal indicating the first driving line of the screen in one vertical period. The gate shift clock GSC is a signal that determines the time when the TFT is turned on / off. The gate output enable signal GOE is a signal for controlling the output of the gate driving circuit 20. The operation of the liquid crystal display according to the gate control signal GDC will be described with reference to FIGS. 2 and 3.

Referring to FIG. 2, the gate driving circuit 18 recognizes the "High" state of the gate start pulse GSP at the rising edge of the gate shift clock GSC, and the gate driving circuit 18 recognizes the "High" state of the gate shift clock GSC. The scan pulse SP maintaining the "High" state is output. The output of the scan pulse SP is masked by the width of the gate output enable signal GOE in the "High" state. This scan pulse SP is between the gate high voltage Vgh set to a voltage for turning on the TFT and the gate low voltage Vgl set to a voltage for turning off the TFT as shown in FIG. Is swinging on. Non-scanning in which the liquid crystal cell Clc charges the data voltage Vd and the scan pulse SP maintains the gate low voltage Vgl during the scanning period in which the scan pulse SP maintains the gate high voltage Vgh. During this period, the liquid crystal cell Clc maintains this charged data voltage Vd for one frame.

However, such a liquid crystal display device has various factors, for example, between liquid crystal cells arranged in a specific horizontal line and liquid crystal cells arranged in another horizontal line according to differences in parasitic capacitance, cell gap, liquid crystal properties, driving method, and the like. Shows the difference in characteristics of the liquid crystal. Since the charging ability of the liquid crystal cell is greatly influenced by the characteristics of the liquid crystal, even if the same data voltage Vd and the gate high voltage Vgh of the same width are applied, the charging amount of the liquid crystal cells arranged in different horizontal lines (see FIG. a)) and the filling amount (Fig. 3 (b)) of the liquid crystal cell arranged in a specific horizontal line will show a difference.

4 illustrates a line dim phenomenon due to a difference in filling amount for each horizontal line. The decrease in the filling amount in a specific horizontal line causes a difference in luminance between the other horizontal lines having a normal filling amount and causes a line dim phenomenon. For example, in the normally black mode, horizontal lines with less charge are darker than other horizontal lines with normal charge. Such a luminance difference for each horizontal line is a factor that degrades the display quality of the liquid crystal display.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof to improve display quality by compensating a horizontal line luminance difference through gate control signal modulation.

In order to achieve the above object, an LCD according to an exemplary embodiment of the present invention includes an image including a plurality of data lines and a plurality of gate lines, a plurality of liquid crystal cells arranged in a matrix form, and a thin film transistor disposed at the intersection. A display unit; A gate driving circuit supplying scan pulses to the gate lines in response to gate control signals; a data driving circuit supplying data voltages to the data lines; A memory for storing position information of a specific position of the image display unit and count value information indicating a pulse width of a scan pulse supplied to a gate line of the specific position; And controlling a pulse width of a scan pulse to be supplied to a specific position of the image display unit differently from those of scan pulses to be supplied to gate lines other than the specific position based on the position information and the count value information. A timing controller is provided.

The count value information includes first count value information indicating generation of a gate shift clock for determining a turn-on time of the thin film transistor; And second count value information indicating generation of a gate output enable signal for controlling the output of the gate driving circuit.

The count value information may include: first count value information indicating generation of a gate shift clock for determining a turn-on time of the thin film transistor; Second count value information indicating generation of a gate output enable signal for controlling the output of the gate driving circuit; And third count value information instructing generation of a pulse modulation signal for controlling the high logic voltage output of the scan pulse.

The memory may be built in the timing controller.

The memory may be one of an electrically erasable programmable read only memory (EEPROM) and an extended display identification data ROM (EDID ROM) capable of erasing and updating the position information and the count value information.

According to an embodiment of the present invention, a plurality of data lines and a plurality of gate lines intersect, a plurality of liquid crystal cells are arranged in a matrix form, and a driving method of a liquid crystal display apparatus having an image display unit including a thin film transistor at the intersection, Supplying test data to the data lines and supplying scan pulses to the gate lines to display a test image on the image display unit; Determining a specific position in which the luminance differs from other portions in the image display portion based on the test image; Storing position information of the specific position and count value information indicating a pulse width of the scan pulse to be supplied to the gate line of the specific position in a memory of the liquid crystal display; And the pulse widths of the scan pulses to be supplied to a specific position of the image display unit based on the positional information and the count value information from the memory, and those of the scan pulses to be supplied to gate lines of the image display unit other than the specific position. Controlling differently.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 5 to 13. FIG.

5 is a block diagram of a liquid crystal display according to the present invention.

Referring to FIG. 5, the liquid crystal display according to the present invention includes an interface 110, a memory 112, a timing controller 114, a reference voltage generation circuit 116, a data driving circuit 118, and a gate driving circuit 120. ) And a liquid crystal panel 122.

The interface unit 110 is a digital data signal (RGB Data) and control signals (for example, an input clock CLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync) input from a driving system such as a personal computer. The data enable signal DE is supplied to the timing controller 112. The interface unit 10 mainly uses a low voltage differential signal (LVDS) interface and a TTL interface for signal transmission with a driving system. The interface unit 110 may be integrated into a single chip together with the timing controller 114.

The memory 112 includes position information PD for a specific position of the liquid crystal panel 122 and a pulse width of a gate high voltage supplied to the gate line GL at this specific position (hereinafter referred to as "pulse width of a scan pulse"). Count value information (CD) indicating " The specific position refers to the position of the gate line (or horizontal line) whose luminance is lower than that of other gate lines (or horizontal lines) in the image display unit of the liquid crystal panel 122. In order to determine this specific position, the user displays the test image on the image display unit of the liquid crystal panel 122 in the test step of the liquid crystal panel 122, and then detects the luminance of the image display unit. For the display of the test image, scan pulses of the same width as the test voltage having the same magnitude are applied to the liquid crystal cells connected to all horizontal lines. As a result of the luminance detection, when the luminance of the liquid crystal cells connected to a specific horizontal line is lower than that of the liquid crystal cells connected to other horizontal lines due to the characteristic difference of the liquid crystal, the user stores the position information PD of the specific horizontal line. Save to 112. In addition, the user stores count value information CD indicative of the pulse width of the scan pulse supplied to this particular horizontal line in the memory 112. To this end, the memory 112 is a nonvolatile memory capable of erasing and updating data, for example, an electrically erasable programmable read only memory (EEPROM) or an extended display identification data ROM (EDID ROM). The count value information CD is set so that the pulse width of the scan pulse supplied to the specific horizontal line is different from the pulse width of the scan pulse supplied to the other horizontal lines. For example, when driven in a normally black mode, the count value information CD is supplied with pulse widths of scan pulses supplied to a specific horizontal line to other horizontal lines to compensate for a decrease in luminance in a specific horizontal line. It is set to be larger than the pulse width of the scan pulse. The count value information CD includes first count value information indicating generation of a gate shift clock and second count value information indicating generation of a gate output enable signal and / or a generation indicating pulse generation signal. 3 count value information.

The timing controller 114 generates a data control signal DDC for controlling the driving timing of the data driving circuit 118 using the control signals from the interface unit 110. The timing controller 114 controls the driving timing of the gate driving circuit 120 by using the control signals from the interface unit 110, the position information PD and the count value information CD from the memory 112. The modulation gate control signal MGDC is generated. The modulation gate control signal MGDC is a modulation gate shift clock MGSC and a modulation gate output enable signal MGOE and / or a modulation gate modulation signal MFLK, as shown in FIGS. 8 and 10. The timing controller 114 transmits the digital data signal RGB input from the interface unit 110 to the data driving circuit 118.

The gate driving circuit 120 generates a scan pulse having a first pulse width in response to the modulation gate control signal MGDC and supplies the scan pulse to other horizontal lines other than a specific horizontal line, and a second pulse larger than the first pulse width. A scan pulse with a width is generated and supplied to a specific horizontal line. The gate driving circuit 120 will be described in detail with reference to FIG. 6.

The reference voltage generation circuit 116 generates various gamma reference voltages GMA set based on the transmittance-voltage characteristic of the panel and supplies the generated gamma reference voltages GMA to the data driving circuit 118.

The data driving circuit 118 converts the digital data signal RGB to the data voltage based on the gamma reference voltages GMA in response to the data control signal DDC. The data driving circuit 118 supplies a data voltage to the data lines DL whenever a scan pulse having a first or second pulse width is supplied.

In the liquid crystal panel 122, a gate line GL and a data line DL intersect each other, and a TFT for driving the liquid crystal cell Clc is formed at an intersection thereof. The TFT supplies a data voltage supplied through the data line DL to the pixel electrode of the liquid crystal cell Clc in response to a scan pulse having a first or second pulse width supplied through the gate line GL. For this purpose, the gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc. The liquid crystal cell Clc is charged with a potential difference between the data voltage and the common voltage Vcom, and the arrangement of the liquid crystal molecules is changed by the electric field formed by the potential difference to control the amount of light transmitted or to block the light. The storage capacitor Cst maintains the charging voltage of the liquid crystal cell Clc for one frame.

6 schematically shows the gate driving circuit 120.

Referring to FIG. 6, the gate driving circuit 120 includes a plurality of integrated circuits (ICs), each of which includes a shift register block 130, a level shifter block 132, and an output buffer block 134. It is provided.

The shift register block 130 has a plurality of stages S1 to Si that are cascaded. The shift register block 130 shifts the shift output signal from the first stage S1 to the i-th stage Si in response to the gate start pulse GSP and the modulation gate shift clock MGSC supplied from the timing controller 114. Vs1 to Vsi) are sequentially output.

The level shifter block 132 includes a plurality of level shifters L / S1 to L / Si to correspond one-to-one with the plurality of shift registers S1 to Si. The plurality of level shifters L / S1 to L / Si are in response to the modulation gate output enable signal MGOE and / or the modulation gate modulation signal MFLK supplied from the timing controller 114. The shift output signals Vs1 to Vsi from Si are converted into scan pulses SP1 to SPi swinging between the gate low voltage Vgl and the gate high voltage Vgh and supplied to the output buffer block 134. Here, the gate high voltage Vgh is a voltage above the threshold voltage of the TFTs of the liquid crystal display panel 122, that is, the gate-on voltage, and the gate low voltage Vgl is a voltage below the threshold voltage of the TFTs, that is, the gate-off voltage. to be.

The output buffer block 134 includes a plurality of output buffers B1 to Bi to correspond one-to-one with the plurality of level shifters L / S1 to L / Si. The plurality of output buffers B1 to Bi buffer the scan pulses SP1 to SPi from the level shifters L / S1 to L / Si and output them to the corresponding gate lines GL1 to GLi.

7 schematically shows the data driving circuit 118.

Referring to FIG. 7, the data driving circuit 118 includes a plurality of integrated circuits (ICs), each integrated circuit including a shift register 182 and a first latch (sub) which are cascaded between an input line and a data line. 181, a second latch 183, a digital-to-analog converter (hereinafter referred to as a "DAC") 184, and a buffer 185.

The shift register 182 shifts the source start pulse SSP from the timing controller 114 according to the source shift clock signal SSC to generate a sampling signal. In addition, the shift register 182 shifts the source start pulse SSP to transfer the carry signal CAR to the next stage shift register 182.

The first latch 181 samples and stores the digital data RGB according to the sampling signal input from the shift register 182, and supplies the stored digital data to the second latch 183.

The second latch 183 latches the data EFD and RGB input from the first latch 181, and then a second latch in another integrated circuit in response to the source output signal SOE from the timing controller 131. The digital data of one horizontal line latched together with 183 is simultaneously output. At this time, the source output signal SOE is generated approximately every one horizontal period, and each pulse width is constant.

The DAC 184 converts the digital data RGB from the second latch 183 according to the polarity signal POL from the timing controller 131 to the positive analog gamma voltage VPG or the negative analog gamma voltage VNG. Convert to In addition, the voltage generated from the DAC 184 controls the polarity of the data according to an inversion scheme such as a dot inversion, N dot inversion, line inversion, column inversion scheme, etc. in response to the polar line signal POL.

The buffer 185 outputs the analog gamma voltages VPG and VNG input from the DAC 184 to the data line DL without signal attenuation.

In Fig. 7, reference numeral 'R' denotes a line resistance between the output terminal of the data driving circuit 118 and the data line DL.

FIG. 8 shows a modulation gate control signal MGDC and a plurality of scan pulses SP generated therein according to a first embodiment of the present invention, and FIG. 9 shows a data voltage Vd in a liquid crystal cell Clc. Shows the charge level.

As shown in FIG. 8, the modulation gate control signal MGDC according to the first embodiment is a modulation gate shift clock MGSC and a modulation gate output enable signal MGEO. The modulation gate control signal MGDC is generated by the timing controller 114, and according to the counting value information CD stored in the memory 112, a first period T1 or a second period greater than the first period T1. Has (T2). The gate driving circuit 120 of FIG. 6 generates scan pulses SP1, SP2, SP4, etc. having the first pulse width W1 using the modulation gate control signal MGDC of the first period T1. The scan pulse SP3 having the second pulse width W2 is generated using the modulation gate control signal MGDC of the second period T2. The scan pulse SP3 having the second pulse width W2 is supplied to a specific horizontal line whose luminance is lower than that of other horizontal lines. As a result, the turn-on time of the TFTs connected to the specific horizontal line is increased, so that the charge amount Vd at the specific horizontal line with low charging capability is compensated as shown in FIG. 9 (b). FIG. 9A shows the charge amount Vd of the liquid crystal cells connected to the horizontal lines other than the specific horizontal line.

FIG. 10 shows a modulation gate control signal MGDC and a plurality of scan pulses SP generated therein according to a second embodiment of the present invention, and FIG. 11 shows a data voltage Vd of a liquid crystal cell Clc. Shows the charge level.

As shown in FIG. 10, the modulation gate control signal MGDC according to the second embodiment is a modulation gate shift clock MGSC, a modulation gate output enable signal MGEO, and a modulation gate modulation signal MFLK. For reference, the gate modulation signal FLK serves to reduce the amount of feed through voltage (ΔVp) generated by the parasitic capacitor Cgd between the gate electrode and the drain electrode of the TFT. Since the amount of the feed through voltage ΔVp is proportional to the difference between the gate high voltage Vgh and the gate low voltage Vgl (Vgh-Vgl), the gate modulation signal FLK is determined by the scan pulse. High division modulation reduces the magnitude of the differential voltage (Vgh-Vgl). The modulation gate control signal MGDC is generated by the timing controller 114 and according to the count value information CD stored in the memory 112, the second period greater than the first period T1 or the first period T1 ( T2). The gate driving circuit 120 of FIG. 6 generates scan pulses SP1, SP2, SP4, etc. having the first pulse width W1 using the modulation gate control signal MGDC of the first period T1. The scan pulse SP3 having the second pulse width W2 is generated using the modulation gate control signal MGDC of the second period T2. The scan pulse SP3 having the second pulse width W2 is supplied to a specific horizontal line whose luminance is lower than that of other horizontal lines. As a result, the turn-on time of the TFTs connected to the specific horizontal line is increased, so that the charge amount Vd at the specific horizontal line with low charging capability is compensated, as shown in FIG. FIG. 11A shows the charge amount Vd of the liquid crystal cells connected to the horizontal lines other than the specific horizontal line.

12 shows an image display unit in which a luminance difference for each line is compensated for.

13 is a flowchart illustrating a method of driving a liquid crystal display according to the present invention.

Referring to FIG. 13, a user supplies test data to data lines and scan pulses to gate lines to display a test image on an image display unit to detect luminance (S410 and S420).

The user determines a specific position in which the luminance is different from that in the image display section based on this test image (S430). A test luminance value is used as a reference value for this purpose.

When the specific position where the luminance is lowered is determined, the user stores the position information of the specific horizontal line and count value information indicating the pulse width of the scan pulse to be supplied to the gate line of this specific position in the memory of the liquid crystal display device. S440)

The timing controller generates a modulation gate control signal based on the position information and the count value information from the memory. Then, the gate driving circuit controls the pulse width of the scan pulse to be supplied to the specific position of the image display unit differently from that of the scan pulses to be supplied to the gate lines of the image display unit other than the specific position using this modulation gate control signal. (S450)

As described above, the liquid crystal display device and the driving method thereof according to the present invention modulate the gate control signal by controlling the timing controller using adjustable memory information, and use the modulated gate control signal to be supplied to a specific position. By varying the pulse width of the scan pulse, the display quality can be improved by compensating the line luminance in a specific horizontal line.

Furthermore, the liquid crystal display and the driving method thereof according to the present invention can prevent the redesign of the liquid crystal panel by compensating for the line defect caused by the characteristic difference of the liquid crystal through the modulation gate control signal.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (8)

An image display unit including a thin film transistor in an area where a plurality of data lines and a plurality of gate lines intersect, a plurality of liquid crystal cells are arranged in a matrix form, and where the plurality of data lines and the plurality of gate lines intersect; A gate driving circuit supplying scan pulses to the gate lines in response to gate control signals; A data driver circuit for supplying data voltages to the data lines; A memory for storing position information of a specific position of the image display unit and count value information indicating a pulse width of a scan pulse supplied to a gate line of the specific position; And A timing of controlling a pulse width of a scan pulse to be supplied to a specific position of the image display unit differently from that of scan pulses to be supplied to gate lines other than the specific position based on the position information and the count value information And a specific position is a position of a gate line having a lower luminance than other gate lines in the image display unit. The pulse width of the scan pulses to be supplied to the gate lines of the image display unit other than the specific position is a first pulse width, and the pulse width of the pulse of the scan pulse to be supplied to the specific position is a second pulse width, and the second And a pulse width is greater than the first pulse width. The method of claim 1, The count value information, First count value information indicating generation of a gate shift clock for determining a turn-on time of the thin film transistor; And And second count value information for instructing generation of a phosphorous output enable signal for controlling an output of the gate driver circuit. The method of claim 1, The count value information, First count value information indicating generation of a gate shift clock for determining a turn-on time of the thin film transistor; Second count value information indicating generation of a gate output enable signal for controlling the output of the gate driving circuit; And And third count value information instructing generation of a pulse modulation signal for controlling the high logic voltage output of the scan pulse. The method of claim 1, And the memory is built in the timing controller. The method of claim 1, And the memory is one of an electrically erasable programmable read only memory (EEPROM) and an extended display identification data ROM (EDID ROM) capable of erasing and updating the position information and the count value information. A liquid crystal display having an image display unit including a thin film transistor in a region where a plurality of data lines and a plurality of gate lines intersect, a plurality of liquid crystal cells are arranged in a matrix form, and where the plurality of data lines and the plurality of gate lines intersect. In the driving method of the device, Supplying test data to the data lines and supplying scan pulses to the gate lines to display a test image on the image display unit; Determining a specific position in which the luminance differs from other portions in the image display portion based on the test image; Storing position information of the specific position and count value information indicating a pulse width of the scan pulse to be supplied to the gate line of the specific position in a memory of the liquid crystal display; And The pulse width of the scan pulse to be supplied to a specific position of the image display unit based on the positional information from the memory and the count value information is different from that of the scan pulses to be supplied to the gate lines of the image display unit other than the specific position. And controlling the position, wherein the specific position is a position of a gate line having a lower luminance than other gate lines in the image display unit. The pulse width of the scan pulses to be supplied to the gate lines of the image display unit other than the specific position is a first pulse width, and the pulse width of the pulse of the scan pulse to be supplied to the specific position is a second pulse width, and the second The pulse width is larger than the first pulse width, the driving method of the liquid crystal display device. The method of claim 6, The count value information, First count value information indicating generation of a gate shift clock for determining a turn-on time of the thin film transistor; And And second count value information indicating generation of a gate output enable signal for controlling the output of the gate driving circuit. The method of claim 6, The count value information, First count value information indicating generation of a gate shift clock for determining a turn-on time of the thin film transistor; Second count value information indicating generation of a gate output enable signal for controlling the output of the gate driving circuit; And And third count value information for instructing generation of a pulse modulation signal for controlling the high logic voltage output of the scan pulse.

Images