KR101342438B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device which improves image display quality by improving delay distortion of a gate drive signal, and improves an abnormal image display phenomenon such as horizontal dim by improving a polling time delay phenomenon of a gate drive signal. There is an advantage of providing a display image of higher quality by providing sufficient image data writing time.

Description

[0001] Liquid crystal display device [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having improved image display quality by improving delay distortion of a gate driving signal.

Among display devices, liquid crystal display devices have advantages of small size, thinness and low power consumption and are used in notebook computers, office automation devices, audio / video devices, and the like. In particular, an active matrix type liquid crystal display device using a thin film transistor (hereinafter referred to as "TFT") as a switching element is suitable for displaying dynamic images.

FIG. 1 is a block diagram illustrating a general LCD device 100. For convenience of explanation, only a liquid crystal display panel 110, a plurality of source drivers SD1 to SD4, and a plurality of gate drivers GD1 to GD4 Respectively.

The liquid crystal display panel 110 is formed so that a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn cross each other, and a thin film transistor TFT and a liquid crystal capacitor are formed in the crossing area. Clc) and a storage capacitor Cst are defined as pixels.

The pixels are formed in a matrix form in each region where the plurality of data lines DL1 to DLm and the plurality of gate lines GL1 to GLn cross each other, and are arranged in a matrix form, and image data is written to the plurality of pixels to display an image. This area is called an active area (A / A).

The plurality of source drivers SD1 to SD4 output the image data D to the plurality of data lines DL1 to Dlm and provide the image data D to the liquid crystal display panel 110. The gate drivers GD1- GD4 sequentially output the gate driving signals Vg to the respective gate lines GL1 to GLn to control the switching of the thin film transistor TFT formed in each pixel so that the video data is written in the pixels to display the video do.

Of course, in addition to the above-described configuration, a general liquid crystal display device may provide image data and a plurality of control signals to the plurality of source drivers SD1 to SD4, and may supply the gate driving signals GD1 to GD4 to the gate drivers GD1 to GD4. And a gate output enable (GOE) signal for indicating an output of the liquid crystal display panel 110, a backlight unit unit for supplying light to the liquid crystal display panel 110, And a power supply unit.

In this basic configuration, the liquid crystal display faces each other of the liquid crystal display panel 110 in order to prevent distortion of the gate driving signal Vg caused by the RC component of the gate lines GD1 to GD4. The beam may be formed as a double bank type configured at each side end, in which case an increase in cost is caused by an additional configuration of a gate driver provided in the form of an integrated circuit (IC). The single bank type, which constitutes the gate driver only on one side of the side), is more efficient in terms of manufacturing cost reduction.

However, the biggest problem of the single bank type is a delay distortion phenomenon of the gate driving signal Vg applied to the gate lines GL1 to Gln.

A gate applied to each of the first and second pixels P1 and P2 of FIG. 1 when the low level voltage of the gate driving signal Vg is called Vgl and the high level voltage is Vgh. The driving signal Vg will be described with reference to the waveform of the gate driving signal Vg in FIG. 2.

The first pixel P1 of FIG. 1 is a pixel located at a first entrance portion to which the first gate driving signal Vg (1) is first applied from the gate driving units GD1 to GD4. Since it is not substantially affected by the RC component, waveform distortion of the first gate driving signal Vg (1) does not occur.

In contrast, the second pixel P2 is a pixel configured at the position furthest from the gate driving units GD1 to GD4, and is affected by the entire RC component of the nth gate line GLn.

Accordingly, a distorted waveform whose time is delayed in charging the thin film transistor TFT of the second pixel P2 to a voltage level that can be switched on and which is delayed even when completely turned off is generated. It becomes visible. The delay of the rising time and the falling time of the signal waveform due to the RC component is called an RC delay phenomenon.

Accordingly, in the second pixel P2, the timing for switching on the thin film transistor TFT, that is, the image data writing time DW2 is higher than the image data writing time DW1 of the first pixel P1. As a result, luminance decreases or horizontal dim occurs.

In addition, the gate driving signal distortion, which appears as the n-th gate driving signal {Vg (n)}, is more severely distorted toward the end of each gate line GL1 to GLn. Thus, the n-th gate driving signal The off timing of the thin film transistor TFT caused by the polling time delay of {Vg (n)} is delayed, causing an abnormal image to be expressed, such as image data of a next horizontal pixel column is input.

The present invention has been made to solve the above problems, and an object of the present invention is to improve image distortion caused by RC delay of a gate driving signal. In addition, another object of the present invention is to provide a more reliable image display quality by improving the polling timing delay problem of the gate driving signal and further securing the writing time of the image data.

In order to solve the above problems, the present invention includes a timing controller for outputting a plurality of control signals including digital image data and a gate output enable signal; A source port eastern section for receiving the digital image data and converting the digital image data into an analog voltage signal; A gate driver for outputting a gate driving signal according to the gate output enable signal; A data line to which the analog voltage signal is applied, a gate line intersecting the data line, and a gate driving signal applied thereto, and an intersection region of the data line and the gate line, and switching is controlled by the gate driving signal. A liquid crystal display panel including a liquid crystal pixel including a first thin film transistor, and a second thin film transistor outputting an off voltage of the first thin film transistor to the gate line; An off voltage supply unit supplying the off voltage to the second thin film transistor; A level shift circuit unit for outputting a switching control voltage for controlling the switching of the second thin film transistor by modulating the voltage level of the gate output enable signal.

The liquid crystal pixel further includes a liquid crystal capacitor and a storage capacitor connected to the first thin film transistor.

The first thin film transistor and the second thin film transistor are characterized in that the same MOS type.

The first thin film transistor and the second thin film transistor are both NMOS type.

The off voltage is a voltage for switching the first thin film transistor to an off switching state.

The off voltage is a low level voltage of the gate driving signal.

The switching control voltage is generated by boosting a high level voltage of the gate output enable signal.

The first thin film transistor and the second thin film transistor are on switching driving at different timings.

According to the present invention having the above-described characteristics, the polling time delay phenomenon of the gate driving signal generated in the single bank type liquid crystal display device is improved, thereby improving abnormal image display phenomenon such as horizontal dim and sufficient image data. There is an advantage of providing a display image of higher quality by providing a writing time.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of the LCD 200 according to the present invention. The timing controller 210, the source driver 220, the gate driver 230, and the liquid crystal display panel 240 are described. And an off voltage supply unit 250 and a level shift circuit unit 260.

Hereinafter, the configuration will be described, the timing controller 210 provides the digital image data input from the outside to the source driver 220, and the operation of the source driver 220 and the gate driver 230. Provide a plurality of control signals for controlling. In particular, the plurality of control signals further include a gate output enable (GOE) signal for controlling an output timing of the gate driving signal Vg output from the gate driver 230 to the liquid crystal display panel 240. Include.

The gate output enable signal is normally input at a high level voltage of about 3.3V and a low level voltage of about 0V. The gate driving signal Vg is a low level of the gate enable signal GOE. Is output to the liquid crystal display panel 240.

The source driver 220 may be configured in the form of an integrated circuit (IC), and receives digital image data from the timing controller 210, converts the digital image data into an analog voltage signal, and inputs the signal from the timing controller 210. The analog voltage signal is output to the liquid crystal display panel 240 according to a plurality of control signals.

The gate driver 230 outputs a gate drive signal Vg to the liquid crystal display panel 240 according to a gate output enable signal input from the timing controller 210, and also includes an integrated circuit IC. A plurality may be configured in the form or may be configured on the liquid crystal display panel 240.

Referring to FIG. 4, the liquid crystal display panel 240 crosses a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn in an active area A / A where image display is performed. The liquid crystal pixel P is formed in a region where the plurality of data lines DL1 to DLm and the plurality of gate lines GL1 to GLn cross each other.

The liquid crystal pixel P includes a first thin film transistor TFT1 and a liquid crystal capacitor connected to one data line of the plurality of data lines DL1 to DLm and one gate line of the plurality of gate lines GL1 to GLn. And a storage capacitor Cst.

The first thin film transistor TFT1 configured in each of the liquid crystal pixels P is switched and controlled by the gate driving signal Vg output from the gate driver 230, and output from the source driver 220. The signal is written to the liquid crystal capacitor Clc.

In the liquid crystal display panel 240, a second thin film transistor TFT2 is connected to an end of each gate line GL1 to GLn, and each of the second thin film transistors TFT2 is preferably the active region. (A / A) It is comprised in an external dummy area (D / A).

In addition, both of the first thin film transistor TFT1 and the second thin film transistor TFT2 are the same MOS type, preferably the NMOS type as shown.

The second thin film transistor TFT2 connected to the ends of the plurality of gate lines GL1 to GLn is switched and controlled by a signal output from the level shift circuit unit 260 at a gate terminal thereof. The off voltage Vgl supplied from the off voltage supply unit 250 is supplied.

The off voltage supply unit 250 supplies an off voltage Vgl to the second thin film transistor TFT2 of the liquid crystal display panel 240. The off voltage supply unit 250 may be a circuit unit configured separately, The off voltage Vgl may be supplied to each component of the display device 200 through a power supply unit for supplying operating power.

In addition, the off voltage Vgl is a voltage for switching control of the first thin film transistor TFT1 configured in each of the liquid crystal pixels P to the off state, and is a gate output from the gate driver 230. It is a low level voltage of the drive signal Vg.

The level shift circuit unit 260 supplies a switching control voltage Vsw for on / off switching of the second thin film transistor TFT2 of the liquid crystal display panel 240. As a level shifter, the gate driver 230 receives a gate output enable signal that controls the gate driver 230 to output a gate driving signal Vg, and outputs the switching control voltage Vsw.

That is, the gate output enable signal output from the timing controller 210 to the gate driver 230 includes a high level (about 3.3V) and a low level (about 0V). The voltage level of the high level voltage of the enable signal is modulated to output the switching control voltage Vsw of the second thin film transistor TFT2.

In addition, although not shown in the configuration diagram of FIG. 3, it is natural to include a backlight unit unit for supplying light to the liquid crystal display panel 240 and a separate power supply unit for supplying operation power to each component unit.

The operation of the liquid crystal display according to the present invention having the above-described configuration will be described with reference to the signal timing diagram of FIG. 5.

When an operation of the liquid crystal display is performed, the timing controller 210 outputs image data and a plurality of control signals to the source driver 220 and outputs a plurality of control signals including a gate output enable (GOE) signal. Output to the gate driver 230. In this case, the gate output enable signal (GOE) is also supplied to the level shift circuit unit 260.

First, in the section ①, in response to the input of the gate output enable (GOE) signal, the gate driver 230 sequentially performs the gate driving signal Vg on the plurality of gate lines GL1 to GLn of the liquid crystal display panel 240. ).

Next, in the section ②, the level shift circuit unit 260 step-up modulates the level of the high level voltage of the gate output enable (GOE) signal and applies it to the second thin film transistor TFT2. Accordingly, the second thin film transistor TFT2 is turned on so that the off voltage Vgl output from the off voltage supply unit 250 is applied to each of the gate lines GL1 to GLn.

As a result, the gate driving signal Vg applied to each of the gate lines GL1 to GLn is simultaneously switched off, and the first thin film transistor TFT1 is immediately switched off. Even liquid crystal pixels located far from the gate driver 230 and having an RC delay are switched off immediately without a delay in polling timing of the gate driver signal Vg.

As a result, the polling time delay of the gate driving signal Vg due to the RC component of the gate lines GL1 to GLn may cause the image data of the next horizontal pixel to be input or the horizontal dim phenomenon to be improved.

In addition, as shown in FIG. 6, a portion of the high level section of the gate output enable signal GOE to which the off voltage Vgl is applied to each of the gate lines GL1 to GLn is defined as a gate driving signal Vg. If it is further allocated to the low level section of the gate output enable signal applied to GL1 to GLn, when the image data writing time given in FIG. 5 is (DW3), it is allocated from the off voltage Vgl application time. The image data writing time becomes (DW3 + DW4) including the set time DW4.

That is, according to the present invention, the image data is written due to the delay of the rising time by not only improving the polling time delay phenomenon during the RC delay of the gate driving signal Vg but also reducing the polling time of the gate driving signal Vg. It can also improve the lack of time.

1 is a block diagram illustrating a general liquid crystal display device 100.

FIG. 2 is a waveform diagram of a gate driving signal Vg according to the operation of the liquid crystal display of FIG. 1.

3 is a block diagram showing the configuration of a liquid crystal display device 200 according to the present invention.

4 is a view for explaining the liquid crystal display panel 240 of the liquid crystal display device according to the present invention;

5 is a signal waveform diagram for explaining the operation of the liquid crystal display according to the present invention.

6 is a signal waveform diagram illustrating an application operation of the liquid crystal display device according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

210: timing controller 220: source driver

230: gate driver 240: liquid crystal display panel

250: off voltage supply unit 260: level shift circuit unit

Claims (8)

A timing controller for outputting a plurality of control signals including digital image data and a gate output enable signal; A source driver which receives the digital image data and converts the digital image data into an analog voltage signal; A gate driver for outputting a gate driving signal according to the gate output enable signal; A data line to which the analog voltage signal is applied, a gate line intersecting the data line, and a gate driving signal applied thereto, and an intersection region of the data line and the gate line, and switching is controlled by the gate driving signal. A liquid crystal display panel including a liquid crystal pixel including a first thin film transistor, and a second thin film transistor outputting an off voltage of the first thin film transistor to the gate line; An off voltage supply unit supplying the off voltage to the second thin film transistor; A level shift circuit unit for outputting a switching control voltage for controlling switching of the second thin film transistor by modulating a voltage level of the gate output enable signal A liquid crystal display The method according to claim 1, The liquid crystal pixel, A liquid crystal display further comprising a liquid crystal capacitor and a storage capacitor connected to the first thin film transistor. The method according to claim 1, And the first thin film transistor and the second thin film transistor are of the same MOS type. The method according to claim 3, The first thin film transistor and the second thin film transistor are both NMOS type liquid crystal display device, characterized in that The method according to claim 1, The off voltage is a voltage for switching the first thin film transistor to an off switching state. The method according to claim 5, And the off voltage is a low level voltage of the gate driving signal. The method according to claim 1, And the switching control voltage is generated by boosting a high level voltage of the gate output enable signal. The method according to claim 1, And the first thin film transistor and the second thin film transistor are switched on at different timings.

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