KR101341373B1 - Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods - Google Patents

Abstract

A method of forming a semiconductor device includes providing a substrate including a semiconductor material layer on an electrically insulating material layer. The first metallization layer is formed over the first side of the semiconductor material layer. The through wafer interconnect is formed to at least partially pass through the substrate. The second metallization layer is formed on the second side opposite the first side. A first metallization layer, a substrate, and a second between the first fabricated semiconductor structure supported by the substrate on the first side of the semiconductor material layer and the second fabricated semiconductor structure supported by the substrate on the first side of the semiconductor material layer An electrical path is provided that extends through the metallization layer. Semiconductor structures are fabricated using this method.

Description

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING TWO OR MORE PROCESSED SEMICONDUCTOR STRUCTURES CARRIED BY A COMMON SUBSTRATE , AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS}

Embodiments of the present invention generally relate to methods of forming a semiconductor device comprising two or more semiconductor structures bonded to a common substrate, and semiconductor devices formed by such methods.

3D integration of two or more semiconductor structures may provide many advantages over microelectronic applications. For example, 3D integration of microelectronic components can improve electrical performance and power consumption while reducing the area of the device footprint. See, e.g., P. Garrou, et al., "The Handbook of 3D Integration," Wiley-VCH (2008).

The 3D integration of semiconductor structures may include the attachment of a semiconductor die to one or more additional semiconductor die (i.e., die-to-die (D2D)), attachment of a semiconductor die to one or more semiconductor wafers D2W), and attachment of a semiconductor wafer to one or more additional semiconductor wafers (i.e., wafer-to-wafer W2W), or a combination thereof.

Often, individual semiconductor structures (eg, dies or wafers) are relatively thin and difficult to handle with equipment for processing semiconductor structures. Therefore, a so-called "carrier" die or wafer may be attached to substantial semiconductor structures that include active and passive components of an operative semiconductor device therein. The carrier die or wafer typically does not include any active or passive components of the semiconductor device to be formed. These carrier dies and wafers are referred to herein as "carrier substrates ". By processing equipment used to process active and / or passive components within semiconductor structures, carrier substrates increase the overall thickness of semiconductor structures (by providing structural support for relatively thin semiconductor structures). Facilitating the handling of the structures, the semiconductor structures will include active and passive components of the semiconductor device to be fabricated thereon. Such semiconductor structures are referred to herein as "device substrates," which will ultimately include active and / or passive components of the semiconductor device to be fabricated on the device substrate and upon completion of the manufacturing process. It will ultimately include active and / or passive components of the semiconductor device to be fabricated thereon.

The bonding techniques used to bond one semiconductor structure to another semiconductor structure can be classified in various manners, with one layer of intermediate material therebetween to bond the two semiconductor structures It is the first approach, depending on whether it is provided, and the second approach, depending on whether the bonding interface allows electrons (i.e., current) to pass through the interface. The so-called "direct bonding method" is a direct solid-to-solid chemical bonding between two semiconductor structures that bond them together without the use of intermediate bonding materials between the two semiconductor structures that bond them together. This is how a -to-solid chemical bond is built. A direct metal-to-metal bonding method has been developed to bond a metal material on the surface of a first semiconductor structure to a metal material on a surface of a second semiconductor structure.

The direct metal-to-metal bonding method may also be classified by the temperature range over which each method is performed. For example, some direct metal-to-metal bonding methods are performed at relatively high temperatures where at least partial melting of the metal material occurs at the bonding interface. Such direct bonding processes may not be desirable for use in bonded semiconductor structures involving one or more device structures because relatively high temperatures may adversely affect previously formed device structures to be.

A "thermo-compression" bonding process is a direct bonding process in which pressure is applied between bonding surfaces at a temperature of between 200 [deg.] C and about 500 [deg.] C, and often between about 300 [deg.] C and about 400 [

Additional direct bonding methods have been developed that can be performed at temperatures below 200 < 0 > C. This direct bonding process, which is performed herein at temperatures below 200 ° C, is referred to as the "ultra-low temperature" direct bonding process. The cryogenic direct bonding method can be performed by careful removal of surface impurities and surface compounds (e. G., Native oxides) and by increasing the intimate contact area between the two surfaces at the atomic scale. The intimate contact area between the two surfaces is generally achieved by applying pressure between the splicing surfaces so that plastic deformation occurs or by polishing the splicing surfaces by polishing the splicing surfaces to reduce surface roughness to values close to atomic scale And applying pressure to obtain such plastic deformation.

Some cryogenic direct bonding methods can be performed without applying pressure between the bonding surfaces at the bonding interface, but with other cryogenic direct bonding methods to achieve the appropriate bonding strength at the bonding interface, there is no pressure between the bonding surfaces at the bonding interface Can be applied. A cryogenic direct bonding method in which pressure is applied between bonding surfaces is conventionally referred to as "surface assisted bonding" or "SAB" methods. Thus, as used herein, the terms "surface torsion bonding" and "SAB" refer to a process by which a first material is bonded to a second material and a pressure is applied between the bonding surfaces at a bonding interface at a temperature of & And means a direct bonding process in which the first material is directly bonded to the second material.

The carrier substrate is typically attached to the element substrate using an adhesive. Similar bonding methods are used to secure one semiconductor structure that includes active and / or passive components of one or more semiconductor devices therein to another semiconductor structure that includes active and / or passive components of one or more semiconductor devices therein. Can be used.

The semiconductor die may have electrical connections that do not match the connections on other semiconductor structures to be connected. An interposer (i.e., additional structure) may be disposed between the two semiconductor structures or between the semiconductor die and the semiconductor package to reroute and align a suitable electrical connection. The interposer may have one or more conductive traces and vias used to form a suitable contact between the desired semiconductor structures.

Embodiments of the present disclosure may provide methods and structures for forming semiconductor devices that include two or more semiconductor structures and are supported by a common substrate. Electrical connections through a common substrate between two or more semiconductor structures may be provided. This Summary is provided to introduce a selection of concepts in a simplified form, further describing the detailed description of the embodiments herein. This Summary is not intended to identify key features or essential features of the claims, nor is it intended to be used to limit the scope of the claims.

In some embodiments , the present invention includes a method of forming a semiconductor device. According to this method, the substrate may be provided comprising a semiconductor material layer on the electrically insulating material layer. A first metallization layer comprising a plurality of electrically conductive features can be formed on a substrate on the first side of the semiconductor material layer opposite the electrically insulating material layer. The plurality of through wafer interconnects may be formed at least partially through the substrate. One or more through wafer interconnects may be formed to extend through each of the metallization layer and the semiconductor material layer. A second metallization layer comprising a plurality of electrically conductive features can be formed on the substrate on the second side of the semiconductor material layer opposite the first side of the semiconductor material layer. The electrical path is formed by the first metallization layer, the substrate between the first fabricated semiconductor structure supported by the substrate on the first side of the semiconductor material layer and the second fabricated semiconductor structure supported by the substrate on the first side of the semiconductor material layer. And (eg are formed) extending continuously through the second metallization layer.

In further embodiments, the present invention includes semiconductor structures formed using the methods described herein. For example, in further embodiments, the present invention provides a substrate comprising a semiconductor material layer, a first metallization layer on a substrate over a first side of the semiconductor material layer, and a semiconductor material opposite the first side of the semiconductor material layer. A semiconductor device comprising a second metallization layer on a substrate over a second side of the layer. The plurality of through wafer interconnects extend at least partially through each of the first metallization layer and the semiconductor material layer of the substrate. The first processed semiconductor structure may be supported by a substrate on the first side of the semiconductor material layer, and the second processed semiconductor structure may also be supported by the substrate on the first side of the semiconductor material layer. One or more electrical paths are from the first fabricated semiconductor structure, through the conductive features of the first metallization layer, through the first through wafer interconnects of the plurality of through wafer interconnects, through the conductive features of the second metallization layer, and in plurality Extend through the second through wafer interconnect of the through wafer interconnect to the second fabricated semiconductor structure.

Embodiments of the present invention will be more fully understood with reference to the following detailed description of the embodiments of the present invention and the accompanying drawings:
1 is a simplified cross-sectional view of an insulator-phase-semiconductor (SeOI) substrate that may be used in embodiments of the method of the present invention;
2 is a simplified cross-sectional view illustrating a method that can be used to fabricate the SeOI substrate of FIG. 1;
3 is a simplified plan view of the SeOI substrate of FIG. 1 schematically showing a plurality of fabricated semiconductor structures thereon;
4 is a simplified cross-sectional view schematically illustrating a plurality of transistors formed in and on a semiconductor material layer of the SeOI substrate of FIG. 1;
FIG. 5 is a simplified cross-sectional view schematically showing a first side of a semiconductor material layer of the SeOI substrate of FIG. 1 and a first metallization layer formed over a transistor; FIG.
6A-6F illustrate an embodiment of a method of the present invention that can be used to form a structure that includes two or more fabricated semiconductor structures supported by the structure of FIG. 5 and to electrically interconnect two or more fabricated semiconductor structures. Used to illustrate them;
FIG. 6A illustrates the fabrication of through wafer interconnect through the semiconductor material layer and the first metallization layer of the SeOI substrate shown in FIG. 5;
FIG. 6B shows the bonding of the carrier substrate onto the first metallization layer on the side opposite the SeOI substrate; FIG.
6C illustrates removal of a portion of a SeOI substrate to expose a through wafer interconnect through the structure on a side opposite the carrier substrate;
FIG. 6D shows a second metallization layer formed over the semiconductor material layer of the SeOI substrate on a side opposite the first metallization layer; FIG.
6E illustrates removal of the carrier wafer and other portions of the structure shown in FIG. 6D;
FIG. 6F illustrates a further processed semiconductor structure bonded to and electrically coupled to the structure of FIG. 6E over the first side of the semiconductor material layer of the SeOI substrate, and further on the second side of the semiconductor material layer of the SeOI substrate. Illustrating junction and electrical coupling of another substrate and semiconductor structure;
7A-7F are similar to FIGS. 6A-6F and may be used to form a structure comprising two or more processed semiconductor structures supported by the structure of FIG. 5, and to electrically interconnect two or more processed semiconductor structures. Used to show further embodiments of the present method, wherein the electrically insulating material layer of the SeOI substrate is not removed during the present process;
FIG. 8 is a schematic of a first side of the semiconductor material layer of the SeOI substrate of FIG. 1 and a first metallization layer formed over the transistor, similar to FIG. 5, including the region of the SeOI substrate where no transistor is formed;
9A-9F are similar to FIGS. 6A-6F and may be used to form a structure comprising two or more processed semiconductor structures supported by the structure of FIG. 8 and to electrically interconnect two or more processed semiconductor structures. Used to show additional embodiments of the present method, wherein the electrically insulating material layer of the SeOI substrate is removed during the present process;
10A-10F are similar to FIGS. 9A-9F and may be used to form a structure comprising two or more processed semiconductor structures supported by the structure of FIG. 8 and to electrically interconnect two or more processed semiconductor structures. Used to show further embodiments of the present method, wherein the electrically insulating material layer of the SeOI substrate is not removed during the present process;
FIG. 11 is a simplified cross-sectional view of a fabricated semiconductor structure similar to that shown in FIG. 10F, but directly bonded to the first metallization layer on the first side of the SeOI substrate, and on the second side of the SeOI substrate; Shows another substrate bonded directly to the layer;
FIG. 12 is a simplified cross-sectional view of a fabricated semiconductor structure similar to that shown in FIG. 7F, but with a direct bonded fabricated semiconductor structure on the first side of the SeOI substrate and another substrate bonded directly to the metallization layer on the second side of the SeOI substrate. Illustrated.

The examples provided herein do not imply actual aspects of a particular material, element, system, or method, but correspond to ideal representative features used to describe the embodiments herein.

Headings used herein should not be construed as limiting the scope of the embodiments of the invention as defined by the following claims and their legal equivalents. The concepts described in certain names can be generally applied in different areas throughout the specification.

A plurality of references are cited herein, the entire disclosure of which is incorporated herein by reference for all purposes. Moreover, none of the cited references, regardless of how it is characterized herein, is recognized as prior art on the subject matter claimed herein.

As used herein, the term "semiconductor device" includes one or more semiconductor materials capable of performing one or more functions when properly and functionally integrated into an electronic or optoelectronic device or system. It means and includes an operative device. Semiconductor devices include electronic signal processors, memory devices (e.g., random access memory random access memory (RAM), dynamic random access memory (DRAM), flash memory, etc.), optoelectronic devices (e.g., light emitting diodes, laser light emission). Diodes, solar cells, etc.), and elements including, but not limited to, two or more such elements in operative connection with one another.

As used herein, the term " semiconductor structure " means and includes any structure used or formed during semiconductor device manufacturing. Semiconductor structures include, for example, assemblies or composite structures that include two or more die and / or wafers that are three-dimensionally integrated with each other, as well as die and wafer (e.g., carrier substrate and device substrate). Semiconductor structures also include fully fabricated semiconductor devices as well as intermediate structures formed during semiconductor device fabrication.

As used herein, the term "processed semiconductor structure " means and includes a semiconductor structure that includes one or more device structures formed at least partially. The processed semiconductor structure is a subset of the semiconductor structure, and all of the processed semiconductor structures are semiconductor structures.

As used herein, the term "bonded semiconductor structure" means and includes any structure that includes two or more semiconductor structures attached together. The junction semiconductor structure is a subset of the semiconductor structure, and all of the junction semiconductor structures are semiconductor structures. A bonded semiconductor structure including at least one processed semiconductor structure is also a processed semiconductor structure.

As used herein, the term “device structure” means and includes a portion of a processed semiconductor structure that includes or defines at least a portion of an active or passive component of a semiconductor device formed on or in the semiconductor structure. do. For example, device structures include active and passive components of integrated circuits, such as transistors, transducers, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.

As used herein, the term "through wafer interconnect" or "TWI" refers to the relationship between the first semiconductor structure and the second semiconductor structure across the interface between the first semiconductor structure and the second semiconductor structure. And means conductive vias extending through at least a portion of the first semiconductor structure used to provide structural and / or electrical connections to the substrate. Through wafer interconnect is also referred to in the art as other terms such as "through silicon / substrate vias" or "TSVs" and "through wafer vias" or "TWVs". The TWI typically extends through the semiconductor structure in a direction substantially perpendicular to the approximately planar major surface of the semiconductor structure (in a direction parallel to the Z axis) through the semiconductor structure.

As used herein, the term "active surface", when used in connection with a fabricated semiconductor structure, is intended to form one or more device structures within and / or on an exposed major surface of the fabricated semiconductor structure. By processed or to be processed, is meant and includes an exposed major surface of a processed semiconductor structure.

As used herein, the term "metallization layer" refers to one or more of conductive lines, conductive vias, and conductive contact pads, which are used to conduct current along at least a portion of the electrical path. Means and includes a layer of a processed semiconductor structure that includes.

As used herein, the term "back surface" when used in connection with a processed semiconductor structure means that the exposed surface of the processed semiconductor structure on the opposite side of the processed semiconductor structure from the active surface of the semiconductor structure Quot; means < / RTI >

As used herein, the term "III-V type semiconductor material" includes at least one element from group IIIA (B, Al, Ga, In, Ti) of the periodic table, , As, Sb, Bi)). ≪ / RTI >

Embodiments herein include methods and structures for forming a semiconductor structure, and more specifically, include semiconductor structures including junction semiconductor structures and methods for forming such junction semiconductor structures.

In some embodiments, the through wafer interconnect is formed through at least a portion of a semiconductor-on-insulator (SeOI) substrate, and one or more metallization layers are formed over at least a portion of the SeOI substrate. The processing semiconductor structure (eg, semiconductor device) may be supported by at least a portion of the SeOI substrate, and electrical pathways between the processing semiconductor structures (and optionally, other structures or substrates) may be It can be performed using the conductive features of the metallization layer and through wafer interconnect. Embodiments of the methods and structures herein may be used for various purposes, for example for 3D integration processes and to form 3D integration structures.

1 illustrates a substrate 100 that can be incorporated into embodiments herein. Substrate 100 includes a relatively thin layer of semiconductor material 104. In some embodiments, the semiconductor material layer 104 may be at least substantially single crystal semiconductor material.

By way of example and not limitation, the semiconductor material layer 104 may comprise single crystal silicon, germanium, or III-V semiconductor material, and may or may not be doped. In some embodiments, the semiconductor material layer 104 may include an epitaxial layer made of a semiconductor material.

In some embodiments, the semiconductor material layer 104 may have an average total thickness of about 1 μm or less, about 500 nm or less, or even about 10 nm or less.

Optionally, a layer of semiconductor material may be disposed over and supported by the base 106. By way of example and not limitation, the base 106 may comprise oxides (eg, silicon oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), nitrides (eg, silicon nitride (Si ₃ N ₄ ) or nitride One or more dielectric materials, such as boron (BN)). In further embodiments, base 106 may comprise a semiconductor material, such as any of those described above with respect to semiconductor material 104. In some embodiments base 106 may comprise a multilayer structure comprising two or more different materials.

In some embodiments, the substrate 100 may include what is conventionally referred to as a "semiconductor-on-insulator" type substrate. For example, substrate 100 may include what is conventionally referred to as a " silicon-on-insulator " type substrate. In such embodiments, an electrically insulating material layer 105 may be disposed between the semiconductor material layer 104 and the base 106. Electrically insulating material 105 may include what is conventionally referred to as a "buried oxide" layer (BOX). The electrically insulating material 105 may be, for example, nitride (silicon nitride (eg, Si ₃ N ₄ )) or oxide (eg, silicon oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )). It may include a ceramic material. In some embodiments, the electrically insulating material layer 105 may have an average total thickness of about 1 μm or less, about 300 nm or less, or even about 10 nm or less.

As a non-limiting example, the substrate 100 shown in FIG. 1 may be formed using a process conventionally referred to as a SMART-CUT ™ process. For example, as shown in FIG. 2, a relatively thick layer of semiconductor material 104 ′ may be bonded to the exposed major surface 107 of the electrically insulating material layer 105. The relatively thick semiconductor material layer 104 'may have the same composition as that of the semiconductor material layer 104 provided over the base 106, and the semiconductor material layer 104 may have a relatively thick semiconductor material layer 104'. And may comprise a relatively thin portion of the layer 104 '.

In some embodiments, a bonding material (not shown) may be used to bond the relatively thick semiconductor material layer 104 ′ to the major surface 107 of the electrically insulating material layer 105. Such a bonding material may include, for example, one or more of silicon oxide, silicon nitride, and mixtures thereof. Such a bonding material may be formed or provided on either or both of the opposing surfaces of the electrically insulating material layer 105 and the relatively thick semiconductor material layer 104 ′ to improve the bonding between the surfaces. .

In some embodiments, the relatively thick semiconductor material layer 104 ′ may be bonded to the electrically insulating material layer 105 at a temperature of about 400 ° C. or less, or even about 350 ° C. or less. However, in other embodiments, the bonding process can be performed at higher temperatures.

After bonding the relatively thick semiconductor material layer 104 'to the electrically insulating material layer 105, the relatively thick semiconductor material layer 104' may be thinned to form a relatively thin layer of the semiconductor 104 of FIG. Can be. A portion 110 of the relatively thick semiconductor material layer 104 ′ may be removed from the relatively thin semiconductor material layer 104, with the relatively thin layer of semiconductor material on the surface 107 of the electrically insulating material 105. (104) remains.

By way of example and not limitation, SMART may be used to separate portions 110 of the relatively thin semiconductor material layer 104, electrically insulating material 105, and the relatively thick semiconductor material layer 104 ′ from the base 106. The -CUT ™ process can be used. Such a process is described, for example, in US Patent RE39,484 (inventor: Bruel, published February 6, 2007), US 6,303,468 (invented by Aspar, published October 16, 2001), United States Patent 6,335,258 (Inventor: Aspar et al., Issue Date: January 1, 2002), US Patent 6,756,286 (Inventor: Moriceau et al., Publication Date: June 29, 2004), US Patent 6,809,044 (Inventor: Aspar et al., Publication Date : October 26, 2004), and US Pat. No. 6,946,365 (Inventor: Aspar et al., Published September 20, 2005), the disclosures of which are incorporated herein by reference in their entirety.

Briefly, a plurality of ions (eg, one or more of hydrogen, helium, or inert gas ions) may be implanted into the semiconductor material layer 104 ′ along the ion implantation surface 112. In some embodiments, a plurality of ions may be implanted into the semiconductor material layer 104 ′ before bonding the semiconductor material layer 104 ′ to the electrically insulating material layer 105 and the base 106.

Ions may be implanted along a direction substantially perpendicular to the semiconductor material layer 104 ′. As is known in the art, the depth at which ions are implanted into the semiconductor material layer 104 'is, at least in part, a function of the energy involved in implanting ions into the semiconductor material layer 104'. In general, ions implanted with less energy will be implanted at relatively shallow depths, and ions implanted with higher energies will be implanted at relatively deep depths.

Ions may be implanted into the semiconductor material layer 104 'with a predetermined energy selected to implant ions into the semiconductor material layer 104' to a desired depth. Ions may be implanted into the semiconductor material layer 104 ′ before or after bonding the semiconductor material layer 104 ′ to the electrically insulating material layer 105 and the base 106. As one non-limiting particular example, the semiconductor material layer 104 such that the average thickness of the relatively thin semiconductor material layer 104 ranges from approximately one thousand nanometers (1,000 nm) to approximately one hundred nanometers (10 nm). Within ') an ion implantation face 112 may be disposed at some depth from its surface. As is known in the art, inevitably at least some ions may be implanted at a depth other than the desired implantation depth, and ions as a function of the inner depth of the semiconductor material layer 104 'from the surface of the semiconductor material layer 104'. The graph of concentrations (eg, prior to conjugation) may represent a generally bell-shaped (symmetric or asymmetric) curve with a maximum at the desired injection depth.

After ion implantation into the semiconductor material layer 104 ′, ions may define an ion implantation face 112 (shown in dashed lines in FIG. 2) within the semiconductor material layer 104 ′. Ion implantation surface 112 may include one layer (or region) in semiconductor material layer 104 'aligned to (eg, approximately concentrated) the surface of the maximum ion concentration in semiconductor material layer 104'. have. Ion implantation face 112 may define a zone of weakness within semiconductor material layer 104 'along which semiconductor material layer 104' may be cleaved or cracked in subsequent processing. It can be structured. For example, the semiconductor material layer 104 ′ may be heated to split or split along the ion implantation surface 112. In some embodiments, during the cleaving process, the temperature of the semiconductor material layer 104 ′ may be maintained at about 400 ° C. or less, or even about 350 ° C. or less. However, in other embodiments, the cleaving process can be performed at higher temperatures. Optionally, mechanical forces may be applied to the semiconductor material layer 104 ′ to cause or assist in cleavage of the semiconductor material layer 104 ′ along the ion implantation surface 112.

In further embodiments, a relatively thick layer of semiconductor material 104 ′ (eg, a layer having an average thickness greater than about 100 microns) is bonded to the electrically insulating material layer 105 and the base 106, and then By thinning the relatively thick layer of semiconductor material 104 ′ from the side opposite the base 106, the layer of electrically insulating material 105 and the relatively thin layer of semiconductor material 104 can be provided on the base 106. . For example, the relatively thick layer of semiconductor material 104 'may be thinned by removing material from the exposed major surface of the relatively thick layer of semiconductor material 104'. Relatively thick, for example, using chemical processes (eg wet or dry chemical etching processes), mechanical processes (eg grinding or polishing processes), or by chemical-mechanical polishing (CMP) processes Material may be removed from the exposed major surface of the semiconductor material layer 104 ′. In some embodiments, this process may be performed at a temperature of about 400 ° C. or less, or even about 350 ° C. or less. However, in other embodiments, this process may be performed at higher temperatures.

In still another further embodiment, a relatively thin layer of semiconductor material 104 is in-situ on the surface 107 of the electrically insulating material layer (105) (in situ ) can be formed. For example, the substrate 100 of FIG. 1 may be formed by depositing a semiconductor material, such as silicon, polysilicon, or amorphous silicon, on the surface 107 of the electrically insulating material layer 105 to a desired thickness. Can be. In some embodiments, the deposition process may be performed at a temperature of about 400 ° C. or less, or even about 350 ° C. or less. For example, the low temperature deposition process for forming the relatively thin semiconductor material layer 104 may be performed using a plasma enhanced chemical vapor deposition process as is known in the art. However, in other embodiments, the deposition process may be performed at higher temperatures.

In some embodiments, the substrate 100 of FIG. 1 may include a relatively small die level structure. In other embodiments, the substrate 100 may comprise a relatively larger wafer having an average diameter of at least about 100 millimeters, at least about 300 millimeters, or even at least about 400 millimeters. In such embodiments, as shown in the schematic diagram of FIG. 3, a plurality of processed semiconductor structures 120 may be fabricated in and on various regions of the substrate 100. The plurality of processed semiconductor structures 120 may be arranged in an ordered array or grid pattern on the substrate 100.

Examples of methods that can be used to fabricate a processed semiconductor structure 120 using the substrate 100 are described below with reference to FIGS. 4-5.

Referring to FIG. 4, a plurality of transistors 122 may be formed in and over selected regions of the semiconductor material layer 104 corresponding to the regions where the processed semiconductor structure 120 (FIG. 3) is formed. 4 schematically shows a transistor 122. As is known in the art, each transistor 122 may include a source region and a drain region, separated by a channel region. The source, drain, and channel regions may be formed in the semiconductor material layer 104. The gate structure may be formed over the semiconductor material layer 104 vertically over the channel region between the source and drain regions. Although only three transistors 122 are shown in FIG. 4 for simplicity, in practice, each processed semiconductor structure 122 may include thousands, millions, or even more transistors 122. .

Referring to FIG. 5, a first metallization layer 124 may be formed on the first side of the semiconductor material layer 104 opposite the electrically insulating material layer 105. The first metallization layer 124 includes a plurality of electrically conductive features 126. The plurality of electrically conductive features 126 may include one or more vertically extending conductive vias, laterally extending conductive traces, and conductive contact pads. At least some of the conductive features 126 may be in electrical contact with corresponding features, such as source regions, drain regions, and gate structures of the transistor 122. Conductive features 126 may be formed of metal and may include metal. The first metallization layer 124 can be formed by a layer-by-layer process, where alternating metal layers and dielectric material 125 form conductive features 126. Deposited and patterned, these features are inherent in and surrounded by dielectric material 125. Conductive features 126 may be used to route or redistribute electrical pathways from the location of various active components of transistor 122 to other locations spaced therefrom. Therefore, in some embodiments, the first metallization layer 124 may include what is conventionally referred to as a redistribution layer (RDL).

In the embodiments of FIG. 5, conductive features 126 are formed in the first metallization layer 124 over regions of the substrate 100 where the transistors 122 are not formed (commonly referred to as active regions). However, it is not formed on other substrate 100 regions (commonly referred to as inactive regions) that do not contain any transistor 122.

6A-6F illustrate the fabrication of the junction semiconductor structure shown in FIG. 6F, which may comprise two or more fabricated semiconductor structures (eg, semiconductor elements) supported by a portion of the substrate 100. Include. In addition, a portion of the substrate 100 is used to provide a direct, continuous electrical path between two or more processing semiconductor structures through the portion of the SeOI substrate 100.

The methods of embodiments herein can use the fabricated semiconductor structure 120 of FIG. 5.

Next, referring to FIG. 6A, the carrier substrate 140 may optionally be temporarily bonded to the exposed major surface 128 of the first metallization layer 124 of the fabricated semiconductor structure of FIG. 5. The carrier substrate 140 may be used to facilitate handling of the semiconductor structure by the processing equipment during subsequent manufacturing processes.

After bonding the carrier substrate 140 to the first metallization layer 124, the base 106 and the electrically insulating material layer 105 of the substrate 100 may be removed to form the structure shown in FIG. 6B. . The base 106 and the electrically insulating material layer 105 of the substrate 100 may be subjected to, for example, chemical processes (eg, wet or dry chemical etching processes), mechanical processes (eg, grinding or polishing processes). May be removed using a chemical or mechanical polishing (CMP) process.

After removal of the base 106 and the electrically insulating material layer 105, a plurality of through wafer interconnects 130 are at least partially through the semiconductor material layer 104, at least partially in the dielectric material. Through 125 and in the active device region, the structure shown in FIG. 6C can be formed. After etching the holes or vias, through the semiconductor material layer 104, at least partially through the dielectric material 125, and disposed in the active device area, the holes or vias are removed. Through filling the electrically conductive materials (eg, copper or copper alloy), or by other methods known in the art, through wafer interconnects 130 may be formed. For example, one or more through wafer interconnects 130 may be formed to extend completely through the first metallization layer 124 and the semiconductor material layer 104 to the carrier substrate 140. The carrier substrate 140 serves as an etch-stop layer in an etching process used to form holes or vias that are ultimately filled with one or more electrically conductive materials to form the through wafer interconnect 130. Can be used. It should be noted that in some embodiments of the present disclosure, electrically conductive features 126 may also act as an etch-stop layer in the etching process used to form the holes or vias.

At least a portion of the through wafer interconnects 130 may be in contact with the conductive features 126 of the metallization layer 126, and thus are in electrical contact with one or more active element features of the transistors 122.

By way of example and not limitation, one or more masks and etching processes may be used to form the holes or vias, and one or more electroless plating process and electrolytic plating process may remove the holes or vias. Can be used to fill with conductive material. In some embodiments, each of the processes used for forming the through wafer interconnect 130, including forming holes or vias and filling the holes or vias with an electrically conductive material, are about 400 ° C. or less. Or even at a temperature of about 350 ° C. or less. However, in other embodiments, these processes may be performed at higher temperatures. For example, in embodiments in which copper may be used in the back-end of line (BEOL) process used to form through wafer interconnects, the temperature will not exceed approximately 400 ° C., Alternatively, in embodiments in which aluminum may be used in the BEOL process used to form the through wafer interconnect, the temperature may exceed approximately 400 ° C.

Referring to FIG. 6D, after removing the base 106 and the electrically insulating material layer 105, defining holes or vias, the first side of the semiconductor material layer 104 having the first metallization layer 124 formed thereon. A second metallization layer 154 may be formed on the second side of the semiconductor material layer 104 opposite. The view of FIG. 6D is inverted relative to the view of FIGS. 6A-6C, in which the structure is reversed to facilitate formation of the second metallization layer 154 on the second side opposite the semiconductor material layer 104. Because.

The second metallization layer 154 is similar to the first metallization layer 124 and includes a plurality of electrically conductive features 156. The plurality of electrically conductive features 156 may include one or more vertically extending conductive vias, horizontally extending conductive traces, and conductive contact pads. At least a portion of the conductive features 156 may be in electrical contact with the through wafer interconnects 130, thus the conductive regions 126 and the active region of the transistors 122 of the first metallization layer 124. (Eg, source regions, drain regions, and gate structures) may also be in electrical contact. Conductive features 156 may be formed of metal and include metal. The second metallization layer 154, like the first metallization layer 124, is a layer-by-layer process, for example, via a commonly known damascene process. Alternating metal layers and dielectric material 125 are deposited and patterned in such a manner as to form conductive features 156, which are embedded in and surrounded by the dielectric material. Conductive features 156 route electrical pathways from the point where through wafer interconnects 130 are exposed through the second side of semiconductor material layer 104 to other points spaced therefrom. It can be used to route or redistribute. Therefore, in some embodiments, the second metallization layer 154 may include what is conventionally referred to as a redistribution layer (RDL).

Additionally, as shown in FIG. 6D, some of the conductive features 156 of the second metallization layer 154 may have two or more through wafer interconnects exposed on the second side of the semiconductor material layer 104. Between the ends of 130, it may provide a direct and continuous electrical connection through the second metallization layer 154.

FIG. 6E shows the semiconductor structure inverted once again, so the second metallization layer 154 is disposed at the bottom of the semiconductor structure from the view of FIG. 6D. After formation of the conductive features 156 of the second metallization layer 154, the dielectric material 125 may be removed in some regions of the first metallization layer 124. Regions of the first metallization layer 124 that are removed may include dielectric material 125 in inactive regions, ie, regions without any active elements. Dielectric material 125 may be removed through an etching process such as, for example, dry etching (eg, reactive ion etching) or wet etching. To remove the dielectric material 125 in the inactive region of the processed semiconductor structure, a processed structure as shown in FIG. 6D may be detached from the carrier substrate 140 and attached to an additional carrier (not shown). . The additional carrier may be attached to the second metallization layer 154. Upon removal of dielectric material 125 from the inactive region of the fabricated semiconductor structure, vias 156 ′ of second metallization 154 are exposed as shown in FIG. 6E.

After removing a portion of dielectric material 125 and exposing vias 156 ', the fabricated semiconductor structure of FIG. 6E is diced. In addition, the die can be electrically tested and mounted on a package with a known good die (KGD) using bump technology. Subsequently, on the interposer of FIG. 6E, above the active elements (ie within the active regions) and above the inactive elements (ie within the inactive regions), an additional die (such as using similar or different functionality or similar or different techniques). Manufactured using C) can be laminated using micro-bump technology.

Silicon-on-insulator (SOI) interposers, as used in embodiments herein, provide a fan-out, typically required to match the electrical routing between the interposer and the device package, in a cost-effective manner. Note that it helps to provide fan-out (or redistribution) layers. Alternatively, the general method of shrinking package routing to match device routing adds significant cost to device packages. Therefore, an SOI interposer provides inactive regions that may have additional dies (or additional die piles) from similar or different technologies that are stacked and connected to a package through the same electrical routing.

Thus, as more particularly, in this step of the process, the one or more semiconductor processing structure 120. As shown in Figure 6e in situ (in situ ) may be formed in and on the semiconductor material layer 104 (ie, the remaining portion of the substrate 100) of the substrate 100. Such fabricated semiconductor structures 120 may be supported by a semiconductor material layer 104. One or more processing semiconductor structures 120 may include, for example, electronic signal processors, electronic memory devices, and / or optoelectronic devices (eg, light emitting diodes, laser light emitting diodes, solar cells, etc.). have.

Referring to FIG. 6F, one or more additional fabricated semiconductor structures, such as fabricated semiconductor structure 160A and fabricated semiconductor structure 160B, are formed on the first side of semiconductor material layer 104 and through wafer interconnect 130 and vias 156. The bonded semiconductor structure shown in FIG. 6F can be formed by structurally and electrically coupling to the exposed ends of '). Additional processing semiconductor structure (160A, 160B) is in the layer of semiconductor material 104 and in-situ thereon (in situ ) and may be supported by a layer of semiconductor material 104 that is on a side in common with the formed semiconductor structure 120.

Each of the additional processed semiconductor structures 160A, 160B may comprise a semiconductor device, such as an electronic signal processor, an electronic memory device, and / or an optoelectronic device (eg, a light emitting diode, a laser light emitting diode, a solar cell, etc.). have. As a non-limiting example, the processed semiconductor structure 120 formed in situ may include an electronic signal processor device, and each of the additional processed semiconductor structures 160A, 160B may be an electronic memory device, a light emitting device. And at least one of a diode, a laser light emitting diode, and a solar cell.

In some embodiments, conductive features, such as conductive pads, of additional fabricated semiconductor structures 160A, 160B are each using conductive solder micro-bumps (balls) 162, for example, as is known in the art. May be structurally and electrically connected to through wafer interconnects 130 and vias 156 ′. In addition, additional fabricated semiconductor structures 160A, 160B may include interposers and electrical routing structures as manufactured by the methods herein described above.

One or more electrical paths may be provided by electrically connecting additional fabricated semiconductor structures 160A, 160B to through wafer interconnect 130 and vias 156 ′, which paths may include first metallization layer 124. ), The remaining portion of the substrate 100 (ie, through the semiconductor material layer 104 past the through wafer interconnects 130 and vias 156 ′), and the processing semiconductor structure 120 and each additional processing. The second metallization layer 154 between the semiconductor structures 160A and 160B extends through the continuous structure. Such electrical paths may be used to transfer electronic signals and / or power between the processing semiconductor structures 120, 160A, 160B. Therefore, the process semiconductor structures 120, 160A, 160B can be designed and configured to work together as a single semiconductor package device.

As also shown in FIG. 6F, the conductive features 156 of the second metallization layer 154 may be structurally and electrically connected to other features of higher structure, such as another substrate 170. Can be. The substrate 170 may include, for example, an organic printed circuit board, and may include a package level substrate. The conductive features 156 of the second metallization layer 154 are structurally and electrically connected to the conductive features of the substrate 170 using, for example, conductive solder bumps (balls) 172, as is known in the art. Can be electrically connected. Between the processing semiconductor structures 120, 160A, 160B, the first metallization layer 124, the through wafer interconnect 130, and the second metallization layer 154 lead to the conductive features of the additional substrate 170. Electrical paths may also be provided, and these additional electrical paths may also be used to transport power and / or electrical signals between them.

7A-7F are similar views of FIGS. 6A-6F, illustrating additional embodiments of the methods herein that may be used to form a junction semiconductor structure including two or more fabricated semiconductor structures supported by the structure of FIG. 5. Used to illustrate. However, in the embodiments of FIGS. 7A-7F, the electrically insulating material layer 105 of the substrate 100 is not removed during processing, as in the embodiments of FIGS. 6A-6F. The method processes of FIGS. 7A-7F are approximately identical to the methods described above with respect to FIGS. 6A-6F, and the detailed descriptions described above are not repeated below.

The methods of further embodiments herein may again utilize the processed semiconductor structure 120 as shown in FIG. 7A.

As shown in FIG. 7B, the carrier substrate 140 may optionally be temporarily bonded to the exposed major surface 128 of the first metallization layer 124. After bonding the carrier substrate 140 to the first metallization layer 124, the base 106 of the substrate 100 is removed from the structure, leaving behind the semiconductor material layer 104 and the electrically insulating material layer 105. Can be. A plurality of through wafer interconnects 130 are formed through the first metallization layer 124, through the semiconductor material layer 104, and also through the electrically insulating material layer 105, thereby providing a method of FIG. 7C. The illustrated structure can be formed. In such methods, the carrier substrate 140 may be used as an etch-stop layer in an etching process used to form holes or vias that are finally filled with one or more electrically conductive materials to form the through wafer interconnect 130. Can be.

Referring to FIG. 7D, the second metallization layer 154 may be formed on the second side opposite to the first side of the semiconductor material layer 104 on which the first metallization layer 124 is formed. In other words, the second metallization layer 154 may be formed over the electrically insulating material layer 105. The view of FIG. 7D is reversed relative to the view of FIGS. 7A-7C because the structure may be reversed to facilitate the formation of the second metallization layer 154. The second metallization layer 154 is similar to the first metallization layer 124 and includes a plurality of electrically conductive features 156 as described herein above.

FIG. 7E shows the semiconductor structure inverted once again, so that the second metallization layer 154 is disposed at the bottom of the semiconductor structure in the view of FIG. 7E. As shown in FIG. 7E, portions of the first metallization layer 124 and the carrier substrate 140 may be removed. For example, regions of the first metallization layer 124 on regions of the semiconductor material layer 104 that do not include the transistors 122 may be removed (ie, inactive regions of the fabricated semiconductor structure). Dielectric material 125 is removed). Dielectric material 125 may be removed, for example, through an etching process such as dry etching (eg, reactive ion etching) or wet etching. To remove the dielectric material 125 in the inactive regions of the fabricated semiconductor structure, the fabricated structure as shown in FIG. 7D may be detached from the carrier substrate 140 and attached to an additional carrier (not shown). The additional carrier may be attached to the second metallization layer 154. As shown in FIG. 7E, upon removal of dielectric material 125 from inactive regions of the fabricated semiconductor structure, vias 156 ′ of second metallization 154 are exposed.

In this process step, the one or more fabricated semiconductor structures 120 are in situ ( in situ ) over and in the semiconductor material layer 104 of the remainder of the substrate 100. The processed semiconductor structure of FIG. 7E can be diced (and the carrier removed). In addition, the die can be electrically tested and mounted on a package with a known good die (KGD) utilizing bump technology. Then, on top of the active elements (i.e. in the active regions) and on the inactive elements (i.e. in the inactive regions), use an additional die (like or different functionality) on top of the interposer of 7e using micro-bump technology or Manufactured using similar or different techniques) can be laminated.

Referring to FIG. 7F, one or more additional fabricated semiconductor structures, such as fabricated semiconductor structure 160A and fabricated semiconductor structure 160B, may be provided with through wafer interconnects 130 and vias on the first side of semiconductor material layer 104. Structurally and electrically coupled with the exposed ends of 156 ′, the junction semiconductor structure shown in FIG. 7F may be formed.

One or more electrical paths may be provided by electrically connecting additional fabricated semiconductor structures 160A, 160B to through wafer interconnect 130 and vias 156 ′, which paths may include first metallization layer 124. ), The remaining portion of the substrate 100 (ie, through the through wafer interconnects 130 and vias 156, through the semiconductor material layer 104, the electrically insulating material layer 105), and the fabricated semiconductor structure 120 ) And a second metallization layer 154 between each additional fabricated semiconductor structure 160A, 160B. Such electrical paths may be used to transfer electronic signals and / or power between the processing semiconductor structures 120, 160A, 160B.

As also shown in FIG. 7F, the conductive features 156 of the second metallization layer 154 may be structurally and electrically connected to higher-level conductive structures, such as another substrate 170. Can be. Between the processing semiconductor structures 120, 160A, 160B, the first metallization layer 124, the through wafer interconnect 130, and the second metallization layer 154 lead to the conductive features of the additional substrate 170. Electrical paths may also be provided, and these additional electrical paths may also be used to transport power and / or electrical signals between them.

In still further embodiments of the methods herein, the first metallization layer 124 may be an additional conductive feature in regions where the processing semiconductor structure does not correspond to the regions to be formed in situ. And 126, and regions of such a first metallization layer may not be removed during the process.

For example, FIG. 8 is a view similar to that of FIG. 5, illustrating a first metallization layer 124 ′ that can be formed on a first side of the semiconductor material layer 104 opposite the electrically insulating material layer 105. do. In the embodiments of FIG. 8, conductive features 126 are formed in the first metallization layer 124 over the regions of the substrate 100 where the transistors 122 are formed, and additional conductive features 126 are formed. Formed on other regions of the substrate 100 that do not include the transistors 122.

9A-9F form a junction semiconductor similar to those described above with reference to FIGS. 6A-6F, but with the structure shown in FIG. 8 including a first metallization layer 124 ′ instead of the structure shown in FIG. 5. The method of use is shown. The method processes of FIGS. 9A-9F are approximately similar to the method processes described above with respect to FIGS. 6A-6F, and the foregoing detailed descriptions are not repeated below.

9A, a plurality of through wafer interconnects 130 may be formed to reach the electrically insulating material layer 105 through each of the first metallization layer 124 ′ and the semiconductor material layer 104. In these methods, the electrically insulating material layer 105 is an etch-stop layer in an etching process used to form holes or vias that are finally filled with one or more electrically conductive materials to form the through wafer interconnects 130. Can be used as.

As shown in FIG. 9B, the carrier substrate 140 optionally includes a first metallization after forming through wafer interconnects 130 through the first metallization layer 124 ′ and the semiconductor material layer 104. It may be temporarily bonded to the exposed major surface 128 of layer 124 ′. After bonding the carrier substrate 140 to the first metallization layer 124 ′, the base 106 and the electrically insulating material layer 105 of the substrate 100 are removed from the structure leaving the semiconductor material layer 104. The structure shown in FIG. 9C may be formed.

The semiconductor structure as shown in FIG. 9C may alternatively be mounted to the carrier substrate with the semiconductor structure of FIG. 8 and through one or more grinding and polishing layers of the semiconductor material 104 and the electrically insulating material layer. It should be noted that by removing 105, it may be manufactured. Subsequent processes define through wafer interconnections 130 that lead through the semiconductor layer 104 into the first metallization layer 124 ′.

Referring to FIG. 9D, the second metallization layer 154 may be formed on the second side opposite to the first side of the semiconductor material layer 104 on which the first metallization layer 124 ′ is formed. The view of FIG. 9D is reversed relative to the view of FIGS. 9A-9C because the structure can be reversed to facilitate the formation of the second metallization layer 154. The second metallization layer 154 is similar to the first metallization layer 124 and includes a plurality of electrically conductive features 156 as described herein above.

FIG. 9E shows the semiconductor structure inverted once again, so that the second metallization layer 154 is disposed at the bottom of the semiconductor structure in the view of FIG. 9E. As shown in FIG. 9E, the carrier substrate 140 may be removed. However, regions of the semiconductor material layer 104 that do not include the transistors 122 and regions of the first metallization layer 124 ′ above are not to be removed as in the above-described embodiments. In this process step, on one or more processed semiconductor structure 120, semiconductor material layer 104 of the remainder of the substrate 100 and in the in-situ (in situ ) can be formed.

In this process step, the fabricated semiconductor structure of FIG. 9E can be diced (and the carrier removed). In addition, the die can be electrically tested and mounted on a package with a known good die (KGD) utilizing bump technology. Then, on top of the active elements (i.e. in the active regions) and on the inactive elements (i.e. in the inactive regions), use an additional die (like or different functionality) on top of the interposer of 9e using micro-bump technology Manufactured using similar or different techniques) can be laminated.

Therefore, in more detail, referring to FIG. 9F, one or more additional fabricated semiconductor structures, such as fabricated semiconductor structure 160A, fabricated semiconductor structure 160B, and fabricated semiconductor structure 160C, may include first metallization layer 124. Structurally and electrically connected to the exposed ends of the through wafer interconnect 130 at the exposed major surface of '), to form the bonded semiconductor structure shown in FIG. 9F. The further processed semiconductor structure 160C may include any type of processed semiconductor structure previously mentioned with respect to the further processed semiconductor structures 160A, 160B. Thus, the configured electrical paths between the processing semiconductor structure 120, 160A, 160B, 160C through the first metallization layer 124 ′, through wafer interconnect 130, and the second metallization layer 154. Electrical paths may be used to transport power and / or electrical signals therebetween.

Also, as shown in FIG. 9F, the conductive features 156 of the second metallization layer 154 may be structurally and electrically connected to higher-level conductive structures such as other substrates 170. . Conductive features of the additional substrate 170 through the first metallization layer 124 ′, through wafer interconnect 130, and second metallization layer 154 between the fabricated semiconductor structures 120, 160A, 160B, 160C. Electrical paths leading to them may also be provided, and these additional electrical paths may also be used to transport power and / or electrical signals between them.

10A through 10F form a junction semiconductor similar to that described above with reference to FIGS. 7A through 7F, but using the structure shown in FIG. 8 including a first metallization layer 124 ′ instead of the structure shown in FIG. 5. Shows the method. The method processes of FIGS. 10A-10F are approximately similar to the method processes described above with respect to FIGS. 6A-6F and 7A-7F, and the detailed descriptions described above are not repeated below.

Referring to FIG. 10A, the plurality of through wafer interconnects 130 reaches the base 106 through each of the first metallization layer 124 ′, the semiconductor material layer 104, and the electrically insulating material layer 105. It can be formed to be. In such methods, the base 106 may be used as an etch-stop layer in an etching process used to form holes or vias that are finally filled with one or more electrically conductive materials to form the through wafer interconnect 130. .

As shown in FIG. 10B, carrier substrate 140 optionally passes through wafer interconnect 130 through first metallization layer 124 ′, semiconductor material layer 104, and electrically insulating material layer 105. ) May be temporarily bonded on the exposed major surface 128 of the first metallization layer 124 ′. After bonding the carrier substrate 140 to the first metallization layer 124 ′, the base 106 of the substrate 100 is removed from the structure, leaving the semiconductor material layer 104 and the insulating material layer 105, The structure shown in FIG. 10C can be formed.

The semiconductor structures as shown in FIG. 10C can alternatively be manufactured by mounting the semiconductor structure of FIG. 8 on a carrier substrate and removing the semiconductor material 104 through one or more grinding and polishing operations. Keep in mind that it may. Subsequent processes are through wafer interconnections 130, through the insulating material layer 105, through the semiconductor layer 104, and into the first metallization layer 124 ′. Can be defined.

Referring to FIG. 10D, the second metallization layer 154 may be formed on a second side opposite to the first side of the semiconductor material layer 104 on which the first metallization layer 124 ′ is formed. In other words, the second metallization layer 154 may be formed on the side of the electrically insulating material layer 105 opposite the semiconductor material layer 104 above the electrically insulating material layer 105. The view of FIG. 10D is reversed to the view of FIGS. 10A-10C because the structure can be reversed to facilitate the formation of the second metallization layer 154. The second metallization layer 154 is similar to the first metallization layer 124 'and includes a plurality of electrically conductive features 156 as described herein above.

FIG. 10E shows the semiconductor structure inverted once again, so the second metallization layer 154 is disposed at the bottom of the semiconductor structure in the view of FIG. 10E. As shown in FIG. 10E, the carrier substrate 140 may be removed. However, the regions of the first metallization layer 124 ′ over the regions of the semiconductor material layer 104 that do not include the transistors 122 are the embodiments previously described with reference to FIGS. 6A-6F and 7A-7F. Will not be removed as in the field. In this process step, one or more processed semiconductor structures 120 may be formed in situ over and within the semiconductor material layer 104 of the remainder of the substrate 100.

In this process step, the processed semiconductor structure of FIG. 10E can be diced. In addition, the die can be electrically tested and mounted on a package with a known good die (KGD) utilizing bump technology. Then, on top of the active elements (i.e. in the active regions) and on the inactive elements (i.e. in the inactive regions), using a micro-bump technique at the top of the interposer of 10e (using similar or different functionality or Manufactured using similar or different techniques) can be laminated.

Thus, in more detail, referring to FIG. 10F, one or more additional fabricated semiconductor structures, such as fabricated semiconductor structure 160A, fabricated semiconductor structure 160B, and fabricated semiconductor structure 160C may be formed of first metallization layer 124 ′. The junction semiconductor structure shown in FIG. 10F may be formed by structurally and electrically connecting to the exposed ends of the through wafer interconnect 130 at the exposed major surface of the < RTI ID = 0.0 > Thus, electrical paths through the first metallization layer 124 ′, through wafer interconnect 130, and second metallization layer 154 may also be provided between the fabricated semiconductor structures 120, 160A, 160B, 160C. These additional electrical paths can also be used to transport power and / or electrical signals between them.

Also, as shown in FIG. 10F, the conductive features 156 of the second metallization layer 154 may be structurally and electrically connected to other features of higher structure such as other substrates 170. have. Conductive features of the additional substrate 170 through the first metallization layer 124 ′, through wafer interconnect 130, and second metallization layer 154 between the fabricated semiconductor structures 120, 160A, 160B, 160C. Electrical paths leading to the furnaces can also be provided, and these additional electrical paths can also be used to transport power and / or electrical signals between them.

In the embodiments described herein, the conductive features (eg, conductive pads) of the additional processed semiconductor structure 160A, 160B, 160C may be through wafer interconnect 130 using conductive micro bumps or micro balls 162. 130 ') is structurally and electrically connected. Similarly, the conductive features 156 of the second metallization layer 154 are structurally and electrically connected to the conductive features of the additional substrate 170 using conductive bumps or balls 172. In further embodiments of the present disclosure, the conductive features of the further fabricated semiconductor structures 160A, 160B, 160C may be a through wafer interconnect 130 using a metal-to-metal direct bonding process. ) Can be structurally and electrically connected. Similarly, the conductive features 156 of the second metallization layer 154 can be structurally and electrically coupled to the conductive features of the additional substrate 170 using a metal-to-metal direct bonding process. . It should be noted that the direct bonding method may have a reduced bonding pitch compared to the micro-bump techniques described herein and may be employed in additional embodiments herein. Such reduced junction pitch may enable higher input / output (I / O) density between junction element structures.

For example, FIG. 11 illustrates embodiments of a bonded semiconductor structure similar to that of FIG. 10F, wherein the metal-to-metal direct bonding process penetrates through the conductive features of additional processed semiconductor structures 160A, 160B, 160C. To bond to 130, and to bond the conductive features 156 of the second metallization layer 154 to the conductive features of the additional substrate 170. Such direct bonding processes can be used to form a junction semiconductor structure such as those shown in FIGS. 6F, 7F, and 9F.

The metal-to-metal direct bonding process is less than about 400 ° C., or even about 350 ° C. in some embodiments herein, to avoid thermal damage of the device structure within the fabricated semiconductor structure 120, 160A, 160B, 160C. It may be carried out at temperatures below. In some embodiments, the bonding process may include an ultra low temperature direct bonding process, and may also include a surface assisted direct bonding process, which processes may include As defined herein above.

As another example, FIG. 12 illustrates embodiments of a bonded semiconductor structure similar to that of FIG. 7F, in which an oxide-to-oxide direct bonding process is added to further processing semiconductor structure 160A. , 160B) was used to bond the electrically insulating material layer 105. As in FIG. 11, a metal-to-metal direct bonding process may be used to bond the conductive features 156 of the second metallization layer 154 to the conductive features of the additional substrate 170. To form the junction semiconductor structure of FIG. 12, some modified methods similar to those previously described with reference to FIGS. 7A-7F may be used. For example, to form the junction semiconductor structure of FIG. 12, portions of the first metallization layer 124 may be removed as described above with reference to FIG. 7E. However, the processes may be used to remove portions of the semiconductor material layer 104 in those regions to expose the electrically insulating material layer 105, which may be formed to include oxide. In addition, additional fabricated semiconductor structures 160A and 160B may be directly bonded to the electrically insulating material layer 105 in an oxide-to-oxide direct bonding process. In addition, at least through wafer interconnect 130 interconnected to additional fabricated semiconductor structures 160A, 160B may provide additional processing semiconductor structures 160A, 160B for electrically insulating material layer 105 in an oxide-to-oxide direct bonding process. ), And before the second metallization layer 154 is formed. Forming the through wafer interconnects 130 after a direct bonding process is an electrical structure established between each of the conductive features of the through wafer interconnects 130 and the additional fabricated semiconductor structures 160A and 160B to which they are connected. You can improve the quality of the connection.

An oxide-to-oxide direct junction process is, in some embodiments herein, less than about 400 ° C., or even less than about 350 ° C., to avoid thermal damage of the device structure within the fabricated semiconductor structure 120, 160A, 160B. Can be carried out at a temperature. In some embodiments, the bonding process may include a cryogenic direct bonding process, and may include a surface assisted direct bonding process, which processes have been previously defined herein.

Similar oxide-to-oxide direct junction processes may also be used to form junction semiconductor structures similar to those shown in FIGS. 6F, 9F, and 10F.

Embodiments of the present invention can be used to provide direct, continuous electrical paths between fabricated semiconductor structures supported by at least a portion of a SeOI type substrate, which electrical paths are supported by at least a portion of the SeOI type substrate. Only through conductive features (eg, pads, traces, and vias) that do not pass through a portion of another high level substrate (eg, additional substrate 170) to which at least a portion of the SeOI type substrate is attached. Is extended to. Such electrical paths may be shorter than previously known configurations and may provide improvements in signal speed and / or power efficiency.

Further non-limiting embodiments of the present description are described below:

Example 1: providing a substrate comprising a layer of semiconductor material over a layer of electrically insulating material; Forming a first metallization layer on the substrate, the first metallization layer comprising a plurality of electrically conductive features on the first side of the semiconductor material layer opposite the electrically insulating material layer; Forming a plurality of through wafer interconnects at least partially through the substrate and forming at least one through wafer interconnect of the plurality of through wafer interconnects extending through each of the metallization layer and the semiconductor material layer; Forming a second metallization layer comprising a plurality of electrically conductive features on a second side opposite the first side of the semiconductor material layer; And a first fabricated semiconductor structure supported by a first metallization layer, a substrate, and a substrate on the first side of the semiconductor material layer and a second fabricated supported by the substrate on the first side of the semiconductor material layer. Providing electrical paths extending continuously through a second metallization layer between semiconductor structures.

Example 2 The method of Example 1, wherein providing a substrate comprises selecting a substrate comprising a semiconductor-on-insulator (SeOI) substrate.

Example 3 The method of example 2, wherein selecting a substrate comprising a SeOI substrate comprises selecting a substrate comprising a silicon-on-insulator (SeOI) substrate.

Example 4 The oxide material layer of any one of embodiments 1-3, wherein the semiconductor material layer has an average total thickness of about 1 micron or less, and the electrically insulating material layer has an average total thickness of about 300 nm or less. A semiconductor device forming method comprising a.

Embodiment 5: The method of any of embodiments 1-4, wherein forming at least one through wafer interconnect of the plurality of through wafer interconnects extending through each of the metallization layer and the semiconductor material layer comprises: an electrically insulating material. And forming at least one through wafer interconnect of the plurality of through wafer interconnects extending through the layer.

Embodiment 6: The semiconductor of any one of embodiments 1-5, further comprising bonding at least one of the first and second processing semiconductor structures to the substrate on a first side of the semiconductor material layer. Device Formation Method.

Example 7: Bonding at least one of a first fabricated semiconductor structure and a second fabricated semiconductor structure onto the substrate over a first side of a layer of semiconductor material comprises: a first fabricated semiconductor structure and a second Bonding at least one of the fabricated semiconductor structures directly to the substrate in a metal-to-metal direct bonding process at a temperature of about 400 ° C. or less.

Example 8 The method of any of embodiments 1-7, wherein at least one of the first and second fabricated semiconductor structures is in situ on the substrate over the first side of the semiconductor material layer. The method of forming a semiconductor device further comprising forming.

Example 9 The method of any one of embodiments 1-8, wherein providing an electrical path extends through at least one conductive features of the first metallization layers, and through each of the metallization layer and the semiconductor material layer. Extending through at least one of the plurality of through wafer interconnects, at least one conductive feature of the second metallization layer, and at least one other through wafer interconnect of the plurality of through wafer interconnects. The method of claim 1 further comprising the step of constructing an electrical path.

Embodiment 10: The semiconductor of any one of embodiments 1-9, further comprising structurally and electrically connecting at least one conductive feature of the second metallization layer to a conductive feature of another substrate. Device Formation Method.

Embodiment 11: The first process semiconductor structure and the second process semiconductor according to any one of embodiments 1 to 10, from the group consisting of an electronic signal processor element, an electronic memory element, an electromagnetic radiation emitter element, and an electromagnetic radiation receiving element. Selecting each structure individually.

Embodiment 12: The method of Embodiment 11, further comprising: selecting a first fabricated semiconductor structure comprising an electronic signal processor element; And selecting the second fabricated semiconductor structure to include at least one of an electronic memory device, a light emitting diode, a laser light emitting diode, and a solar cell.

Example 13: A substrate comprising a layer of semiconductor material; A first metallization layer on the substrate over the first side of the semiconductor material layer; A second metallization layer on the substrate on a second side opposite the first side of the semiconductor material layer; A plurality of through wafer interconnects extending at least partially through each of the first metallization layer and the semiconductor material layer of the substrate; A first fabricated semiconductor structure supported by the substrate on the first side of the semiconductor material layer; And a second fabricated semiconductor structure supported by the substrate on the first side of the semiconductor material layer, wherein an electrical path is from the first fabricated semiconductor structure through the conductive features of the first metallization layer, Through the first through wafer interconnect of the plurality of through wafer interconnects, through the conductive feature of the second metallization layer, and through the second through wafer interconnect of the plurality of through wafer interconnects, to the second fabricated semiconductor structure. Extending so far.

Embodiment 14 The semiconductor structure of Embodiment 13, wherein the substrate comprises a SeOI substrate.

Example 15 The semiconductor structure of example 14, wherein the insulator-phase-semiconductor (SeOI) substrate comprises an insulator-phase-silicon (SeOI) substrate.

Example 16: The semiconductor structure of Example 14 or 15, wherein the layer of semiconductor material has an average total thickness of about 300 microns or less.

Embodiment 17 The semiconductor structure of any one of embodiments 14-16, wherein at least one through wafer interconnect of the plurality of through wafer interconnects extends at least partially through an electrically insulating material layer of the SeOI substrate.

Embodiment 18 The semiconductor structure of any one of embodiments 13-17, wherein at least one of the first and second processing semiconductor structures is bonded to the substrate over a first side of the semiconductor material layer.

Embodiment 19 The semiconductor structure of embodiment 18, wherein at least one metal feature of the first and second fabricated semiconductor structures is directly bonded to at least one through wafer interconnect of the plurality of through wafer interconnects. .

Embodiment 20 The method of any of embodiments 13-19, wherein the electrical path passes through the substrate, the first metallization layer, and the second metallization layer between the first and second processing semiconductor structures. To extend continuously.

Embodiment 21 The semiconductor structure of any of Embodiments 13-20, wherein at least one conductive feature of the second metallization layer is electrically connected to conductive features of the other substrate.

Embodiment 22 The method of any of Embodiments 13-21, wherein each of the first and second processing semiconductor structures is an electronic signal processor element, an electronic memory element, an electromagnetic radiation emitter element, and an electromagnetic radiation receiver element. A semiconductor structure comprising one.

Embodiment 23 The system of Embodiment 22, wherein the first fabricated semiconductor structure comprises an electronic signal processor device, wherein the second fabricated semiconductor structure comprises at least one of an electronic memory device, a light emitting diode, a laser light emitting diode, and a solar cell. Semiconductor structure comprising.

The illustrative embodiments of the invention described above do not limit the scope of the invention. These are merely examples of embodiments of the invention as defined by the claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of the present invention. In addition, various modifications of the present invention other than those shown and described herein, such as alternative and swimmer combinations of the described elements, will be apparent to those skilled in the art from this specification. Such modifications are also intended to be within the scope of the claims. Headings are used for clarity and convenience herein and do not limit the scope of the following claims.

Claims (18)

Providing a substrate comprising a layer of semiconductor material over the layer of electrically insulating material;
Forming a first metallization layer on the substrate, the first metallization layer comprising a plurality of electrically conductive features on the first side of the semiconductor material layer opposite the electrically insulating material layer;
Forming a plurality of through wafer interconnects at least partially through the substrate and forming at least one through wafer interconnect of the plurality of through wafer interconnects extending through each of the metallization layer and the semiconductor material layer;
Forming a second metallization layer comprising a plurality of electrically conductive features on a second side opposite the first side of the semiconductor material layer; And
A first fabricated semiconductor structure supported by a first metallization layer, a substrate and a substrate on the first side of the semiconductor material layer and a second fabricated semiconductor supported by the substrate on the first side of the semiconductor material layer Providing electrical paths extending continuously through the second metallization layer between the structures. The method of claim 1, wherein forming at least one through wafer interconnect of the plurality of through wafer interconnects extending through each of the metallization layer and the semiconductor material layer comprises: a plurality of through wafer interconnects extending through the electrically insulating material layer. Forming at least one of the through wafer interconnects. The method of claim 1, further comprising bonding at least one of a first processed semiconductor structure and a second processed semiconductor structure to the substrate on a first side of a semiconductor material layer. 4. The method of claim 3, wherein bonding at least one of a first processed semiconductor structure and a second processed semiconductor structure onto the substrate over a first side of a semiconductor material layer comprises: Bonding at least one directly to the substrate in a metal-to-metal direct bonding process at a temperature of 400 ° C. or less. The semiconductor device formation of claim 1, further comprising forming at least one of the first and second fabricated semiconductor structures in situ on the substrate over the first side of the semiconductor material layer. Way. The method of claim 1, wherein providing an electrical path comprises: forming at least one conductive features of the first metallization layers and at least one of a plurality of through wafer interconnects extending through each of the metallization layer and the semiconductor material layer. Configuring an electrical path extending through the through wafer interconnect, at least one conductive features of the second metallization layer, and at least one other through wafer interconnect of the plurality of through wafer interconnects, respectively; A semiconductor element formation method. The method of claim 1, further comprising structurally and electrically connecting at least one conductive feature of the second metallization layer to a conductive feature of another substrate. The method of claim 1, further comprising individually selecting each of the first and second processing semiconductor structures from the group consisting of an electronic signal processor element, an electronic memory element, an electromagnetic radiation emitter element, and an electromagnetic radiation receiving element. A semiconductor element formation method, including. 9. The method of claim 8,
Selecting a first fabricated semiconductor structure comprising an electronic signal processor element; And
Selecting the second fabricated semiconductor structure to include at least one of an electronic memory device, a light emitting diode, a laser light emitting diode, and a solar cell. A substrate comprising a semiconductor material layer;
A first metallization layer on the substrate over the first side of the semiconductor material layer;
A second metallization layer on the substrate on a second side opposite the first side of the semiconductor material layer;
A plurality of through wafer interconnects extending at least partially through each of the first metallization layer and the semiconductor material layer of the substrate;
A first fabricated semiconductor structure supported by the substrate on the first side of the semiconductor material layer; And
A second fabricated semiconductor structure supported by the substrate on the first side of the semiconductor material layer;
An electrical path is from the first fabricated semiconductor structure, through the conductive features of the first metallization layer, through the first through wafer interconnect of the plurality of through wafer interconnects, and to the conductive features of the second metallization layer. And extend through the second through wafer interconnect of the plurality of through wafer interconnects to the second fabricated semiconductor structure. The semiconductor structure of claim 10, wherein the substrate comprises a SeOI substrate. The semiconductor structure of claim 11, wherein at least one through wafer interconnect of the plurality of through wafer interconnects extends at least partially through an electrically insulating material layer of the SeOI substrate. The semiconductor structure of claim 10, wherein at least one of the first and second processing semiconductor structures is bonded to the substrate over a first side of the semiconductor material layer. The semiconductor structure of claim 13, wherein at least one metal feature of the first and second fabricated semiconductor structures is directly bonded to at least one through wafer interconnect of the plurality of through wafer interconnects. The semiconductor structure of claim 10, wherein the electrical path extends continuously through the substrate, the first metallization layer, and the second metallization layer between the first and second processing semiconductor structures. The semiconductor structure of claim 10, wherein at least one conductive feature of the second metallization layer is electrically connected to conductive features of another substrate. The semiconductor structure of claim 10, wherein each of the first and second semiconductor structures comprises one of an electronic signal processor element, an electronic memory element, an electromagnetic radiation emitter element, and an electromagnetic radiation receiver element. 18. The method of claim 17,
The first fabricated semiconductor structure includes an electronic signal processor element,
The second fabricated semiconductor structure includes at least one of an electronic memory device, a light emitting diode, a laser light emitting diode, and a solar cell.

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