KR101319674B1 - Photovoltaic cells and methods to enhance light trapping in semiconductor layer stacks - Google Patents

Abstract

The photovoltaic cell includes a substrate, a semiconductor layer stack, a reflective conductive electrode layer, and a textured template layer. The semiconductor layer stack is disposed above the substrate. The electrode layer is located between the substrate and the semiconductor layer stack. The template layer is located between the substrate and the electrode layer. The template layer includes an uneven upper surface that imparts a predetermined shape to the electrode layer. The electrode layer reflects light back into the semiconductor layer stack based on the predetermined shape of the electrode layer.

Description

Method for improving light trapping in photovoltaic cells and semiconductor layer laminates {PHOTOVOLTAIC CELLS AND METHODS TO ENHANCE LIGHT TRAPPING IN SEMICONDUCTOR LAYER STACKS}

This application is a formal patent application of pending US Patent Provisional Application No. 61 / 176,072 (hereinafter referred to as "'072 Application") entitled "Method of Improving Light Trap in Photovoltaic Cells and Thin Film Silicon". Insist on priority interests. The '072 application was filed on May 6, 2009. The entire contents of the '072 application are incorporated herein by reference in their entirety.

The subject matter described in this application relates to a photovoltaic device.

Various known photovoltaic devices include thin film solar cell modules fabricated using thin films of silicon or other semiconductor materials. Light entering the module passes into the silicon film. Once light is absorbed into the silicon film, the light can generate electrons and holes in the silicon. Electrons and holes are used to generate electrical potential and / or current that can be withdrawn from the module and applied to an external electrical load.

Photons of light separate electrons from atoms in the silicon film by exciting electrons in the silicon film. In order for the photons to excite the electrons in the silicon film and to separate the electrons from the atoms, the photons require more energy than the energy band gap of the silicon film. The energy of photons is related to the wavelength of light incident on the silicon film. Thus, the light absorbed in the silicon film is based on the energy bandgap of the silicon film and the wavelength of the light. Light absorbed in the silicon film may be referred to as "trapped" light in the film.

The amount of current or power produced by the photovoltaic device can be directly related to the amount of light captured in the silicon film. For example, the efficiency of a photovoltaic device in converting incident light into a current may be related to the amount of light or photons that excite electrons in the silicon film of the photovoltaic device. However, some known photovoltaic devices exit a photovoltaic device without exciting electrons in the silicon film by allowing a relatively large amount of incident light to pass through the silicon film, be reflected at the reflective electrode and pass back through the silicon film. Light can pass through the film in a direction substantially perpendicular to the substrate below the silicon film and can be reflected in the opposite direction.

There is a need for a photovoltaic device that increases the amount of light or photons that are trapped in the semiconductor layer of the photovoltaic device or excite electrons within the semiconductor layer.

In one embodiment, the photovoltaic cell comprises a substrate, a semiconductor layer stack, a reflective conductive electrode layer, and a textured template layer. The semiconductor layer stack is disposed above the substrate. The electrode layer is located between the substrate and the semiconductor layer stack. The template layer is located between the substrate and the electrode layer. The template layer includes an uneven upper surface that imparts a predetermined shape to the electrode layer. The electrode layer reflects light back into the semiconductor layer stack based on the predetermined shape of the electrode layer.

In other embodiments, other photovoltaic cells are provided. The photovoltaic cell includes a substrate, a semiconductor layer stack, and an electrode layer. The semiconductor layer stack is disposed above the substrate. The electrode layer is positioned between the substrate and the semiconductor layer stack and includes a reflective layer and a light transmissive conductive layer. The conductive layer includes an uneven upper surface that scatters incident light into the reflective layer. The reflective layer reflects the light scattered by the conductive layer back into the semiconductor layer stack.

In other embodiments, other photovoltaic cells are provided. The photovoltaic cell includes a substrate, a semiconductor layer stack, and a reflective conductive electrode layer. The substrate has a predetermined uneven upper surface. The semiconductor layer stack is disposed above the substrate. The electrode layer is located between the top surface of the substrate and the semiconductor layer stack. The uneven upper surface of the substrate gives a predetermined shape to the electrode layer. The electrode layer reflects light back into the semiconductor layer stack based on the predetermined shape.

1 is a schematic perspective view of a photovoltaic (PV) device and a cross-sectional view of a PV device, according to one embodiment.
FIG. 2 is a cross-sectional view of a PV cell according to one embodiment shown in FIG. 1 taken along line 2-2 of FIG.
3 is a cross-sectional view illustrating an example of a peak structure for the template layer illustrated in FIG. 1 according to an embodiment.
4 is a cross-sectional view illustrating one example of a valley structure for the template layer shown in FIG. 1 according to one embodiment.
5 is a cross-sectional view illustrating an example of a curved structure for the template layer shown in FIG. 1 according to an embodiment.
6 is a cross-sectional view of a PV cell including a plurality of template layers according to another embodiment.
7 is a cross-sectional view of a PV cell with textured electrodes according to another embodiment.
8 is a cross-sectional view of a PV cell with a textured template layer formed of discrete layers according to another embodiment.
9 is a cross-sectional view of a PV cell with a textured substrate according to another embodiment.
10 is a flow diagram illustrating a method of manufacturing a PV device with a textured template layer, according to one embodiment.
11 is a flow chart illustrating a method of manufacturing a PV device with a plurality of textured template layers, according to one embodiment.
12 is a flowchart illustrating a method of manufacturing a PV device with textured electrodes according to one embodiment.
FIG. 13 is a flow diagram illustrating a method of manufacturing a PV device having a textured template layer formed of separated layers according to one embodiment.
14 is a flowchart illustrating a method of manufacturing a PV device with a textured substrate, according to one embodiment.
The foregoing description, as well as the following detailed description of certain embodiments of the presently required technology, may be better understood by reading in conjunction with the accompanying drawings. In the drawings certain embodiments are shown for the purpose of illustrating the presently required technology. However, the presently required technology is of course not limited to the arrangement and configuration shown in the accompanying drawings. In addition, the components of the drawings are not drawn to scale, and the relative dimensions of one component to another should not be interpreted or understood to require such a relative dimension.

The foregoing description, as well as the following detailed description of certain embodiments of the presently required technology, may be better understood by reading in conjunction with the accompanying drawings. It is to be understood that the elements or steps mentioned herein as singular or used without specific reference to the number do not exclude the case where the elements or steps are plural unless explicitly stated. In addition, the term "one embodiment" is not intended to exclude the presence of additional embodiments that also include the mentioned features. Also, unless stated to the contrary, embodiments that "include" or "include" an element with a particular characteristic or a plurality of elements may include additional such elements without that characteristic.

1 is a schematic perspective view of a photovoltaic (PV) device 100 and a detailed view 110 of a cross-section of the PV device 100, according to one embodiment. The PV device 100 includes a plurality of PV cells 102 electrically connected to each other. For example, the PV device 100 may have 100 or more PV cells 102 connected in series with each other. The outermost PV cells 102 located at or adjacent to both sides 132, 134 of the PV device 100 are electrically coupled with respective conductive leads 104, 106. Leads 104 and 106 may extend between both ends 128 and 130 of PV device 100. Leads 104 and 106 are connected with a circuit 108 that includes an electrical load through which current generated by the PV device 100 is collected or applied. For example, the current generated by the PV device 100 may be collected in an energy storage device such as a battery and / or may be applied to a device that consumes at least a portion of the current to perform a certain function.

The PV cell 102 includes a laminate of a plurality of layers. In one embodiment, PV cell 102 includes a support substrate 112, a textured template layer 136, a bottom electrode 114, a semiconductor layer stack 116, and an upper electrode 118. ) And an upper adhesive layer 120 and a cover sheet 122. The top electrode 118 of one PV cell 102 may be electrically connected to the bottom electrode 114 of a neighboring PV cell 102 to electrically couple the PV cells 102 in series.

The PV device 100 generates a current from light incident on the upper surface 124 of the cover sheet 122. Light passes through the cover sheet 122, the upper adhesive layer 120, and the upper electrode 118. At least a portion of the light is absorbed by the semiconductor layer stack 116 when light initially enters and passes through the semiconductor layer stack 116. The semiconductor layer stack 116 may include N-I-P or P-I-N stacks 126, 128, 130 of a doped semiconductor layer or film in the illustrated embodiment. Alternatively, semiconductor layer stack 116 may include N-I-P and / or P-I-N stacks 126, 128, 130 of a doped semiconductor layer or film. Some of the light may pass through the semiconductor layer stack 116. Light passing through the semiconductor layer stack 116 may be reflected back into the semiconductor layer stack 116 by the template layer 136 and / or the bottom electrode 114.

When light initially passes through the semiconductor layer stack 116 and / or when light is reflected back from the template layer 136 into the semiconductor layer stack 116, the photons of light are in the semiconductor layer stack 116. Excites electrons from Depending on the wavelength of the light and the energy bandgap of the material in the semiconductor layer stack 116, the photons of light can excite electrons within the semiconductor layer stack 116 to separate the electrons from the atom. When an electron is separated from an atom, a complementary amount of charge or hole is produced. Semiconductor layer or film 126, 128, 130 in semiconductor layer stack 116 that generates electron-hole pairs when light passes through semiconductor layer or film 126, 128, 130 in semiconductor layer stack 116. ) May be referred to as an active layer or an active film. Electrons are drifted or diffused through the semiconductor layer stack 116 and collected at the top or bottom electrodes 118, 114. Holes travel or diffuse through the semiconductor layer stack 116 and are collected at the remaining ones of the top and bottom electrodes 118 and 114. Electrons and holes collected at the top or bottom electrodes 118, 114 create a potential difference in the PV cell 102. The potential difference in the PV cell 102 can be added over the entire PV device 100. For example, the potential difference of each PV cell 102 can be summed together. As the number of PV cells 102 increases, additional voltage differences across the series of PV cells 102 may also increase.

Electrons and holes flow through the top and bottom electrodes 118, 114 of either PV cell 102 to the opposite electrodes 114, 118 of the neighboring PV cell 102. For example, if electrons flow to the bottom electrode 114 of the first PV cell 102 when light meets the semiconductor layer stack 116, then electrons pass through the bottom electrode 114 to the neighboring PV cell 102. Flows to the upper electrode 118. Likewise, if holes flow to the top electrode 118 of the first PV cell 102, holes then flow through the top electrode 118 to the bottom electrode 114 of the neighboring PV cell 102.

Electrons and holes flow between neighboring PV cells 102 through top and bottom electrodes 118 and 114 to generate current and voltage. The voltages generated by each PV cell 102 are summed in series across the plurality of PV cells 102. Thereafter, current flows into the circuit 108 through the connection of the leads 104, 106 to the top and bottom electrodes 118, 114 of the outermost PV cell 102. For example, the first lead 104 may be electrically connected to the top electrode 118 of the leftmost PV cell 102, while the second lead 106 may be connected to the bottom electrode 114 of the rightmost PV cell 102. Can be electrically connected.

According to one embodiment, template layer 136 has a predetermined textured shape, thereby being based on or based on one or more reflective surfaces template layer 136 between semiconductor layer stack 116 and substrate 112. It will have a corresponding shape. Template layer 136 has a controlled or predetermined uneven top surface 138. As described below, the top surface 138 may be defined by a regular or periodic arrangement of certain structures 300, 400, 500 (shown in FIGS. 3-5), such as three-dimensional cones, pyramids, cylinders, and the like. have. The reflective surface that reflects light may be part of the bottom electrode 114 as part of the outer layer of the PV cell 102. Textured shape incident light on the reflective surface can be scattered to be reflected back into the semiconductor layer stack in various different directions. Scattering light back into the semiconductor layer stack 116 excites additional electrons from the atoms to increase the voltage difference generated in the PV cell 102.

The top surface 138 of the template layer 136 may be controlled or given a shape by a layer applied over the template layer 136. For example, certain patterns or arrays of template layer 136 may be repeated into one or more layers applied onto template layer 136. For example, one or more of the bottom electrode 114, the semiconductor layer stack 116, and / or the top electrode 118 may have a shape that corresponds to, coincides with, or matches the shape of the template layer 136. The template layer 136 may have a shape for improving light scattering, light focusing, and light absorption in the semiconductor layer stack 116.

FIG. 2 is a cross-sectional view of the PV cell 102 according to one embodiment shown in FIG. 1 taken along line 2-2 of FIG. 1. As noted above, the PV cell 102 is a substrate-configured solar cell in that the PV cell 102 receives light from the side 124 of the PV cell 102 opposite the substrate 112. The substrate 112 is a laminated surface on which the remaining films or layers of the PV cell 102 are applied. The substrate 112 may include or be formed from an insulating material or a conductive material. In one embodiment, the substrate 112 is formed of glass, such as float glass or borosilicate glass. In another embodiment, the substrate 112 may be formed from soda-lime float glass, low content iron float glass or glass comprising at least 10% by weight sodium oxide (Na ₂ O). In another embodiment, the substrate 112 is formed from a ceramic such as silicon nitride (Si ₃ N ₄ ) or aluminum oxide (alumina, Al ₂ O ₃ ). In another embodiment, substrate 112 is formed of a conductive material, such as a metal or metal alloy. For example, the substrate 112 may be formed from stainless steel, aluminum, titanium, polyethylene terephthalate (PET), polyethylenenaphthalene (PEN), or the like.

Template layer 136 is applied on substrate 112. The template layer 136 includes an insulating or conductive material that can withstand the temperatures encountered by the template layer 136 during application of the bottom electrode 114, the semiconductor layer stack 116 and / or the top electrode 118. It may be formed from such a material. For example, template layer 136 may be formed of a material capable of sustaining a temperature of at least 200 ° C. In another embodiment, template layer 136 should be able to withstand a temperature of at least 400 ° C.

Template layer 136 may be formed from amorphous silicon that is etched after being applied to substrate 112 to form a structure, such as structures 300, 400, and 500 (shown in FIGS. 3-5) that reflect incident light. . The template layer 136 may be etched using reactive ion etching of the template layer 136. An etching mask may be disposed on the template layer 136 to prevent the predetermined regions of the template layer 136 from being etched and to form the structures 300, 400, and 500 on the template layer 136. By way of example only, silicon dioxide, such as spheres, may be applied to template layer 136 prior to applying bottom electrode 114. The template layer 136 may then be etched using silicon dioxide while preventing certain areas of the template layer 136 covered by the silicon dioxide from being removed.

In another example, the template layer 136 may be formed by applying a metal layer or metal alloy layer on the substrate 112 by sputtering or the like and then anodizing the metal layer or metal alloy layer. In one embodiment, the template layer 136 is formed by sputtering aluminum or tantalum onto the substrate 112 and then forming the structures 300, 400, 500 (shown in FIGS. 3-5) in the template layer 136. It is applied by anodizing aluminum or tantalum. The template layer 136 may be anodized by immersing the substrate 112 and template layer 136 into a liquid bath containing acid. A voltage difference is applied between the template layer 136 and the conductive member also immersed in the liquid bath. A positive voltage is applied to the template layer 136 and a negative voltage is applied to the conductive member. The voltage difference releases hydrogen at the conductive member or cathode and oxygen at the template layer 136 or anode. Aluminum oxide may be formed on the template layer 136. The acid contained in the liquid bath dissolves at least a portion of the aluminum oxide to form the structures 300, 400, 500. Further immersion of the template layer 136 into an acid bath may further etch the aluminum oxide of the template layer 136 to define the structures 300, 400, and 500. One or more parameters involved in anodizing the template layer 136 may be changed to control the shape and / or size of the structures 300, 400, 500. For example, the time during which the template layer 136 is immersed in the liquid bath with the voltage difference applied, the type of acid contained in the liquid bath, the strength of the voltage difference, and / or the acidic etching period after the anodizing treatment may be described later. , 400 and 500 may be changed in size and / or shape.

In another embodiment, template layer 136 is applied by applying a static charge to substrate 112 and then placing substrate 112 in an atmosphere that contains oppositely charged particles. The charge applied to the substrate 112 attracts particles to the substrate 112 and applies them onto the bubbles to form the structures 300, 400, 500 (shown in FIGS. 3 to 5) of the template layer 136. Particles forming the template layer 136 may be held in place by applying an adhesive layer over the template layer 136. Alternatively, the particles may be held in place by annealing the substrate 112 and the particles. Examples of particles that can be applied using electrostatic charges include, but are not limited to, faceted ceramics or diamondoid materials. For example, the particles may include or be formed from silicon carbide, alumina (Al ₂ O ₃ ), aluminum nitride (AlN), diamond, and chemical vapor deposition (CVD) diamond.

Template layer 136 may be separate from the layer of PV cell 102 that forms a voltage difference within PV cell 102 and / or delivers the current generated by PV cell 102. For example, the template layer 136 may not be a conductive layer for exchanging voltage or current with any of the electrodes 114 and 118, and the template layer 136 may have electrons and / or holes when incident light encounters the template layer 136. It may not be a layer that produces. Alternatively, template layer 136 may form part of bottom electrode 114. For example, the template layer 136 may include a reflective conductive material electrically coupled with the bottom electrode 114 applied on the template layer 136.

In an embodiment where template layer 136 is an insulating or dielectric material that does not allow current to flow between adjacent cells 102 of PV device 100 (shown in FIG. 1), template layer 136 is shown in FIG. 1. As can be extended continuously between adjacent cells 102. Alternatively, when template layer 136 causes current to flow, the portions or template layer 136 located between adjacent cells 102 may be electrically insulated from bottom electrode 114 of adjacent cells 102. Can be removed. For example, when template layer 136 comprises or is formed from a metal or metal alloy, current flows from bottom electrode 114 of either cell 102 through template layer 136 to bottom electrode of adjacent cell 102. Template layer 136 may be etched between these cells 102 to ensure that it does not pass through 114.

In embodiments where the substrate 112 is a conductive material, the template layer 136 may be applied onto the substrate 112 as an insulating or dielectric material that extends continuously between adjacent cells 102. For example, when substrate 112 includes a metal or metal alloy, template layer 136 may not be etched or removed between cells 102. Alternatively, if both substrate 112 and template layer 136 are conductive materials, an additional insulating layer may be disposed between conductive substrate 112 and conductive template layer 136. For example, if both substrate 112 and template layer 136 include a metal or metal alloy, an insulating material layer may be applied onto substrate 112 before template layer 136 is applied. The additional insulating layer electrically separates template layer 136 from substrate 112 such that there is no conductive path that directly couples the current delivered from template layer 136 to substrate 112. Template layer 136 may be removed between cells 102 similarly as described above such that template layer 136 does not establish a conductive path that extends between bottom electrodes 114 of adjacent cells 102.

In one embodiment, template layer 136 is at least partially opaque. For example, template layer 136 may prevent light from passing through template layer 136. Template layer 136 may be light reflective. For example, the template layer 136 may be formed of a reflective material or may include a top layer or layer of reflective material that reflects incident light. For example, the template layer 136 may have a reflective silver (Ag) layer or film on the top surface 138 at the interface between the template layer 136 and the bottom electrode 114. This conductive reflective layer or film may be electrically coupled with the bottom electrode 114.

In another embodiment, template layer 136 is an antireflective layer. Non-reflective template layer 136 may be applied to impart a controlled or desired shape onto bottom electrode 114. For example, the bottom electrode 114 may be light reflective. The bottom electrode 114 is applied on the template layer 136 such that the reflective bottom electrode 114 has the same or nearly the same shape as the template layer 136. Then, the formed bottom electrode 114 may reflect and scatter incident light as with the template layer 136 if the template layer 136 was light reflective. In one embodiment, the bottom electrode 114 includes a conductive reflective layer 200 applied on the template layer 136 and a transparent conductive layer 202 applied on the reflective layer 200. For example, the reflective layer 200 can be a conductive layer or film that carries current and can reflect incident light back into the semiconductor layer stack 116. By way of example only, reflective layer 200 may comprise or be formed from silver, aluminum, a silver alloy or an aluminum alloy. The reflective layer 200 may be applied in various thicknesses. For example, the reflective layer 200 may be applied to a thickness of approximately 100 to 300 nanometers.

The conductive layer 202 provides electrical contacts for the semiconductor layer stack 116. For example, electrons or holes generated in the semiconductor layer stack 116 may be transferred into the conductive layer 202. The conductive layer 202 is referred to as a "transparent" conductive layer in that it includes or is formed of a conductive material to allow at least some of the light to pass through the conductive layer 202. The term "transparent" is not used as an intention to limit the conductive layer 202 to a material that is completely transparent to light. By way of example only, the conductive layer 202 may comprise or be formed from one or more of aluminum doped zinc oxide, zinc oxide, indium tin oxide.

The conductive layer 202 may act as a buffer layer to provide chemical and / or optical buffer between the semiconductor layer stack 116 and the reflective layer 200. For example, the conductive layer 202 may provide a chemical buffer layer that prevents or prevents diffusion of dopants and / or impurities between the reflective layer 200 and the semiconductor layer stack 116.

The conductive layer 202 can provide an optical buffer layer having a thickness tuned to one or more light wavelengths. For example, the thickness dimension of the conductive layer 202 extending between the reflective layer 200 and the semiconductor layer stack 116 may be changed based on the wavelength of light to be reflected back into the semiconductor layer stack 116. The energy of photons in the reflected light is based on the wavelength of the light. Therefore, in order to control the energy of at least some of the photons in the light reflected into the semiconductor layer stack 116, the thickness of the conductive layer 202 is larger than that of the other wavelengths. 116 may be set to be reflected back into. By adjusting the thickness of the conductive layer 202 to increase the amount of reflected light having a predetermined wavelength, the amount of electron / hole pairs generated in the semiconductor layer stack 116 can be increased. By way of example only, the typical thickness range of the conductive layer 202 may be between 50 and 500 nanometers.

The semiconductor layer stack 116 may comprise one or more layers or films of semiconductor material, such as silicon. Alternatively, the semiconductor layer stack 116 may comprise or be formed from cadmium, cadmium telluride, indium, gallium, selenium, and the like. The semiconductor layer stack 116 may include a tandem structure comprising a P-I-N or N-I-P type junction or having two or more P-I-N or N-I-P type junctions. For example, the semiconductor layer stack 116 may include films of p-doped silicon, intrinsic silicon, and n-doped silicon applied to each other. The semiconductor material of the semiconductor layer stack 116 may be amorphous, microcrystalline, or a combination thereof.

The upper electrode 118 is applied on the semiconductor layer stack 116. Top electrode 118 includes or is formed of a transparent conductive material that allows current to pass through top electrode 118 while allowing current to flow within PV device 100 (shown in FIG. 1). . The term "transparent" is not intended to be used to limit the upper electrode 118 to a material that is completely transparent to light. By way of example only, the upper electrode 118 may comprise or be formed from one or more of aluminum doped zinc oxide, zinc oxide, indium tin oxide.

As shown in FIG. 2, the template layer 136 may impart a shape to the layer applied onto the template layer 136. For example, peaks and valleys of template layer 136 may be repeated at bottom electrode 114, semiconductor layer stack 116 and / or top electrode 118. The upper electrode 118 may have a textured pattern corresponding to and based on the template layer 136. The textured upper electrode 118 can form anti-reflection properties to capture more incident light. For example, the textured upper electrode 118 may have a greater amount of light entering the semiconductor layer stack 116 through the upper electrode 118 than the amount of light reflected by the upper electrode 118 and away from the semiconductor layer stack 116. can do. Incident light that passes through the top electrode 118, the semiconductor layer stack 116, and the bottom electrode 114 and is perpendicular to the substrate 112 or substantially perpendicular to the substrate 112 may be formed in different structures (eg, in the template layer 136). Reflected back into the semiconductor layer stack 116 from 300, 400, 500 (shown in FIGS. 3-5). Similarly, light incident on the upper electrode 118 at an acute angle, ie, glancing angle, may be easier to encounter one or more structures 300, 400, 500 present on the upper electrode 118. . The structures 300, 400, and 500 may prevent the acute angle incident light from being reflected from the semiconductor layer stack 116. Instead, the acute incident light may collide with the structures 300, 400, and 500 and enter the semiconductor layer stack 116 through the upper electrode 118.

The adhesive layer 120 and the cover sheet 122 are disposed on the upper electrode 118. The shape of template layer 136 may be determined or controlled by one or more parameters of template layer 136. These parameters are controlled to increase the amount of light captured in the active layer of the PV cell 102 (shown in FIG. 1). For example, the parameters of the template layer 136 may pass through the semiconductor layer stack 116 (shown in FIG. 1) so that the semiconductor layer stack (in the reflective layer 200 (shown in FIG. 2) and / or the template layer 136 ( 116 may be modified to increase the amount of light reflected back into it.

The parameters of the template layer 136 may be changed to increase the amount of light captured for the incident light wavelength in a desired or predetermined range. For example, template layer 136 may include three-dimensional cones, paraboloids, and / or having a controlled pitch, height, and / or shape based on the crystalline structure of one or more layers or films 126, 128, 130 in semiconductor layer stack 116. Alternatively, structures 300, 400, 500 (shown in FIGS. 3-5) that include pyramids may be applied. The parameters may be adjusted to increase light scattering and absorption in the visible wavelength range in the amorphous silicon layer of the semiconductor layer stack 116 or in the infrared wavelength range in the microcrystalline silicon layer of the semiconductor layer stack 116. have.

The pattern of the plurality of light scattering structures 300, 400, 500 (shown in FIGS. 3-5) and the structures 300, 400, 500 enhances scattering and focusing of light in a plurality of active layers within the PV cell 102. PV cell 102 may be implemented. For example, the pattern of one structure 300, 400, 500 in the template layer 136 may be used adjacent to the amorphous active layer of the semiconductor layer stack 116 and within the template layer 136 to enhance light scattering in the visible light layer. The second structure 300, 400, 500 pattern may be used adjacent to the crystalline active layer of the semiconductor layer stack 116 to enhance light scattering in the infrared layer.

3 through 5 illustrate, in plan, examples of various structures 300, 400, 500 that achieve a template layer 136 of a predetermined shape in accordance with various embodiments. The structures 300, 400, 500 are created in the template layer 136 to impart the desired texture to the top surface 138 of the template layer 136 and / or the layer applied or provided over the template layer 136. For example, structures 300, 400, 500 may be created during application or etching of template layer 136 to impart a desired texture or pattern within bottom electrode 114. Template layer 136 may comprise a single type of structure 300, 400, 500 repeated throughout template layer 136 or may include a combination of two or more of structures 300, 400, and / or 500. Can be.

The structure 300 shown in FIG. 3 is referred to as the peak structure 300 because the structure 300 looks like a steep peak arranged along the top surface 138 of the template layer 136. Peak structure 300 is defined by one or more parameters including peak height Hpk 302, pitch 304, transition shape 306, and base width Wb 308. As shown in FIG. 3, the peak structure 300 is formed in a shape in which the width decreases as the distance from the substrate 112 increases. For example, the peak structure 300 is reduced in size from the base 310 located at or adjacent to the substrate 112 to several peaks 312. The structure 300 is shown as a triangle in the top view of FIG. 3, but may alternatively have a pyramid or cone shape in three dimensions.

Peak height (Hpk) 302 represents the average or intermediate distance of peak 312 from transition shape 306 between structures 300. For example, template layer 136 may be applied as a substantially flat layer up to base 310 of peak 312 or to the region of transition shape 306. Template layer 136 may continue to be applied to form peak 312. The distance from the base 310 or transition shape 306 to the peak 312 can be the peak height (Hpk) 302.

Pitch 304 represents the average or intermediate distance between peaks 312 of peak structure 300. Pitch 304 may be approximately the same in two or more directions. For example, pitch 304 may be the same in two vertical directions extending parallel to substrate 112. In other embodiments, the pitch 304 may vary along different directions. Alternatively, pitch 304 may represent an average distance or an intermediate distance between other similar points on adjacent structure 300. The transition shape 306 is the general shape of the top surface 138 of the template layer 136 between the structures 300. As shown in the illustrated embodiment, the transition shape 306 can take the shape of a flat “facet”. As an alternative, the flat cutout shape may be conical or pyramid in three dimensions. Base width (Wb) 308 is the average or intermediate distance across structure 300 at the interface between base 310 and template 300 of template layer 136. Base width (Wb) 308 may be approximately the same in more than one direction. For example, the base widths Wb 308 may be identical in two vertical directions extending parallel to the substrate 112. Alternatively, the base width Wb 308 can vary along different directions.

4 illustrates a valley structure 400 of the template layer 136, according to one embodiment. The shape of the valley structure 400 is different from the shape of the peak structure 300 shown in FIG. 3 but may be defined by one or more of the parameters described above in connection with FIG. 3. For example, valley structure 400 is defined by peak height Hpk 402, pitch 404, transition shape 406, and base width Wb 408. Valley structure 400 is formed as a recess or cavity that extends from top surface 138 into template layer 136. The valley structure 400 is shown as having a parabolic shape in the two-dimensional view of FIG. 4, but may have a cone, pyramid or parabolic shape in three dimensions. In operation, valley structure 400 may vary slightly in the shape of an ideal parabola.

In general, the valley structure 400 includes a cavity extending downward from the top surface 138 into the template layer 136 toward the substrate 112. The valley structure 400 extends downward to the bottom 410 or the nadir of the template layer 136 located between the transition features 406. Peak height (Hpk) 402 represents the average or intermediate distance between top surface 412 and bottom 410. Pitch 404 represents the average or median distance between the same or common points of valley structure 400. For example, the pitch 404 may be a distance or an intermediate distance between the midpoints of the transition features 406 extending between the valley structures 400. Pitch 404 may be approximately equal in two or more directions. For example, the pitch 404 may be the same in two vertical directions extending parallel to the substrate 112. In other embodiments, the pitch 404 may vary along different directions. Alternatively, pitch 404 may represent the distance between the bottom 410 of valley structure 400. Alternatively, pitch 404 may represent an average distance or an intermediate distance between other similar points on adjacent valley structure 400.

The transition shape 406 is the general shape of the top surface 138 between the valley structures 400. As shown in the illustrated embodiment, the transition shape 406 can take the shape of a flat “facet”. As an alternative, the flat cutout shape may be conical or pyramid in three dimensions. Base width (Wb) 408 represents the average or median distance between the bottoms 410 of adjacent valley structures 400. Alternatively, the base width Wb 408 may represent the distance between the midpoints of the transition shape 406. Base width (Wb) 408 may be substantially the same in two or more directions. For example, the base widths Wb 408 may be the same in two vertical directions extending parallel to the substrate 112. Alternatively, the base width Wb 408 can vary along different directions.

5 illustrates a curved structure 500 of the template layer 136, according to one embodiment. The shape of the curved structure 500 is different from that of the peak structure 300 shown in FIG. 3 and the valley structure 400 shown in FIG. 4, but one of the parameters described above in connection with FIGS. 3 and 4. It may be limited by the above. For example, the curved structure 500 is defined by the peak height Hpk 502, the pitch 504, the transition shape 506, and the base width Wb 508. The curved structure 500 is formed as a protrusion of the top surface 138 of the template layer 136 extending upward from the base film 510 of the template layer 136. The curved structure 500 has an approximately parabolic or curved shape. In operation, curved structure 500 may vary slightly from the ideal parabolic shape. Although the curved structure 500 is represented by a parabola in the two-dimensional view of FIG. 5, the curved structure 500 may alternatively have a three-dimensional parabolic surface, pyramid or cone shape extending upward from the substrate 112.

In general, the curved structure 500 protrudes upward from the base film 510 to the curved high point 512, ie, the curved peak, away from the substrate 112. Peak height (Hpk) 502 represents the average distance or the median distance between base film 510 and high point 512. Pitch 504 represents the average or intermediate distance between the same or common points of curved structure 500. For example, the pitch 504 can be the distance between the high points 512. Pitch 504 may be approximately equal in two or more directions. For example, the pitch 504 may be the same in two vertical directions extending parallel to the substrate 112. Alternatively, the pitch 504 can vary along different directions. In another example, pitch 504 can represent the distance between midpoints of transition shape 506 extending between curved structures 500. Alternatively, pitch 504 may represent an average distance or an intermediate distance between other similar points on adjacent curved structure 500.

The transition shape 506 is the general shape of the top surface 138 between the curved structures 500. As shown in the illustrated embodiment, the transition shape 506 can take the shape of a flat “facet”. As an alternative, the flat cutout shape may be conical or pyramid in three dimensions. Base width (Wb) 508 represents the average distance or the median distance between transition shapes 506 on both sides of curved structure 500. Alternatively, the base width Wb 508 can represent the distance between the midpoints of the transition shape 506.

According to one embodiment, the pitches 304, 404, 504 and / or base widths Wb 308, 408, 508 of the structures 300, 400, 500 are between about 400 nanometers and about 1500 nanometers. Alternatively, the pitches 304, 404, 504 of the structures 300, 400, 500 may be less than approximately 400 nanometers or greater than approximately 1500 nanometers. The mean or median peak height (Hpk) 302, 402, 502 of the structures 300, 400, 500 may range from approximately 25 of the pitches 304, 404, 504 to the corresponding structures 300, 400, 500. 80%. Alternatively, the average peak height (Hpk) 302, 402, 502 can be another fraction of the pitches 304, 404, 504. The base widths Wb 308, 408, 508 may be approximately equal to the pitches 304, 404, 504. Alternatively, the base widths Wb 308, 408, 508 may be different from the pitches 304, 404, 504. Base width (Wb) 508 may be approximately the same in two or more directions. For example, the base widths Wb 508 may be the same in two vertical directions extending parallel to the substrate 112. Alternatively, the base width Wb 508 can vary along different directions.

The parameters of the structures 300, 400, 500 in the template layer 136 may include whether the PV cell 102 (shown in FIG. 1) is a double or triple-junction cell 102 and / or a semiconductor layer stack 116. May be varied based on which of the semiconductor film or layer in the layer is a current limiting layer. For example, semiconductor layer stack 116 may be a single NIP stack or single PIN stack of doped amorphous or doped microcrystalline semiconductor layers, or two or more stacks of NIP and / or PIN doped amorphous or doped microcrystalline silicon layers. May comprise a sieve. One or more of the above parameters may be based on which of the semiconductor layers in the N-I-P and / or P-I-N stack is a current confined layer. For example, one or more layers in the N-I-P and / or P-I-N stack may limit the amount of current generated by the PV cell 102 when light strikes the PV cell 102. One or more of the parameters of the structures 300, 400, 500 may be based on which of these layers is the current confined layer.

In one embodiment, the PV cell 102 (shown in FIG. 1) comprises a microcrystalline silicon layer in a semiconductor layer stack 116 (shown in FIG. 1) and the microcrystalline silicon layer is a semiconductor layer stack 116. For the current limiting layer of, the pitches 304, 404, 504 of the structures 300, 400, 400 in the template layer 136 under the microcrystalline silicon layer may be between approximately 500 and 1500 nanometers. The microcrystalline silicon layer has an energy bandgap corresponding to infrared light having a wavelength between approximately 500 and 1500 nanometers. For example, if the pitches 304, 404, 504 approximately match the wavelength, the structures 300, 400, 500 may reflect increased amounts of infrared light with wavelengths between 500 and 1500 nanometers. The transition shapes 306, 406, 506 of the structures 300, 400, 500 may be flat incisions and the base widths Wb 308, 408, 508 range from 60% to 100 of the pitches 304, 404, 504. May be%. Peak heights Hpk 302, 402, 502 may be between 25% and 75% of the pitches 304, 404, 504. For example, the ratio of peak height (Hpk) 302, 402, 502 to pitch 304, 404, 504 is a structure 300, 400, 500 that reflects more light back into the semiconductor layer stack 116 compared to other ratios. Scattering angles within

In another example, the tandem of two semiconductor layer stacks 116 stacked on top of one another where the PV cell 102 is one layer stack 116 is an amorphous semiconductor layer and the other layer stack 116 is a microcrystalline semiconductor layer. ), The range of pitches 304, 404, 504 for template layer 136 may vary based on which of the semiconductor layer stacks 116 is a current confined layer. PV cell 102 is a double-junction microcrystalline silicon / amorphous silicon tandem array cell comprising a microcrystalline NIP or PIN doped semiconductor layer stack 116 applied over an amorphous NIP or PIN doped semiconductor layer stack 116. If the microcrystalline semiconductor layer stack 116 is a current confined layer, the pitches 304, 504, 604 may be between approximately 500 and 1500 nanometers. In contrast, if the amorphous semiconductor layer stack 116 is a current confined layer, the pitches 304, 404, 504 may be between approximately 350 and 1000 nanometers.

For a PV cell 102 (shown in FIG. 1) comprising a single semiconductor layer stack 116 of NIP or PIN doped semiconductor film, one or more parameters of the structures 300, 400, 500 may be a semiconductor layer stack. It can be altered based on the crystalline properties or structure of sieve 116 (shown in FIG. 1). For example, in a PV cell 102 that includes a single NIP or PIN stack of amorphous silicon layers in a semiconductor layer stack 116, the template layer 136 may have pitches 304, 404, 504 of approximately 500 nanometers. It may have a structure (300, 400, 500) having. The transition shapes 306, 406, 506 of the structures 300, 400, 500 may be flat and the base widths Wb 308, 408, 508 may be approximately 500 nanometers. Heights Hpk 302, 402, 502 may be approximately 250 nanometers. In another example, in a PV cell 102 that includes a single NIP or PIN stack of microcrystalline silicon layers in a semiconductor layer stack 116, the template layer 136 has a larger pitch 304 of approximately 1000 nanometers. Structures 300, 400, 500 with 404, 504. The transition shapes 306, 406, 506 of the structures 300, 400, 500 may be flat and the base widths Wb 308, 408, 508 may be larger by approximately 1000 nanometers. Heights Hpk 302, 402, 502 may be approximately 500 nanometers.

6 is a cross-sectional view of a PV cell 600 including a plurality of template layers 604, 614 according to another embodiment. The PV cell 600 is similar to the PV cell 102 (shown in FIG. 1) in that several PV cells 600 are electrically connected to form the PV device 100 (shown in FIG. 1). The PV cell 600 includes a substrate 602 that may be similar to the substrate 112 (shown in FIG. 1), and a lower template layer 604 that may be similar to the template layer 136 (shown in FIG. 1). Bottom electrode 606, which may be similar to bottom electrode 114 (shown in FIG. 1), and lower semiconductor layer stack 608, which may be similar to semiconductor layer stack 116 (shown in FIG. 1). It includes. The bottom electrode 606 may include a reflective layer 610 and a conductive layer 612 similar to the reflective layer 200 and the conductive layer 202 (shown in FIG. 2) of the bottom electrode 114.

The PV cell 600 includes an upper template layer 614 applied over or on the lower semiconductor layer stack 608. Upper template layer 614 may be applied to include one or more structures 300, 400 and / or 500 (shown in FIGS. 3-5) using the techniques described in this application. The patterns of the structures 300, 400, 500 in the template layers 604, 614 may be different as shown in FIG. 6. For example, pitches 304, 404, 504 (shown in FIGS. 3-5) of structures 300, 400, 500 may be larger in lower template layer 604 than in upper template layer 614.

The upper semiconductor layer stack 616 is coated on the upper template layer 614. The upper semiconductor layer stack 616 is a semiconductor layer stack 116 (shown in FIG. 1) in that the upper semiconductor layer stack 616 may comprise a NIP or PIN doped amorphous or microcrystalline semiconductor layer stack. May be similar to In one embodiment, the lower semiconductor layer stack 608 is an N-I-P or P-I-N stack of microcrystalline semiconductor layers, while the upper semiconductor layer stack 616 is an N-I-P or P-I-N stack of amorphous semiconductor layers. The parameters defining the structures 300, 400, 500 (shown in FIGS. 3-5) in the upper and lower template layers 614, 604 respectively are semiconductor layer stacks applied over the template layers 614, 604. 616, 608 may be adjusted. For example, the pitches 304, 404, 504 (shown in FIGS. 3-5) of the structures 300, 400, 500 in the upper template layer 614 are the structures 300, 400, 500 in the lower template layer 604. May be smaller than the pitch 304, 404, 504. As described above, the pitches 304, 404, 504 of the structures 300, 400, 500 in each template layer 604, 614 are trapped within the corresponding semiconductor layer stack 608, 616 or excite electrons. Can be based on the wavelength of light to be used.

An upper electrode 618, which may be similar to the upper electrode 118 (shown in FIG. 1), may be applied on the upper semiconductor layer stack 616. An adhesive layer 620 similar to the adhesive layer 120 (shown in FIG. 1) may be applied on the upper electrode 618. A cover sheet 622 similar to cover sheet 122 (shown in FIG. 1) may be disposed on adhesive layer 620.

7 is a cross-sectional view of a PV cell 700 with a textured electrode 704 according to another embodiment. The PV cell 700 may be similar to the PV cell 102 (shown in FIG. 1) in that several PV cells 700 are electrically connected to form a PV device 100 (shown in FIG. 1). The PV cell 700 includes a substrate 702 that may be similar to the substrate 112 (shown in FIG. 1). Template layer 704 may be applied on substrate 702 and formed to include one or more of the structures 300, 400, 500 (shown in FIGS. 3-5) described above. In the illustrated embodiment, template layer 704 includes a reflective layer 706 applied over substrate 702 and a conductive layer 708 applied over reflective layer 706. Reflective layer 706 may include or be formed from a metal or metal alloy that reflects incident light. Conductive layer 708 may be formed of a light transmissive conductive material, such as one or more materials in conductive layers 202 (shown in FIG. 2) and 612 (shown in FIG. 6). Reflective layer 706 and conductive layer 708 may be electrically coupled and may serve as a bottom electrode for PV cell 700. A semiconductor layer stack 710 is applied over template layer 704, which may be similar to semiconductor layer stack 116 (shown in FIG. 1).

Reflective layer 706 may be applied as an approximately smooth layer. The conductive layer 708 may be applied and / or etched to have the uneven upper surface 718. As with the top surface 138 (shown in FIG. 1) of the template layer 136 (shown in FIG. 1), the top surface 718 of the conductive layer 708 may have one or more scattering incident light toward the reflective layer 706. It may have a predetermined pattern or array of structures 300, 400 and / or 500 (shown in FIGS. 3-5). Incident light passing through the semiconductor layer stack 710 applied on the bottom electrode 704 may reflect at least a portion of the light back into the semiconductor layer stack 710. Some of the light may pass through the conductive layer 708 and be reflected at the reflective layer 706. Depending on the angle at which incident light meets the structures 300, 400, and 500 of the conductive layer 708, the light may change the optical path across the interface between the semiconductor layer stack 710 and the conductive layer 708. For example, incident light may pass through the semiconductor layer stack 710 and reach the conductive layer 708 along an optical path oriented perpendicular to the surface of the substrate 702. Based on the angle at which light meets the structures 300, 400, 500 of the conductive layer 708, the light may pass through the conductive layer 708 and meet the reflective layer 706 at an oblique angle. Thereafter, light is reflected back into the semiconductor layer stack 710 at a different angle from the angle initially passing through the semiconductor layer stack 710 through the conductive layer 708. Changing the angle at which the reflected light passes through the semiconductor layer stack 710 may increase the amount of light that is captured or excites electrons in the semiconductor layer stack 710.

An upper electrode 712, which may be similar to the upper electrode 118 (shown in FIG. 1), may be applied on the semiconductor layer stack 710. An adhesive layer 714 similar to the adhesive layer 120 (shown in FIG. 1) may be applied to the upper electrode 712. A cover sheet 716 similar to cover sheet 122 (shown in FIG. 1) may be disposed on adhesive layer 714.

8 is a cross-sectional view of a PV cell 800 with a textured template layer 804 formed of separated layers in accordance with another embodiment. The PV cell 800 may be similar to the PV cell 102 (shown in FIG. 1) in that several PV cells 800 are electrically connected to form a PV device 100 (shown in FIG. 1). The PV cell 800 includes a substrate 802 that may be similar to the substrate 112 (shown in FIG. 1).

Template layer 804 is applied on substrate 802. Template layer 804 includes a reflective layer 806 and a texturing layer 808. Reflective layer 806 may be similar to reflective layer 706 (shown in FIG. 7). For example, the reflective layer 806 may be a reflective metal or metal alloy applied on the substrate 802. The texturing layer 808 may be or an array of periodic individual island features 812 applied on the reflective layer 806. The island features 812 of the texturing layer 808 may be separate and separated from each other, as shown in FIG. 8, or may be connected to each other. The texturing layer 808 may be formed by applying dielectric and / or conductive particles onto the reflective layer 808. The size and / or location of these particles on the reflective layer 806 is set to form one or more structures 300, 400 and / or 500 (shown in FIGS. 3-5).

The bottom electrode 810 is applied only to the texturing layer 808 or to the texturing layer 808 and the reflective layer 806 as shown in FIG. 8. The bottom electrode 810 may be similar to the conductive layer 122 (shown in FIG. 1) of the bottom electrode 114 (shown in FIG. 1). For example, in one embodiment, the bottom electrode 810 includes or is formed of a light transmissive conductive material. The bottom electrode 810 may be in contact with or electrically coupled to the conductive reflective layer 806 between the island features 812 of the texturing layer 808. When the island shapes 812 are conductive, the bottom electrode 810 may be electrically connected to the island shapes 812 and the reflective layer 806.

On the bottom electrode 810, a semiconductor layer stack 814 similar to the semiconductor layer stack 116 (shown in FIG. 1) is applied. An upper electrode 816 may be applied on the semiconductor layer stack 814, which may be similar to the upper electrode 118 (shown in FIG. 1). An adhesive layer 818 similar to the adhesive layer 120 (shown in FIG. 1) may be applied on the upper electrode 816. A cover sheet 820 similar to the cover sheet 122 (shown in FIG. 1) may be disposed on the adhesive layer 818.

9 is a cross-sectional view of a PV cell 900 with a textured substrate 902 according to another embodiment. The PV cell 900 may be similar to the PV cell 102 (shown in FIG. 1) in that several PV cells 900 are electrically connected to form a PV device 100 (shown in FIG. 1). The PV cell 900 includes a textured substrate 902 that may include or be formed of the same or similar material as the substrate 112 (shown in FIG. 1). The substrate 902 of the illustrated embodiment is an integral template in that the substrate 902 includes one or more textured shapes that may be similar to the structures 300, 400 and / or 500 (shown in FIGS. 3-5). Layer. In one embodiment, the substrate 902 is applied as an approximately flat layer and etched to form the structures 300, 400 and / or 500. By way of example only, the substrate 902 may be etched by exposing the substrate 902 to an acid bath and / or by hitting the substrate 902 with particles. In one embodiment, the substrate 902 is at a predetermined grit blast material, particle size, particle velocity, and / or angle at which the particles strike the substrate 902, depending on the desired structure 300, 400, 500. Grit blasting is performed.

Once the substrate 902 has the desired texture and structure 300, 400 and / or 500 (shown in FIGS. 3-5), a bottom electrode 904 is provided on the substrate 902. The bottom electrode 904 may be similar to the bottom electrode 114 (shown in FIG. 1) and may have a reflective layer 906 and a conductive layer 908 similar to the reflective layer 200 and the conductive layer 202 (shown in FIG. 2). It may include. A semiconductor layer stack 910 similar to the semiconductor layer stack 116 (shown in FIG. 1) is provided on the bottom electrode 904. An upper electrode 912 similar to the upper electrode 118 (shown in FIG. 1) is applied over the semiconductor layer stack 910. An adhesive layer 914 similar to the adhesive layer 120 (shown in FIG. 1) may be coated on the upper electrode 912. A cover sheet 916 similar to the cover sheet 122 (shown in FIG. 1) may be disposed on the adhesive layer 912.

10 is a flow diagram illustrating a method 1000 of fabricating a PV device with a textured template layer, according to one embodiment. In step 1002, a substrate is prepared. For example, a substrate 112 (shown in FIG. 1) may be provided. In step 1004, a template layer is applied on the substrate. For example, template layer 136 (shown in FIG. 1) may be applied onto substrate 112. As noted above, the template layer imparts a predetermined textured pattern to one or more layers applied over the template layer to scatter and / or reflect light back into the semiconductor layer stack.

In step 1006, a bottom electrode is provided over the template layer. For example, a bottom electrode 114 (shown in FIG. 1) may be applied on template layer 136 (shown in FIG. 1). In step 1008, one or more semiconductor layer stacks, such as the semiconductor layer stack 116 (shown in FIG. 1), are applied over the bottom electrode 114.

In step 1010, an upper electrode is provided over the semiconductor layer stack. In one embodiment, an upper electrode 118 (shown in FIG. 1) is applied onto the semiconductor layer stack 116 (shown in FIG. 1). In step 1012, an adhesive is applied on the top electrode and a cover sheet is provided on the adhesive to surround the PV device. For example, an adhesive layer 120 (shown in FIG. 1) and a cover sheet 122 (shown in FIG. 1) may be provided on the upper electrode 118.

11 is a flow diagram illustrating a method 1100 of fabricating a PV device with a plurality of textured template layers, according to one embodiment. In step 1102, a substrate is prepared. For example, a substrate 602 (shown in FIG. 6) may be provided. In step 1104, a first template layer is applied over the substrate. For example, a lower template layer 604 (shown in FIG. 6) may be applied on the substrate 602. As noted above, the lower template layer imparts a predetermined textured pattern to one or more layers applied over the template layer to scatter and / or reflect light back into the semiconductor layer stack applied over the lower template.

In operation 1106, the upper electrode lower template layer is provided. For example, a bottom electrode 606 (shown in FIG. 6) may be applied on the lower template layer 604 (shown in FIG. 6). In step 1108, at least one semiconductor layer stack or semiconductor layer, such as the lower semiconductor layer stack 608 (shown in FIG. 6), is applied over the bottom electrode 606.

In operation 1110, the second template layer is provided on the lower semiconductor layer stack. For example, an upper template layer 614 (shown in FIG. 6) may be applied on the lower semiconductor layer stack 608 (shown in FIG. 6). In step 1112, the upper semiconductor layer stack is applied on the second template layer. In one embodiment, an upper semiconductor layer stack 616 (shown in FIG. 6) may be provided over the upper template layer 614.

In operation 1114, an upper electrode is provided on the second semiconductor layer stack. In one embodiment, an upper electrode 618 (shown in FIG. 6) is provided over the upper semiconductor layer stack 616 (shown in FIG. 6). In step 1116, an adhesive is applied on the top electrode and a cover sheet is provided on the adhesive to enclose the PV device. For example, an adhesive layer 620 (shown in FIG. 6) and a cover sheet 622 (shown in FIG. 6) may be provided over the upper electrode 618.

12 is a flow diagram illustrating a method 1200 of fabricating a PV device with textured electrodes, according to one embodiment. In step 1202, a substrate is prepared. For example, a substrate 702 (shown in FIG. 7) may be provided. In step 1204, a reflective layer is applied on the substrate. For example, a reflective layer 706 may be applied over the substrate 702. In step 1206, a textured conductive layer is applied over the reflective layer. In one embodiment, a textured conductive layer 708 is applied on the reflective layer 706 to form a textured bottom electrode.

In step 1208, one or more semiconductor layer stacks, such as the semiconductor layer stack 710 (shown in FIG. 7), may form the reflective layer 706 (shown in FIG. 7) and the textured conductive layer 706 (shown in FIG. 7). It is applied over the textured bottom electrode 704 (shown in FIG. 7).

In operation 1210, an upper electrode is provided over the semiconductor layer stack. In one embodiment, an upper electrode 712 (shown in FIG. 7) is applied over the upper semiconductor layer stack 710 (shown in FIG. 7). In step 1212, an adhesive is applied on the top electrode and a cover sheet is provided on the adhesive to enclose the PV device. For example, an adhesive layer 714 (shown in FIG. 7) and a cover sheet 716 (shown in FIG. 7) may be provided on the upper electrode 712.

FIG. 13 is a flow diagram illustrating a method 1300 of fabricating a PV device with a textured template layer formed of discrete layers in accordance with one embodiment. In step 1302, a substrate is prepared. For example, a substrate 802 (shown in FIG. 8) may be provided. In step 1304, a reflective layer is applied over the substrate. For example, a reflective layer 806 (shown in FIG. 8) may be applied on the substrate 802. In step 1306, a texturing layer is provided on the reflective layer. In one embodiment, a texturing layer 808 (shown in FIG. 8) is applied on the reflective layer 806. Reflective layer 806 and texturing layer 808 form individual layers of a textured template layer that reflect light back into the semiconductor layer stack.

In step 1308, a bottom electrode is provided over the texturing layer and / or the reflective layer. For example, as described above, the bottom electrode 810 (shown in FIG. 8) may be applied onto the texturing layer 808 (shown in FIG. 8) and / or the reflective layer 806 (shown in FIG. 8). In step 1310, one or more semiconductor layer stacks, such as the semiconductor layer stack 814 (shown in FIG. 8), are applied over the bottom electrode 810.

In operation 1312, an upper electrode is provided over the semiconductor layer stack. In one embodiment, an upper electrode 816 (shown in FIG. 8) is applied on the semiconductor layer stack 814 (shown in FIG. 8). In step 1314, an adhesive is applied on the top electrode and a cover sheet is provided on the adhesive to surround the PV device. For example, an adhesive layer 818 (shown in FIG. 8) and a cover sheet 820 (shown in FIG. 8) may be provided on the upper electrode 816.

14 is a flowchart of a method 1400 of manufacturing a PV device with a textured substrate, according to one embodiment. In step 1402, a textured substrate is prepared. For example, a substrate 902 (shown in FIG. 9) may be provided. As noted above, the substrate 902 may be etched to provide a textured surface that is imparted to additional layers applied to the substrate 902.

In step 1404, a bottom electrode is provided over the textured substrate. For example, a bottom electrode 904 (shown in FIG. 9) may be applied onto a textured substrate 902 (shown in FIG. 9). In step 1406, one or more semiconductor layer stacks, such as the semiconductor layer stack 910 (shown in FIG. 9), are applied over the bottom electrode 904.

In step 1408, an upper electrode is applied over the semiconductor layer stack. In one embodiment, an upper electrode 912 (shown in FIG. 9) is applied on the semiconductor layer stack 910 (shown in FIG. 9). In step 1410, an adhesive is applied on the top electrode and a cover sheet is provided on the adhesive to enclose the PV device. For example, an adhesive layer 914 (shown in FIG. 9) and a cover sheet 916 (shown in FIG. 9) may be provided on the upper electrode 912.

These methods 1000, 1100, 1200, 1300, 1400 describe various embodiments of fabricating or generating PV devices that include one or more texturing layers that help reflect light back into the semiconductor layer stack. Additional operations, methods, processes and / or steps may be performed in conjunction with the operations disclosed in these methods 1000, 1100, 1200, 1300, 1400 to manufacture PV devices. For example, depending on the PV device being manufactured, one or more layers provided in these methods 1000, 1100, 1200, 1300, 1400 may be used to electrically insulate or otherwise separate the layers within adjacent PV cells of the PV device. It may need to be etched.

It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and / or aspects thereof) may be used in combination with each other. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. The dimensions, types of materials, orientations, numbers, positions, etc. of the various components described herein are intended to limit the parameters of a particular embodiment, and are not meant to be limiting, but merely exemplary. Many other embodiments and modifications within the spirit and scope of the claims will be apparent to those skilled in the art based on the foregoing description. Accordingly, the scope of the present invention should be determined with reference to the appended claims, along with all equivalents of such claims. In the appended claims, the terms "comprising" and "in" are used interchangeably with the terms "comprising" and "in" respectively. In addition, in the following claims, the terms "first", "second", and "third" are used only in the order of listing and are not intended to impose numerical requirements on the subject. In addition, the limitations of the following claims are not written in "means plus function format" and the limitations of the claims are "means for" accompanying functional phrases without expressly describing additional structures. It is not intended to be interpreted based on 35 USC §112, paragraph 6, unless the phrase is used.

Claims (19)

A substrate;
A lower semiconductor layer stack disposed on the substrate;
A reflective conductive bottom electrode layer disposed between the substrate and the lower semiconductor layer stack;
A textured lower template layer disposed between the substrate and the bottom electrode layer, wherein the lower template layer has a first uneven upper surface that imparts a first uneven shape to the bottom electrode layer, and the bottom electrode layer is provided with the first uneven surface. It is a photovoltaic cell for reflecting light back into the lower semiconductor layer laminate according to the uneven shape,
The lower template layer includes a structure of a first pattern forming a first uneven shape, the structure of the first pattern having a base width determined by the crystalline structure of the lower semiconductor layer stack,
Photovoltaic cells,
An upper electrode disposed on the lower semiconductor layer stack;
An upper semiconductor layer stack disposed between the lower semiconductor layer stack and the upper electrode;
And a textured upper template layer disposed between the lower semiconductor layer stack and the upper semiconductor layer stack, wherein the upper template layer has a second pattern of structures to impart a second uneven shape to the upper semiconductor layer stack. It has a second uneven upper surface formed of,
The photovoltaic cell of claim 1, wherein the structure of the first pattern in the lower template layer is different from the structure of the second pattern in the upper template layer. The photovoltaic cell of claim 1, wherein the lower template layer comprises an array of one or more of a peak structure, a valley structure, or a curved structure that provides an uneven upper surface of the lower template layer. The method of claim 1, wherein the first uneven upper surface of the lower template layer is at least one of a predetermined pitch, a predetermined base width between adjacent structures, or a predetermined height protruding from the substrate or recessed into the lower template layer. The photovoltaic cell formed by the structure of the 1st pattern which has. The photovoltaic cell of claim 3, wherein at least one of a pitch, a base width, or a height of the structure of the first pattern is determined by the crystalline structure of the lower semiconductor layer stack. The photovoltaic cell of claim 3, wherein at least one of the pitch, base width, or height of the structure of the first pattern is determined by the wavelength of light reflected back into the lower semiconductor layer stack. delete The photovoltaic cell of claim 1, wherein the lower template layer comprises a plurality of individual island features separated from each other and disposed between the substrate and the bottom electrode.
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