KR101269903B1 - Die stack package and method for fabricating the same - Google Patents

Abstract

Open the first outer circuit patterns formed on the insulating layer, the bonding finger portion which is part of the first outer circuit patterns, and the control chip land portion which is part of the insulating layer on which the controller chip is to be mounted. A control chip mounted on a control chip land portion exposed by a stack of first and third solder masks stacked in a double layer, and a stack of first and third solder masks; And a printed circuit board (PCB) including a bonding finger connecting a control chip and a bonding finger portion exposed to the stacked portions of the first and third solder masks, and a die stack package using the same. packages) and their preparation methods.

Description

Die stack package and method for fabricating the same}

TECHNICAL FIELD The present invention relates to packaging technology, and more particularly, to a die stack package package and a manufacturing method thereof.

The printed circuit board (PCB) is configured to have wiring circuit patterns on an epoxy insulating layer. In the case of a die stack package in which a plurality of memory semiconductor chips are stacked to implement a large memory device, or a plurality of chips having various functions are stacked in one package, a chip stack in which a plurality of semiconductor chips are stacked is one Stacked on the PCB. In this case, a controller chip for controlling the operation of the individual semiconductor chips stacked on the chip stack of the semiconductor chips is stacked.

In the case of such a die stack package, since the length of the bonding wire connecting the PCB and the PCB stacked on the top is considerably longer, the length of the gold bonding wire lengthens the signal transmission path, thereby improving the operation speed of the device. This may be restricted. In addition, as the length of the bonding wire becomes longer, when molding with an epoxy molding compound (EMC), the bonding wire may be swept away or a defect may be shorted with other neighboring wires. Can be. This failure can act as a limiting factor in the yield of the die stack package.

The present invention proposes a printed circuit board (PCB), a manufacturing method, and a die stack package structure therein, in which a control chip for controlling a plurality of stacked semiconductor chips is embedded.

One aspect of the invention, the step of mounting a controller chip (controller chip) on the first insulating layer; The control chip is buried in the third insulating layer by aligning a second insulating layer and a first circuit layer under the first insulating layer, and aligning a third insulating layer and a second circuit layer on the first insulating layer. Stacking; Forming a first via hole through the second circuit layer and the third insulating layer to expose the control chip; And forming a plating layer filling the first via hole on the second circuit layer to form a first via connected to the control chip and a first outer circuit pattern connected to the first via by filling the first via hole. A control chip embedded printed circuit board (PCB) manufacturing method including the steps is provided.

The mounting of a controller chip on the first insulating layer may include preparing a copper clad laminate having third and fourth circuit layers on both sides of the first insulating layer; Patterning the third and fourth circuit layers to form a fiducial mark that becomes a position reference when the control chip is mounted; And arranging and mounting the control chip on the portion of the first insulating layer at the position where the control chip is to be mounted using the reference mark as a reference.

The method may further include forming a reference through hole by selectively removing portions of the second circuit layer, the third, first and second insulating layers, and the first circuit layer that overlap the reference mark after the lamination. .

The forming of the first via hole may include forming a mask pattern exposing a portion of the second circuit layer located at a position where the first via hole is to be formed by using the reference through hole as a reference; Etching away the portion of the second circuit layer exposed to the mask pattern; And laser drilling a lower portion of the third insulating layer exposed by the removal of the second circuit layer portion.

The second and third insulating layers may be introduced into a prepreg layer, and the first and second circuit layers may be introduced into a copper foil layer.

And forming a second via hole penetrating the second circuit layer, the third, first and second insulating layers, and the first circuit layer prior to forming the plating layer, wherein the plating layer comprises: A second via hole may be filled to form a second via that fills the second via hole, and a second outer circuit pattern connected to the second via may be formed.

The plating layer may be formed by a pattern plating process of selectively plating only the portions where the first and second vias and the first and second outer circuit patterns are located.

The plating layer is plated to fill the first and second via holes on the first and second circuit layers, and selectively etches the plating layer to form the first and second vias and the first and second outer circuit patterns. Image patterning may be further included.

The forming of the second via hole may include performing mechanical drilling through the second circuit layer, the third, first and second insulating layers, and the first circuit layer. .

Another aspect of the invention, the controller chip (controller chip) mounted on the first insulating layer; A second insulating layer laminated on the first insulating layer so that the control chip is buried and having a first outer circuit pattern on a surface thereof; A third insulating layer laminated on a lower surface of the first insulating layer and having a second outer circuit pattern on a surface thereof; And a first via penetrating through the second insulating layer to connect the control chip and the first outer circuit pattern to provide a control chip embedded printed circuit board (PCB).

A control chip embedded printed circuit board (PCB) further including a second via connecting the first and second outer circuit patterns through the second, first and third insulating layers may be provided.

Another aspect of the invention, the controller chip (controller chip) mounted on the first insulating layer; A third insulating layer laminated on the first insulating layer so that the control chip is buried and having a first outer circuit pattern on a surface thereof; A second insulating layer laminated on a lower surface of the first insulating layer and having a second outer circuit pattern on a surface thereof; A first via penetrating the third insulating layer to connect the control chip and the first outer circuit pattern; A solder mask covering the first outer circuit pattern and exposing a portion of the second outer circuit pattern; A stack of a plurality of semiconductor chips mounted on the solder mask portion above the first outer circuit pattern; A molding part protecting the stack of the semiconductor chips; And a solder ball attached to the second outer circuit pattern portion exposed by the solder mask.

Another aspect of the invention, forming the first outer circuit patterns on the insulating layer; A first solder mask is formed to open a portion of a bonding finger, which is part of the first outer circuit patterns, and a portion of a control chip land, which is a part of the insulating layer, on which a controller chip is to be mounted. Making; Forming a third solder mask layer covering the first solder mask; Exposing and developing the third solder mask layer to pattern a third solder mask that opens the bonding finger portion and the control chip land portion; Mounting a control chip on the control chip land portion exposed by the stacked portions of the first and third solder masks; And connecting the bonding finger portion exposed to the stacked portions of the first and third solder masks and the control chip with a bonding wire. present.

Forming second outer circuit patterns on an opposite surface of the insulating layer on which the first outer circuit patterns are formed; Forming a second solder mask that opens a portion of a ball land portion that is part of the second outer circuit patterns; Forming a fourth solder mask layer covering the second solder mask; And exposing and developing the fourth solder mask layer to form a fourth solder mask that opens the ball land portion to which solder balls are to be connected. 6. To present.

The bonding wire may be connected such that the height of the bonding wire is lower than the surface of the third solder mask.

Another aspect of the invention, the first outer circuit patterns formed on the insulating layer; First and third solders stacked in a double layer to open a portion of a bonding finger, which is a part of the first outer circuit patterns, and a portion of a control chip land, which is a part of the insulating layer on which a controller chip is to be mounted. Stacks of solder masks; A control chip mounted on the control chip land portion exposed by the stack of the first and third solder masks; And a bonding wire connecting the bonding finger portion exposed to the stacked portions of the first and third solder masks to the control chip, wherein the control chip is a printed circuit board (PCB).

Second outer circuit patterns formed on an opposite surface of the insulating layer on which the first outer circuit patterns are formed; And a stack of second and fourth solder masks stacked in a double layer to open a ball land portion to which solder balls are connected as part of the second outer circuit patterns. Present a circuit board (PCB).

Another aspect of the invention, the first outer circuit patterns formed on the insulating layer; First and third solders stacked in a double layer to open a portion of a bonding finger, which is a part of the first outer circuit patterns, and a portion of a control chip land, which is a part of the insulating layer on which a controller chip is to be mounted. Stacks of solder masks; A control chip mounted on the control chip land portion exposed by the stack of the first and third solder masks; A bonding wire connecting the bonding finger portion and the control chip exposed to the stacked portions of the first and third solder masks; A stack of a plurality of semiconductor chips mounted on the third solder mask via an adhesive layer; And a molding part which protects the stack of the semiconductor chips and protects the control chip and the bonding wire, and provides a die stack package.

Second outer circuit patterns formed on an opposite surface of the insulating layer on which the first outer circuit patterns are formed; A stack of second and fourth solder masks stacked in a double layer to open a ball land portion as part of the second outer circuit patterns; And a solder ball connected to the ball land part.

According to the present invention, a printed circuit board (PCB) and a manufacturing method incorporating a control chip for controlling a plurality of stacked semiconductor chips and a die stack package structure according thereto can be provided. A control chip that performs a signal transfer operation and a control operation on a semiconductor chip or an electronic product can be mounted inside the PCB, thereby eliminating or suppressing the use of bonding wires. Accordingly, signal transmission between the control chip and the PCB can be made directly, so that the length of the signal path can be effectively reduced. The speed of signal transmission can be improved, resulting in an improvement in the operating speed of the entire electronics or die stack package. In addition, it is possible to effectively suppress a package defect such as a short circuit between wires, which may be caused by the long length of the bonding wire, thereby improving the yield of the semiconductor device package.

1 to 10 are cross-sectional views illustrating a control chip embedded printed circuit board (PCB) and a manufacturing method according to the first embodiment of the present invention.
11 is a cross-sectional view illustrating a die stack package employing a printed circuit board (PCB) according to a first embodiment of the present invention.
12 to 17 are cross-sectional views illustrating a control chip embedded printed circuit board (PCB) and a manufacturing method according to a second embodiment of the present invention.
18 is a cross-sectional view illustrating a die stack package employing a printed circuit board (PCB) according to a second embodiment of the present invention.

According to an embodiment of the present invention, a controller chip may be mounted inside a printed circuit board (PCB) to shorten the length of the bonding wire or exclude the bonding wire. By inducing signal transmission directly between the control chip and the PCB, it is possible to shorten the signal transmission path, thereby improving the signal transmission speed and reducing the stacking structure of electronic products mounted on the PCB, in particular, multilayered semiconductor chips. It can improve the operation speed.

1 to 10 are cross-sectional views illustrating a control chip embedded printed circuit board (PCB) and a manufacturing method according to the first embodiment of the present invention. 11 is a cross-sectional view illustrating a die stack package employing a printed circuit board (PCB) according to a first embodiment of the present invention. The first embodiment of the present invention proposes an embedded PCB structure in which a control chip is embedded or embedded in a PCB, and a die stack package structure using the same.

Referring to FIG. 1, in order to manufacture a printed circuit board (PCB) for a die stack package or a multi chip package in which a plurality of semiconductor chips are stacked and packaged in a multi-layer, a first insulating layer Prepare 110. The first insulating layer 110 may be prepared as an insulating core layer, an epoxy resin layer, or a prepreg layer of a copper clad laminate (CCL). In order to form circuit patterns, the first insulating layer 110 may be formed in the form of a copper foil laminate in which copper foil layers for the third circuit layer 120 and the fourth circuit layer 130 are attached to both surfaces of the first insulating layer 110. Introduce.

Referring to FIG. 2, the third and fourth circuit layers 120 and 130 are patterned to form fiducial marks 131 on the first insulating layer 110. In this case, although not shown together with the reference mark 131, the inner circuit patterns may be patterned from the third and fourth circuit layers 120 and 130. The reference mark 131 or the inner circuit patterns may be patterned by forming a resist layer on the third and fourth circuit layers 120 and 130, and performing an selective etching process after exposure and development.

Referring to FIG. 3, a controller chip 200 is mounted on the first insulating layer 110. The control chip 200 controls the operation of individual semiconductor chips forming a stack of semiconductor chips mounted in a die stack package or a multilayer stacked chip package. In the embodiments of the present invention, the operation speed of the die stack package is controlled. In order to improve the signal transmission rate between the control chip 200 and the PCB.

The reference mark 131 is used as a reference for detecting a position on the first insulating layer 110 on which the control chip 200 is to be mounted when the control chip 200 is mounted. By detecting the reference mark 131, the precise position of the portion of the first insulating layer 110 on which the control chip 200 is to be mounted can be detected, and the control chip 200 is part of the first insulating layer 110 to be raised. Can be accurately mounted on

Referring to FIG. 4, the second insulating layer 310 and the first circuit layer 410 are arranged under the first insulating layer 110, and the third insulating layer 330 is disposed on the first insulating layer 110. And the second circuit layer 430. The second and third insulating layers 310 and 330 may be introduced into sheets of insulating resin such as a prepreg layer, respectively. The first and second circuit layers 410 and 430 may be introduced to form outer circuit patterns of the PCB, and may be introduced into the copper foil layer.

After aligning the second circuit layer 430, the third insulating layer 330, the first insulating layer 110, the second insulating layer 310, and the first circuit layer 410, lamination is performed by heating and pressing. By laminating. By the lamination process, a stacked structure is formed as shown in FIG. 5. In this case, the control chip 200 is impregnated with the third insulating layer 330 to be buried.

Referring to FIG. 6, a reference penetrating through the second circuit layer 430, the third insulating layer 330, the first insulating layer 110, the second insulating layer 310, and the first circuit layer 410 is provided. The hole 501 is formed. The reference through hole 501 is an X-ray guide drill process, and the second circuit layer 430, the third insulating layer 330, the first insulating layer 110, and the second insulating layer 310 are formed. And a portion of the first circuit layer 410 may be selectively removed. Through-hole inspection is performed by X-ray, and a reference through hole 501 may be formed by using a drilling apparatus. The reference through hole 501 may be introduced to match the wiring circuit patterns and the via holes in a subsequent process. The reference through hole 501 is introduced to provide position information of the control chip 200 or to provide position information on which a via hole or another through via hole or circuit pattern to expose the control chip 200 is to be formed.

Since the reference through hole 501 is formed at the position of the reference mark 131, information about the position of the control chip 200 provided by the reference mark 131 may be continuously provided during the subsequent process.

Referring to FIG. 7, the position of the control chip 200 is detected using the reference through hole 601 as a reference, and a position at which a first via hole for electrical connection to the control chip 200 is to be formed ( 601 is detected, and a mask pattern 600 that exposes a portion of the second circuit layer 430 positioned at the first via hole location 601 is formed. The mask pattern 600 may be formed by forming a resist layer such as a dry film, and exposing and developing the resist layer. Thereafter, the portion of the second circuit layer 430 exposed by the mask pattern 600 is selectively etched away. As shown in FIG. 8, the control chip 200 is performed by performing a laser drilling process for selectively removing a portion of the third insulating layer 330 exposed by the removal of the portion of the second circuit layer 430. A first via hole 602 exposing the gap is formed. The first via hole 602 exposes a portion of a chip pad (not shown) for electrical connection formed in the control chip 200. Thereafter, the mask pattern 600 is selectively removed.

Referring to FIG. 9, a second via hole 505 is formed through the second circuit layer 430, the third, first and second insulating layers 330, 110, 310, and the first circuit layer 410. do. The second via hole 505 is formed for the through connection via penetrating the PCB substrate. The second via hole 505 is formed by a mechanical drill process.

Referring to FIG. 10, a first copper plate 711 filling the first via hole 602 is formed on the second circuit layer 430 to fill the first via hole 602 to be connected to the control chip 200. ) And a first outer circuit pattern 713 connected to the first via 711. The plating layer fills the second via hole 505 to form a second via 715 connected to the first outer circuit pattern 713, and is formed to extend on the first circuit layer 410 to form the second outer side. A circuit pattern 717 is formed.

The process of patterning the first via 711, the first outer circuit pattern 713, the second via 715, and the second outer circuit pattern 717 may include first and second circuit layers 410 and 430, and A plating seed layer (not shown) is formed on the first and second via holes 602 and 505, and a plating layer is formed by copper plating on the plating seed layer, and then a resist layer (not shown) is formed on the plating layer. The resist layer is exposed, and the resist layer is exposed and developed to transfer an image pattern to form a resist pattern, which is then subjected to an image patterning process of selectively etching the plating layer with an etching mask. Alternatively, after forming a plating seed layer (not shown), a resist layer (not shown) is formed, the resist layer is exposed and developed to transfer an image pattern to form a resist pattern, and the resist pattern is exposed. The plating may be performed by a pattern plating process to selectively plate the plating layer only on the plating seed layer.

After forming the first via 711 and the first outer circuit pattern 713, the second via 715, and the second outer circuit pattern 717, a solder mask may be formed, although not shown. The surface PCB can be surface treated and routed to fabricate the final PCB as shown in FIG. 11.

The control chip embedded PCB manufactured as described with reference to FIGS. 1 to 10 includes a controller chip 200 mounted on the first insulating layer 110, and the control chip 200 is buried. The third insulating layer 330 stacked on the first insulating layer 110 and having the first outer circuit pattern 713 on the surface thereof, and the second insulating layer 310 having the second outer circuit pattern 717 on the surface thereof. The first via 715 may pass through the second insulating layer 310 to connect the control chip 200 and the first outer circuit pattern 713. A solder mask 800 covering the first outer circuit pattern 713 and exposing a portion of the second outer circuit pattern 717 to a ball land portion may be formed of a solder resist.

The stack 900 of the plurality of semiconductor chips 901 is attached to the solder mask 800 on the upper portion of the first outer circuit pattern 713 via an adhesive layer (not shown). A molding part 950 that protects the stack 900 of the semiconductor chips 901 is formed by a molding process using an epoxy molding material (EMC). A solder ball 850 as a connection member for external connection is attached to a portion of the second outer circuit pattern 717 exposed by the solder mask 800 to form a die stack package. In the die stack package shown in FIG. 11, the control chip 200 is buried in the third insulating layer 330 in the PCB, and the control chip 200 includes the first via 711 and the first outer circuit pattern 713. The second via and the second outer circuit pattern 717 may be electrically connected to the outside via the solder ball 850. Therefore, the signal transmission path with the control chip 200 can be shortened significantly more effectively than the case where the control chip 200 is attached to the upper side of the stack 900 of the semiconductor chips 901. Accordingly, direct signal transmission is possible without bonding wires with the control chip 200, thereby improving signal transmission speed and increasing yield.

12 to 17 are cross-sectional views illustrating a control chip embedded printed circuit board (PCB) and a manufacturing method according to a second embodiment of the present invention. 18 is a cross-sectional view illustrating a die stack package employing a printed circuit board (PCB) according to a second embodiment of the present invention. In the second embodiment of the present invention by forming a solder mask on the PCB in a multi-layer, to secure a space for mounting the control chip in the solder mask, the embedded printed circuit board (embedded PCB) structure consisting of a control chip embedded in the PCB And a die stack package structure using the same. In this case, the multi-layer solder mask structure may be implemented by a multi print solder resist method, that is, a process of forming a solder resist layer two or more times.

Referring to FIG. 12, in order to manufacture a printed circuit board (PCB) for a die stack package or a multi chip package in which a plurality of semiconductor chips are stacked and stacked in multiple layers, an insulating layer 10 may be used. Prepare. The insulating layer 10 may be prepared as an insulating core layer, an epoxy resin layer, or a prepreg layer of a copper clad laminate (CCL). In order to form the circuit patterns, the insulating layer 10 is formed in the form of a copper foil laminate plate having a copper foil layer for the first seed layer 21 and the second seed layer 23 on both sides of the insulating layer 10. Introduce.

Referring to FIG. 13, copper plating is performed on the first and second seed layers 21 and 23 to form a plating layer, and after the image pattern is transferred, the plating layer is patterned to form the first outer circuit patterns 22 and the first layer. 2 Outer circuit patterns 24 are formed. The image pattern transfer process is performed by forming a resist layer, exposing and developing a resist pattern, and patterning the plating layer by selectively etching away a portion of the plating layer exposed by the etching pattern with the resist pattern. Can be. Alternatively, the first and second outer circuit patterns 22 and 24 may be formed by pattern plating.

A first solder mask layer 31 and a second solder mask layer 33 are formed to cover the first and second outer circuit patterns 22 and 24, respectively. The first and second solder mask layers 31 and 33 may be formed by attaching a dry film solder resist having a thickness of about 35 μm by vacuum lamination.

Referring to FIG. 14, a portion of a bonding finger 25 that is a part of the first outer circuit patterns 22 and a control chip land part that is a part of the insulating layer 10 on which a controller chip is to be mounted ( 11) opening a portion of the ball land portion 27 which is part of the first solder mask 32 having the first opening 41 opening the portion and the second outer circuit patterns 24; The second solder mask 34 having the second open portion 43 is patterned. The first and second solder mask layers 31 and 33 are first exposed, developed and cured to be patterned into the first and second solder masks 32 and 34. The final first and second solder masks 32 and 34 may have a thickness of approximately 25 μm of a portion overlapping the first and second outer circuit patterns 22 and 24.

Referring to FIG. 15, the second opener part 43 is covered with the third solder mask layer 35 and the second solder mask 34 that cover the first solder mask 32 and fill the first open part 41. A fourth solder mask layer 37 is formed to fill. The third and fourth solder mask layers 35 and 37 may be formed by attaching a dry film solder resist having a thickness of about 35 μm by vacuum lamination.

Referring to FIG. 16, a portion of a bonding finger 25 that is part of the first outer circuit patterns 22 and a control chip land part that is a part of the insulating layer 10 on which a controller chip is to be mounted ( 11) opening a portion of the ball land portion 27 which is part of the third solder mask 36 and the second outer circuit pattern 24 having a third opening 45 opening the portion; The fourth solder mask 38 having the fourth open portion 47 is patterned. The third and fourth solder mask layers 35 and 37 are subjected to the second exposure and development, and are cured to pattern the third and fourth solder mask layers 36 and 38. The final stack of the first and third solder masks 32 and 36 may secure a thickness of at least about 60 μm of a portion overlapping the first outer circuit patterns 22.

Referring to FIG. 17, the control chip 50 is attached to the control chip land portion 11 exposed by the third open portion 45 of the stacked portions of the first and third solder masks 32 and 36. (Not shown). Subsequently, the bonding finger portion 25 and the control chip 50 exposed to the stacked portions of the first and third solder masks 32 and 36 are connected with a bonding wire 51. At this time, the depth of the third open portion 45 exposing the portion where the control chip 50 is mounted is approximately 20 μm, which is the height of the first outer circuit pattern 22, and the first and third solder masks 32 and 36. At least 60 µm, which is the height of the base plate, may be secured to approximately 80 µm or more.

Since the depth of the third open portion 45 on which the control chip 50 is mounted can be sufficiently secured, the height of the highest point of the bonding wire 51 connected to the control chip 50 is set to the surface of the third solder mask 36. Can be lower than the height. Accordingly, when the stack of subsequent semiconductor chips is mounted, a defect in which the semiconductor chip and the bonding wire 51 come into contact with each other can be effectively suppressed. As described above, the second embodiment of the present invention proposes a technique of stacking two or more solder masks 32 and 36 to deeply secure the depth of the third open part 45 on which the control chip 50 is to be mounted. do.

Referring to FIG. 18, in the die stack package according to the second embodiment of the present invention, a bonding finger which is part of the first outer circuit patterns 22 and the first outer circuit patterns 22 formed on the insulating layer 10 is formed. The first and third solder masks stacked in a double layer to open a portion of the control chip land portion 11, which is a portion of the insulating layer 10 on which the bonding finger 25 and the controller chip 50 are to be mounted. (solder mask: 32, 36), a control chip 50 mounted on the control chip land portion 11, a bonding wire for connecting the bonding finger portion 25 and the control chip 50: 51) a stack 60 of a plurality of semiconductor chips 61 mounted via an adhesive layer 63; And an EMC molding part 70 introduced to protect the stack 60 of the semiconductor chips 61 and to protect the control chip 50 and the bonding wire 51. The ball land part 27 also includes a stack of second and fourth solder masks 34 and 38 stacked in double layers to open a portion of the ball land part 27 that is part of the second outer circuit patterns 24. The die stack package may be configured to include solder balls 65 connected to it.

The control chip 50 of the die stack package configured as described above may be directly connected to the bonding finger portion 25 of the neighboring first outer circuit pattern 22 by the bonding wire 51, and thus, of the bonding wire 51. The length can be shortened effectively. Therefore, by improving the signal transmission speed with the control chip 50, it is possible to improve the operating speed of the die stack package or an electronic component including the same.

10, 110, 310, 330: insulation layer, 22, 24, 713, 717: circuit pattern,
25: bonding finger portion, 32, 34, 36, 38, 800: solder mask,
50, 200: control chip, 60, 900: a stack of semiconductor chips,
70, 950: EMC molding.

Claims (20)

Forming a fiducial mark of the copper foil layer on the first insulating layer;
Arranging and mounting the control chip on the portion of the first insulating layer at the position where the control chip is to be mounted using the reference mark as a reference;
The control chip is buried in the third insulating layer by aligning a second insulating layer and a first circuit layer under the first insulating layer, and aligning a third insulating layer and a second circuit layer on the first insulating layer. Stacking;
Selectively removing portions of the second circuit layer, the third, first and second insulating layers, and the first circuit layer overlapping the reference mark to form a reference through hole;
Forming a first via hole through the second circuit layer and the third insulating layer to expose the control chip to a position where the first via hole is to be formed by using the reference through hole as a reference;
Forming a second via hole penetrating the second circuit layer, the third, first and second insulating layers, and the first circuit layer;
A plating layer filling the first via hole and the second via hole is formed on the second circuit layer to fill the first via hole, and the first via circuit connected to the control chip and the first outer circuit connected to the first via. Forming a pattern, filling the second via hole to form a second via circuit pattern connected to the first outer circuit pattern and filling the second via hole and a second outer circuit pattern connected to the second via;
Forming a solder mask covering the first outer circuit pattern and exposing a portion of the second outer circuit pattern;
Stacking a plurality of semiconductor chips whose operation is to be controlled by the control chip on the solder mask portion above the first outer circuit pattern;
Forming a molding part to protect the laminate in which the semiconductor chips are stacked; And
Attaching a solder ball to the second outer circuit pattern portion exposed by the solder mask.
delete delete The method of claim 1,
Forming the first via hole
Forming a mask pattern exposing a portion of the second circuit layer positioned at a position where the first via hole is to be formed using the reference through hole as a reference;
Etching away the portion of the second circuit layer exposed to the mask pattern; And
A method of fabricating a die stack package comprising laser drilling a lower portion of the third insulating layer exposed by removal of the second circuit layer portion.
The method of claim 1,
The second and third insulating layers are introduced into the prepreg layer,
The first and second circuit layer is a die stack package manufacturing method introduced into the copper foil layer.
delete The method of claim 1,
The plating layer is
The die stack package manufacturing method of claim 1, wherein the first and second vias, and a pattern plating process for selectively plating only the portion where the first and second outer circuit patterns are to be located.
The method of claim 1,
The plating layer is
Plated to fill the first and second via holes on the first and second circuit layers,
And image patterning to selectively etch the plating layer to form the first and second vias and the first and second outer circuit patterns.
The method of claim 1,
Forming the second via hole
And performing mechanical drilling through the second circuit layer, the third, first and second insulating layers, and the first circuit layer.
delete delete delete delete delete delete delete delete delete delete delete

Images