JP5302920B2 - Manufacturing method of multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a multilayer wiring board for forming a highly precise alignment mark while peeling at a lamination process is prevented. <P>SOLUTION: In the manufacturing method of the multilayer wiring board, a peeling sheet 14 including copper foil 14a (metal layer) and copper foil 14b (base layer) is disposed on a support substrate 11. A first sheet on an outer peripheral side of a prescribed valid region of the peeling sheet 14 and second sheets corresponding to a plurality of alignment marks AM positioned at inner peripheral sides are removed, and resin material layers 20 are laminated and formed on upper parts of them. An end face including a peeling interface of the peeling sheet 14 is exposed and peeled and separated on the peeling interface with respect to a laminate before separation 10a where a build-up layer is formed by a lamination process. The multilayer wiring board can finally be obtained while the alignment mark AM having high position precision is used for the laminate after separation. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a multilayer wiring board that does not have a core substrate and is formed by alternately laminating resin insulating layers and conductor layers.

  In general, a multilayer wiring board in which a build-up layer is formed by alternately laminating resin insulating layers and conductor layers on both sides of a core board is used as a package for mounting electronic components. In the multilayer wiring board, the core board is made of a resin containing glass fiber, for example, and has a role of reinforcing the buildup layer with high rigidity. However, since the core substrate is formed thick, it hinders the miniaturization of the multilayer wiring substrate, and it is necessary to provide a through-hole conductor that electrically connects the build-up layers, so that the wiring length becomes long and high-frequency signal transmission is performed. There is a risk of performance degradation. Therefore, in recent years, a coreless multilayer wiring board having a structure suitable for miniaturization and capable of improving high-frequency signal transmission performance without providing the core board has been proposed (for example, see Patent Documents 1 and 2). ). Such a coreless multilayer wiring board is formed by, for example, forming a build-up layer on a support having two metal foils adhered in a peelable manner on the surface, and then peeling the two metal foils at the peeling interface. Thus, the buildup layer can be separated from the support and manufactured using a method for obtaining a wiring board.

JP 2009-289848 A JP 2007-214427 A

  By the way, when forming a multilayer wiring board, it is necessary to provide the alignment mark used as the position reference for forming a conductor pattern or a via conductor. For example, Patent Document 2 discloses a method in which reference holes are formed in the outer four corners of a product area by drilling or the like and used as alignment marks. In general, in the multilayer wiring board having such a structure, the peeling interface between the two metal foils is exposed on the side surface of the outer peripheral portion of the multilayer wiring board and the side surface of the reference hole. In this case, the exposed peeling interface is in a state where the chemicals used in the manufacturing process are soaked and so on, and may become a defective product before the completion of the multilayer wiring board, which may reduce the yield. As a countermeasure for this, Patent Document 2 discloses a technique of covering the peeling interface with a resin layer on the side surface of the outer peripheral portion of the multilayer wiring board and the side surface of the reference hole. However, since the reference hole penetrates the multilayer wiring board in the stacking direction, and the board area is limited by that amount, there is a problem that it is difficult to reduce the size of the multilayer wiring board. Further, since the resin layer that covers the side surface of the peeling interface with respect to the reference hole is formed, there is a problem that the manufacturing process of the multilayer wiring board becomes complicated.

  The present invention has been made to solve these problems, and provides a method for manufacturing a multilayer wiring board capable of forming a high-precision alignment mark while preventing peeling during the lamination process by patterning a release sheet. It aims to be realized.

  In order to solve the above problems, the present invention provides a method for producing a multilayer wiring board in which a resin insulating layer and a conductor layer are alternately laminated, and an underlayer and a metal are formed on at least one main surface side of a plate-like support substrate. A first sheet on the outer peripheral side of a predetermined effective area of the release sheet by patterning the release sheet composed of a base layer and a metal layer, and a sheet placement step of placing the layer in a peelable state A release sheet processing step for removing each portion and second sheet portions corresponding to a plurality of alignment marks located on the inner peripheral side of the predetermined effective area, and a resin material covering the upper portion of the release sheet are laminated A resin material forming step of filling the resin material in a state where the first sheet portion and the second sheet portion are removed in contact with the surface of the support base; A stacking step in which the conductor layer and the resin insulating layer are alternately stacked to form a buildup layer; and the pre-separation laminate including the support base material, the resin material, and the buildup layer. An exposure step that exposes an end face including the release interface of the release sheet on the outer peripheral side of the alignment mark; and after the exposure step, the release sheet is peeled off at the release interface, thereby removing the support base material from the laminate before separation. A separation step of separating the first and second multilayer wiring boards using the post-separation laminated body separated by the separation step.

  According to the method for manufacturing a multilayer wiring board of the present invention, a release sheet comprising a base layer and a metal layer that can be peeled is placed on a support base, and the first and second sheet portions are patterned by patterning the release sheet. A build-up layer is formed in a state where it is removed and filled with a resin material, and a laminated body separated from the support substrate in a state where the end surface including the release interface of the release sheet is exposed is obtained. A substrate is formed. In this case, the metal layer on the outer peripheral side of the effective area is removed by the first sheet portion, and a plurality of alignment marks corresponding to the second sheet portion are formed. Therefore, since the buildup layer is formed in a state where the release interface of the release sheet is covered with the resin material, it is possible to prevent the release interface from being peeled off due to the influence of chemicals used in the lamination process. In addition, the alignment mark formed in the initial stage is exposed on the surface of the release sheet after the separation process, and can be used in the subsequent processes. That is, it is possible to form a high-precision alignment mark that is not misaligned due to the influence of the laminating process, and can be used, for example, for etching a release sheet after the separating process.

  Two post-separation laminates may be obtained from the pre-separation laminate. In this case, if the release sheet, the resin material, and the build-up layer are respectively formed on both sides of the support base material, two post-separation laminates obtained by separating the support base material in the separation step are obtained. be able to.

  In addition to the above steps, it is preferable to perform a sheet roughening step for roughening the release sheet in the resin material forming step. Thereby, the adhesiveness of a peeling sheet and resin material improves by an anchor effect.

  When forming the plurality of alignment marks, various structures and forming methods can be applied. For example, the plurality of alignment marks arranged at the four corners of the predetermined effective area may be formed. Alternatively, the base layer may be a metal foil, and after the release sheet is covered with a photoresist in the release sheet processing step, the first sheet portion and the second sheet portion may be removed by etching.

  In the exposing step, it is preferable that the stacked body is cut in a stacking direction along a cutting line set on an outer peripheral side of an area where the plurality of alignment marks are arranged. In this case, the release interface of the release sheet is exposed on the side surface of the laminate before separation.

  As described above, according to the present invention, when a so-called coreless multilayer wiring board is manufactured, it is effective that a plurality of exposed peeling interfaces are peeled off during the lamination process by patterning the peeling sheet and covering with a resin material. While preventing, it is possible to form a plurality of alignment marks formed on the surface of the peeling interface at the initial stage and perform positioning with high accuracy using the alignment marks after the separation step. Further, since this alignment mark does not have a structure using a through hole, it is suitable for downsizing of the multilayer wiring board and the manufacturing process is simplified. Furthermore, since the resin material is adhered to the release sheet at the alignment mark, the resin material and the release sheet remain in a moderately close contact state, for example, preventing the release interface from being peeled off at the time of cutting the laminate before separation. it can.

It is the 1st section view explaining the manufacturing method of the multilayer wiring board of this embodiment. It is a 2nd cross-section figure explaining the manufacturing method of the multilayer wiring board of this embodiment. It is the 3rd sectional structure figure explaining the manufacturing method of the multilayer wiring board of this embodiment, and the plane structure figure corresponding to it. It is a 4th cross-section figure explaining the manufacturing method of the multilayer wiring board of this embodiment. It is a 5th cross-section figure explaining the manufacturing method of the multilayer wiring board of this embodiment. It is a 6th cross-section figure explaining the manufacturing method of the multilayer wiring board of this embodiment. It is a 7th cross-section figure explaining the manufacturing method of the multilayer wiring board of this embodiment. It is an 8th sectional view explaining the manufacturing method of the multilayer wiring board of this embodiment. It is a 9th sectional view explaining the manufacturing method of the multilayer wiring board of this embodiment. It is a 10th cross-section figure explaining the manufacturing method of the multilayer wiring board of this embodiment. It is the 1st section view explaining the modification of the manufacturing method of the multilayer wiring board of this embodiment. It is a 2nd sectional structure figure explaining the modification of the manufacturing method of the multilayer wiring board of this embodiment. It is a 3rd sectional view explaining the modification of the manufacturing method of the multilayer wiring board of this embodiment. It is a 4th sectional view showing the modification of the manufacturing method of the multilayer wiring board of this embodiment. FIG. 10 is a fifth sectional view illustrating a modification of the method for manufacturing a multilayer wiring board according to the present embodiment. It is a 6th cross-section figure explaining the modification of the manufacturing method of the multilayer wiring board of this embodiment.

  Preferred embodiments of the present invention will be described below with reference to the drawings. However, the embodiment described below is an example of a form to which the technical idea of the present invention is applied, and the present invention is not limited by the content of the present embodiment.

  The manufacturing method of the multilayer wiring board of this embodiment is demonstrated with reference to FIGS. First, as shown in FIG. 1, a plate-like support base material 11 having a copper foil 12 attached on both sides is prepared. The support base 11 is made of, for example, a resin containing glass fiber and has high rigidity. In a state where the release sheet 14 is disposed on the surface of each copper foil 12 of the support base 11 with a prepreg 13 made of, for example, a thermosetting resin, for example, pressure bonding is performed by, for example, vacuum hot pressing (sheet arrangement of the present invention) Process). After the pressure bonding, the outer edge portion is cut and shaped into a predetermined size to obtain the support substrate 11 integrated with the release sheet 14 on the surface. The support base 11 is formed in a rectangular shape having a length of 300 mm and a width of 300 mm, for example. On the other hand, the release sheet 14 has a structure in which two copper foils 14a and 14b having different thicknesses are adhered in a peelable manner. The thickness of the copper foil 14a (the metal layer of the present invention) located outside the support base 11 is larger than the thickness of the copper foil 14b (the base layer of the present invention) located inside.

  Next, as shown in FIG. 2, resist patterns 15 are formed by laminating a photosensitive dry film on each surface of the release sheets 14 on both sides, and exposing and developing. In this resist pattern 15, the alignment mark forming portion Pa and the outer peripheral portion Po are respectively removed. Subsequently, after the etching is performed on the release sheet 14 in a state where the resist pattern 15 is formed, the resist pattern 15 is removed. As a result, as shown in FIG. 3A, the copper foils 14a and 14b are partially removed from the release sheet 14 in the region immediately below the alignment mark forming portion Pa and the region immediately below the outer peripheral portion Po. The release sheet processing step of the present invention), and the surface of the prepreg 13 at that portion is exposed. In addition, it is desirable to roughen the surface of the release sheet 14 in the etched state (sheet roughening step of the present invention). Thereby, the adhesiveness of the peeling sheet 14 and the below-mentioned resin material can be improved.

  Here, with reference to FIG. 3B, a planar structure when the stacked body in the state of FIG. 3A is viewed from above will be described. As shown in FIG. 3B, the outer peripheral portion Po from which the copper foils 14a and 14b are removed by a predetermined width is formed within the entire plane of the support base 11, and the inner region is rectangular. It is an effective area A1. The outer peripheral portion Po outside the effective area A1 is used in a laminating process described later, but is removed by cutting associated with an exposing process described later. On the other hand, the copper foils 14a and 14b remain in the effective area A1, but the copper foils 14a and 14b are removed from the alignment mark forming portions Pa at the four corners. The alignment mark forming portion Pa is a structure for forming an alignment mark AM used for positioning in each step after the separation step described later. For positioning in each step before the separation step, an alignment pattern (not shown) separately provided outside the effective area A1 is used.

  Note that the structure of the alignment mark AM (alignment mark formation portion Pa) illustrated in FIG. 3B is an example, and the number, arrangement, and shape of the alignment mark AM can be determined as appropriate. However, it is desirable to arrange at least two with a relatively small size because of the requirement of positioning accuracy using the alignment mark AM.

  Next, as shown in FIG. 4, a resin material in the form of a film is laminated from the upper part of the release sheet 14 whose surface is roughened, and is cured by applying pressure under vacuum to form a resin material layer 20. (Resin material forming step of the present invention). As a result, the surface of the release sheet 14 is covered with the resin material layer 20, and the resin material layer 20 is filled in the removed portions of the release sheet 14 in the alignment mark forming portion Pa and the outer peripheral portion Po. Thereby, the structure of the alignment mark AM is formed in the alignment mark forming portion Pa. Further, when the outer peripheral portion Pa is covered with the resin material layer 20, the peeling interface between the copper foil 14a and the copper foil 14b is not exposed as shown in FIG. effective.

  Next, as shown in FIG. 5, a plurality of via holes are formed by laser processing at predetermined positions of the resin material layers 20 on both sides, and after a desmear process for removing smears in the via holes, A via conductor 40 is formed. Subsequently, the surfaces of the resin material layers 20 on both sides are patterned to form the conductor layers 30 respectively. Furthermore, a film-like resin material is laminated so as to cover the conductor layers 30 on both sides, and the resin material is cured by pressurizing and heating under vacuum to form the resin insulating layer 21.

  Next, as shown in FIG. 6, a plurality of via holes are formed by laser processing at predetermined positions of the resin insulating layers 21 on both sides, and after desmearing treatment for removing smears in the via holes, electroless copper plating is performed. Then, a thin copper film is formed, and a dry film is pasted on the surface of the copper film and exposed and developed. Subsequently, copper is deposited on the portion where the dry film is removed by performing electrolytic copper plating, and the via conductor 41 and the conductor layer 31 are formed simultaneously (semi-additive method). Further, a film-like resin material is laminated so as to cover the conductor layers 31 on both sides, and the resin material is cured by pressurizing and heating under vacuum to form the resin insulating layer 22. The opening 42 is formed by applying laser processing to the pattern portion of the conductor layer 31 in the resin insulating layer 22. As described above, a buildup layer in which the resin insulating layers 21 and 22 and the conductor layers 30 and 31 are alternately formed is formed (a stacking process of the present invention), and a stacked body 10a (a stacked body before separation of the present invention). Is obtained.

  Next, as shown in FIG. 7, the laminated body 10a obtained in the above-described lamination step is shown by a cutting line (indicated by a broken line in the figure) set slightly on the inner peripheral side from the effective area A1 (FIG. 3B). ) Cut along. As a result, an unnecessary outer peripheral region is removed from the laminated body 10a, and an end surface including the release interface of the release sheet 14 is exposed on the side surface (exposing process of the present invention). In this state, the copper foil 14a and the copper foil 14b that are in close contact with each of the upper and lower release sheets 14 are peeled along the peeling interface. As a result, as shown in FIG. 8, the support base material 11 is separated from the laminate 10a (the separation step of the present invention), and two laminates 10b having the same structure (the separated laminate of the present invention) can be obtained. it can. At this time, in each laminated body 10b, the surface of the copper foil 14a on which the structure of the alignment mark AM is formed appears.

  As described above, according to each step of FIGS. 1 to 8 of the present embodiment, the resin material layer 20 covers the alignment mark forming portion Pa and the outer peripheral portion Po removed by etching the release sheet 14. Therefore, the peeling end surface of the peeling sheet 14 is protected by the resin material layer 20 at the outer peripheral portion Po in the above-described laminating step, and peeling of the peeling end surface due to penetration of chemicals or the like can be reliably prevented. On the other hand, in the exposure step, the copper foil 14a and the resin material layer 20 are adhered to each other at the alignment mark AM, thereby improving the adhesion between the two, and the release sheet 14 is effective when cutting the laminate 10a. However, it becomes difficult to peel off at the peeling interface. However, in the subsequent separation step, the release sheet 14 can be easily peeled off at the release interface by applying a predetermined external force. This is because the area of the close contact portion between the copper foil 14a of the alignment mark AM and the resin material layer 20 is relatively small, so that the adhesiveness does not prevent the separation in the separation step.

  Next, a resist pattern is formed by laminating a photosensitive dry film on the laminated body 10b obtained in the separation step, and exposing and developing, and after etching the copper foil 14a, the resist pattern is removed. To do. In this case, the alignment mark AM is used as a position reference for resist pattern formation. As a result, as shown in FIG. 9, patterning is performed in which a predetermined portion of the copper foil 14 a is removed, and a pad 50 directly connected to the via conductor 40 is formed. At this point, electrical connection via the conductor layer 31, the via conductor 41, the conductor layer 30, the via conductor 40, and the pad 50 becomes possible.

  Next, as shown in FIG. 10, after forming a solder resist layer 51 by applying and curing a photosensitive epoxy resin on the lower surface side of the resin material layer 20, an opening is formed in the pad 50. Although only FIGS. 9 and 10 are shown as the steps after the separation step, various processes are performed on the stacked body 10b obtained in FIG. 10 according to the use and function of the final multilayer wiring board. be able to.

  For example, a solder ball used for a BGA package may be connected to the pad 50. Further, for example, solder bumps for connecting to the terminals of the semiconductor chip may be connected to the upper opening 42. Further, for example, a through hole penetrating the multilayer body 10b may be formed, and a through hole conductor that can be electrically connected via the through hole may be formed. When these steps are performed when the alignment mark AM remains, the alignment mark AM can be used as a position reference. Note that when a multi-cavity substrate form is assumed, the finally obtained laminate 10b can be cut to obtain a plurality of multilayer wiring boards.

  As described above, according to each process (FIGS. 9 and 10) after the separation process of the present embodiment, various structures can be formed by positioning using the alignment mark AM. As shown in FIG. 2, since the positional accuracy of the alignment mark AM is determined at the initial stage, the positional accuracy can be significantly improved as compared with the case where the alignment mark is formed after the stacking process, for example. For example, when the alignment mark AM is not provided at the initial time, it is necessary to form the alignment mark on the upper layer side instead of the lower layer copper foil 14a in the laminated body 10b. Deterioration of position accuracy is unavoidable due to accumulation. In the present embodiment, since the alignment mark AM that is not affected by misalignment due to repeated lamination is formed in advance, high positional accuracy can be realized.

  Regarding the multilayer wiring board of the present invention, the manufacturing method described with reference to FIGS. 1 to 10 is an example, and there are various modifications. Hereinafter, a modification in which the semi-additive method is applied to some processes will be described with reference to FIGS. In this modification, the description of the steps common to the manufacturing method of FIGS. 1 to 10 is omitted, and different steps are mainly described.

  In this modified example, as shown in FIG. 11, from the state shown in FIG. 3A, a dry film is laminated on each surface of the release sheets 14 on both sides and exposed and developed, whereby the resist pattern 60 is formed. Form. Subsequently, as shown in FIG. 12, electroless copper plating and electrolytic copper plating are applied to the surface of each release sheet 14 to form a conductor layer 61. Thereafter, as shown in FIG. 13, a film-like resin material is laminated from the top of the conductor layer 61, and cured by pressurizing and heating under vacuum to form a resin material layer 62, and the surface thereof is polished. . As a result, as in FIG. 4, the resin material layer 62 is filled in the removed portion of the copper foil 14a, and the structure of the alignment mark AM is formed.

  Next, as shown in FIG. 14, a conductor layer 63 is formed on the surface side of each conductor layer 61 using a semi-additive method. Thereafter, each step in FIGS. 4 to 7 is performed in common with the above embodiment. Thereafter, as shown in FIG. 15, in the separation step, two laminated bodies 10c having the same structure (the separated laminated body of the present invention) can be obtained. As shown in FIG. 16, when the entire copper foil 14 a and the conductor layer 61 are etched and removed from the laminated body 10 c by a known method, the conductor layer 63 is partially exposed to the outside. Thereafter, various processes can be performed on the stacked body 10c of FIG. 16 according to the use and function of the final multilayer wiring board. In this modification, the alignment mark AM is removed at a relatively early stage (FIG. 16), but it is possible to use the alignment mark AM according to the situation in the process.

  The contents of the present invention have been specifically described above based on the present embodiment, but the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, in the present embodiment, the release sheet 14 in which the copper foils 14a and 14b are adhered in a peelable manner has been described, but the release sheet 14 may be formed using various metal materials that are in close contact with each other without being limited to copper. Well, its thickness can also be changed. Further, the resin material layer 20, the resin insulating layers 30 and 31, the via conductors 40 and 41, the opening 42, the pad 50, the solder resist layer 51, and other constituent members may be used as long as the effects of the present invention can be obtained. The structure, shape, and formation method of the above can be changed without being limited to the contents disclosed in the present embodiment.

10a, 10b, 10c ... laminate 11 ... support substrate 12 ... copper foil 13 ... prepreg 14 ... release sheet 14a, 14b ... copper foil 15 ... resist pattern 20, 62 ... resin material layers 21, 22 ... resin insulation layer 30, 31, 61, 63 ... conductor layers 40, 41 ... via conductor 42 ... opening 50 ... pad 51 ... solder resist layer 60 ... resist pattern

Claims (6)

In the method of manufacturing a multilayer wiring board in which resin insulation layers and conductor layers are alternately laminated,
A sheet disposing step of disposing the base layer and the metal layer in a peelable state on at least one main surface side of the plate-shaped support base;
By patterning the release sheet composed of the base layer and the metal layer, the first sheet portion on the outer periphery side of the predetermined effective area and the inner periphery side of the predetermined effective area of the release sheet. A release sheet processing step for removing each of the second sheet portions corresponding to the plurality of alignment marks positioned;
A resin material that covers the upper part of the release sheet is laminated, and the resin material is filled in a state where the first sheet portion and the second sheet portion are removed in contact with the surface of the support substrate. A resin material forming step;
A laminating step of alternately laminating the conductor layer and the resin insulating layer on the resin material to form a build-up layer;
An exposure step of exposing an end surface including a release interface of the release sheet on the outer peripheral side of the plurality of alignment marks, with respect to the pre-separation laminate including the support base material, the resin material, and the buildup layer;
A separation step of separating the support substrate from the pre-separation laminate by separating the release sheet at the release interface after the exposing step;
And forming one or a plurality of multilayer wiring boards using the post-separation laminate separated in the separation step.   The release sheet, the resin material, and the build-up layer are respectively formed on both sides of the support base material, and two post-separation laminates obtained by separating the support base material in the separation step are obtained. The method for manufacturing a multilayer wiring board according to claim 1.   The method for producing a multilayer wiring board according to claim 1, further comprising a sheet roughening step of roughening the release sheet prior to the resin material forming step.   4. The method of manufacturing a multilayer wiring board according to claim 1, wherein the plurality of alignment marks are arranged at four corners of the predetermined effective area.   The underlayer is a metal foil, and in the release sheet processing step, after the release sheet is covered with a photoresist, the first sheet portion and the second sheet portion are removed by etching. The manufacturing method of the multilayer wiring board of Claim 1. In the exposing step, the pre-separation laminate is cut in the laminating direction along a cutting line set on the outer peripheral side of the region where the plurality of alignment marks are arranged, and the release sheet is formed on a side surface of the pre-separation laminate. The method according to claim 1, wherein the peeling interface is exposed.

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