KR101197763B1 - Thin film transistor for liquid crystal display and method for manufacturing the same - Google Patents

Abstract

More particularly, the present invention is to improve image quality by reducing parasitic capacitance (Cgd) in a liquid crystal display, and includes a gate electrode, a gate insulating film, and a semiconductor layer formed to have recesses formed by cutting the gate line from one side of the gate line toward the center. A “U” shaped source electrode which overlaps the gate electrode and spaces the main portion of the gate electrode at regular intervals, and an “I” shaped shape formed so that a part of the outer portion overlaps with the gate electrode in a region corresponding to the main portion of the gate electrode. A thin film transistor for a liquid crystal display device including a drain electrode and an ohmic contact layer, and a method of manufacturing the same.

Liquid Crystal Display, Thin Film Transistor, Gate Electrode, Parasitic Capacitance

Description

Thin film transistor for liquid crystal display and its manufacturing method {Thin film transistor for liquid crystal display and method for manufacturing the same}

1 is a plan view schematically illustrating some pixels of a liquid crystal display according to the related art.

FIG. 2 is a plan view illustrating the thin film transistor of FIG. 1.

FIG. 3 is a cross-sectional view illustrating a surface of FIG. 2.

4 is a plan view illustrating some pixels of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a plan view illustrating the gate electrode of FIG. 4.

6 is a cross-sectional view illustrating the II-II 'surface of FIG. 4.

7 is a waveform diagram of a data voltage applied to the pixel electrode of FIG. 4.

8 is a flowchart illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

9 is a plan view illustrating some pixels of a liquid crystal display according to another exemplary embodiment of the present invention.

10 is a plan view illustrating some pixels of a liquid crystal display according to yet another exemplary embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS (S)

100: transparent insulating substrate 110: gate insulating film

120, 121, 122: gate lines 130, 131, 132: data lines

140: thin film transistor 141: gate electrode

142: source electrode 143: drain electrode

144: semiconductor layer 145, 146: ohmic contact layer

150, 152, and 154: pixel electrodes 151 and 153: pixel lines

160, 162: common line 161, 163: common electrode

CH: contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor for a liquid crystal display device and a method for manufacturing the same, and more particularly, to a thin film transistor and a method for manufacturing the same that can improve image quality by reducing parasitic capacitance (Cgd).

The liquid crystal display injects a liquid crystal material having anisotropic dielectric constant between the color filter substrate and the array substrate, which are upper and lower transparent insulating substrates, and adjusts the intensity of the electric field formed in the liquid crystal material to change the molecular arrangement of the liquid crystal material. The display device expresses a desired image by adjusting the amount of light transmitted through the transparent insulating substrate. As the liquid crystal display device, a thin film transistor liquid crystal display device (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

1 is a plan view schematically illustrating some pixels of a conventional array substrate for a liquid crystal display device.

As shown in FIG. 1, an array substrate for a liquid crystal display device includes a matrix of gate lines 20 that form a row, and data lines 30 that form a column and intersect the gate lines 20. The pixel regions P divided by the gate lines 20 and the data lines 30 intersecting with each other are formed together to form a frame (screen). When the scan pulse is sequentially applied to the gate lines 20, a data voltage is applied to the data lines 30 in response to the scan pulse, and one frame is displayed on the liquid crystal display.

A thin film having a gate electrode 41, a source electrode 42, and a drain electrode 43 in each pixel area P and positioned at an intersection of the gate line 20 and the data line 30 to operate as a switching element. The transistor 40 and the pixel electrode 50 connected to the drain electrode 43 of the thin film transistor 40 are constituted.

The thin film transistor 40 applies a data voltage supplied from the data line 30 to the pixel electrode 50 in response to a scan pulse supplied from the gate line 20.

During the period in which the thin film transistor 40 is turned on by the gate high voltage Vgh of the scan pulse supplied to the gate line 20, it corresponds to the difference voltage between the data voltage and the common voltage supplied from the data line 30. The voltage is charged in the pixel electrode 50, and the voltage charged in the pixel electrode 50 is maintained during the period in which the thin film transistor 40 is turned off by the gate low voltage Vgl of the scan pulse.

In this case, the gate high voltage Vgh is generated between the gate electrode 41 and the drain electrode 43 of the thin film transistor 40 at the falling edge of the scan pulse falling to the gate low voltage Vgl. The voltage charged in the pixel electrode 50 by the parasitic capacitor Cgd or the like decreases by? Vp, which is called a feed through voltage or a kick back voltage.

The feed-throw voltage ΔVp is changed in accordance with the data voltage applied to the liquid crystal display, causing flicker or afterimage, thereby degrading the image quality. It is defined as a function.

Here, Cgd is a parasitic capacitance formed between the gate electrode 41 and the drain electrode 43 of the thin film transistor 40, Clc is the liquid crystal capacitance, and Cst is the voltage charged in the pixel electrode 50 for one frame. Storage capacitance to maintain. DELTA Vg is a difference voltage between the gate high voltage VGH and the gate low voltage VGL forming a scan pulse.

FIG. 2 is a plan view illustrating a portion of the thin film transistor of FIG. 1, and FIG. 3 is a cross-sectional view illustrating a plane of FIG. 2.

2 and 3, the thin film transistor 40 on the transparent insulating substrate 10 may include a gate electrode 41, a gate insulating layer 11, a semiconductor layer 44, and a semiconductor formed as part of the gate line 20. The channel portion 44_1 on the layer 44, the ohmic contacts 45 and 46, the source electrode 42, the drain electrode 43, and the like.

As shown in FIG. 2, the drain electrode 43 is formed in an I-shape and connected to the pixel electrode 50, and the source electrode 42 is formed in a U-shape surrounding the drain electrode 43. It is connected to the line 30. That is, the U-shaped source electrode 42 is formed, and the drain electrode 43 has an asymmetric structure formed to be positioned at regular intervals with the source electrode 42 in the groove of the source electrode 42.

The drain electrode 43 and the source electrode 42 overlap the gate electrode 41 by a predetermined area.

The U-shaped thin film transistor 40 having such a configuration is used for the purpose of improving the overlay margin or reducing the area occupied by the source and drain electrodes 42 and 43 to improve the aperture ratio.

However, in the thin film transistor 40, parasitic capacitance Cgd exists in proportion to the overlapping area between the drain electrode 43 and the gate electrode 41, and a feed through voltage generated due to the parasitic capacitance Cgd ΔVp) causes problems such as flicker and afterimage. At this time, if the storage capacitance Cst is increased to reduce the influence due to the feed through voltage ΔVp, the opening ratio may be reduced as a result.

On the other hand, an IPS (In-Plane Switching) type liquid crystal display device requires a higher driving voltage than TN (Twisted Nematic) type, so that the feed through voltage (ΔVp) is also increased, resulting in more flicker or afterimage. There is a problem that a lot is caused, and thus the image quality is further reduced.

Therefore, the technical problem to be achieved by the present invention is to minimize the parasitic capacitance (Cgd) by reducing the overlap area between the gate electrode and the drain electrode, thereby reducing the feed through voltage (ΔVp), solve the flicker or afterimage, etc. To provide a thin film transistor for a liquid crystal display device that can improve the.

Another object of the present invention is to provide a method of manufacturing a thin film transistor for a liquid crystal display device which can efficiently manufacture such a thin film transistor.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

A thin film transistor for a liquid crystal display according to an exemplary embodiment of the present invention for achieving the technical problem is a gate electrode formed to have a recess formed by cutting the gate line toward the center from one side of the gate line on the transparent insulating substrate, and A semiconductor layer formed on an entire surface of the transparent insulating substrate, the gate insulating layer covering the gate electrode, a semiconductor layer formed on the gate insulating layer and undoped with an amorphous silicon material, and having a region corresponding to the gate electrode; And a source electrode having a “U” shape formed on the semiconductor layer while overlapping the gate electrode and surrounding the recess at regular intervals, and formed on the semiconductor layer on the recess, wherein the recess includes the recess. A "I" shaped drain electrode overlapping the gate electrode, the source electrode and And an ohmic contact layer formed at an interface between the drain electrode and the semiconductor layer and made of an n + hydrogenated amorphous silicon material doped with a high concentration of n-type impurities.

A method of manufacturing a thin film transistor for a liquid crystal display according to an exemplary embodiment of the present invention includes forming a gate electrode on a transparent insulating substrate to have a recess formed by cutting a gate line from one side of the gate line toward a center thereof, and forming the gate electrode. Forming a gate insulating film formed over the insulating substrate and covering the gate electrode, an undoped amorphous silicon layer over the gate insulating film, and an n + hydrogenated amorphous silicon layer doped with a high concentration of n-type impurities. After the deposition in sequence, forming a semiconductor layer by etching leaving a region corresponding to the gate electrode, depositing a metal layer on the semiconductor layer while overlapping the gate electrode, and etching the metal layer at a predetermined interval. A source electrode having a “U” shape surrounding the recess with respect to the recess; Forming an “I” shaped drain electrode which is formed on the semiconductor layer and overlaps the gate electrode including the recessed portion to face each other, and exposes the semiconductor layer of a portion of the region corresponding to the gate electrode; forming a channel portion by etching the n + hydrogenated amorphous silicon layer, and forming an ohmic contact layer formed at an interface between the source electrode and the drain electrode and the semiconductor layer, and having an n + hydrogenated amorphous silicon material doped with a high concentration of n-type impurities. It characterized by comprising the step of forming.

In the thin film transistor for a liquid crystal display device and a method for manufacturing the same according to a preferred embodiment of the present invention, the width of the source electrode is preferably 2 μm to 10 μm.

In the thin film transistor for a liquid crystal display device and a method of manufacturing the same according to a preferred embodiment of the present invention, the width of the drain electrode is preferably 2 μm to 10 μm.

In the thin film transistor for liquid crystal display according to the preferred embodiment of the present invention and the manufacturing method thereof, the width of the drain electrode overlapping with the gate electrode is preferably 1/2 or less of the drain electrode width.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention, and methods of achieving the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, a thin film transistor for a liquid crystal display and a method of manufacturing the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a plan view illustrating some pixels of the liquid crystal display according to the exemplary embodiment, and illustrates the pixel region P of the array substrate for the liquid crystal display device applied to the TN structure.

5 is a plan view illustrating the gate electrode of FIG. 4, and FIG. 6 is a cross-sectional view illustrating the II-II ′ surface of FIG. 4.

4 and 6, the pixel region P becomes an area defined by the intersection of the gate line 120 and the data line 130, and at the intersection of the gate line 120 and the data line 130. The thin film transistor 140 is configured.

The pixel electrode P is formed of a transparent conductive metal having a relatively high transmittance of light such as indium-tin-oxide (ITO) and the pixel electrode contacting the thin film transistor 140 through the contact hole CH ( 150).

The thin film transistor 140 includes a gate electrode 141 formed on the transparent insulating substrate 100, a gate insulating layer 110 formed on the gate electrode 141, a semiconductor layer 144, and an ohmic contact layer 145, 146. ), A source electrode 142, a drain electrode 143, and the like.

The semiconductor layer 144 is formed on the gate insulating layer 110 and is made of an undoped amorphous silicon material.

The gate electrode 141 is formed as part of the gate line 120, and as shown in FIGS. 5 and 6, is formed to have a concave groove in a region corresponding to the drain electrode 143. The concave groove 141-1 of the gate electrode 141 may be expressed as a recess 141-1 formed by cutting the gate line 120 from one side SD of the gate line 120 toward the center CT. Can be.

The U-shaped source electrode 142 is formed to branch from the data line 130 near the gate electrode 141 to overlap with the gate electrode 141, and to be constant with the source electrode 142 inside the source electrode 142. An I-shaped drain electrode 143 is formed between the channel portions 144_1 of the semiconductor layer 144 by a gap.

More specifically, the source electrode 142 is formed on the semiconductor layer 144 so as to overlap the gate electrode 141 to surround the groove of the gate electrode 141 at regular intervals. The source electrode 142 is formed on the semiconductor layer 144 while overlapping the gate electrode 141, and surrounds the recess 141-1 at regular intervals. The drain electrode 143 is formed in a region corresponding to the groove of the gate electrode 141 on the semiconductor layer 144, and is positioned inside the source electrode 142 so that only a part of the outer portion overlaps the gate electrode 141. . The drain electrode 143 is formed on the semiconductor layer 144 on the recess 141-1 and overlaps the gate electrode 141 including the recess 141-1. The portion overlapping with the drain electrode 143 on the gate electrode 141 is removed by etching while leaving only a part of the outer portion.

Ohmic contact layers 145 and 146 are formed at the interface between the source electrode 142 and the drain electrode 143 and the semiconductor layer 144, and n + hydrogenated amorphous silicon in which n-type impurities are heavily doped. Made of matter.

Although not shown, a protective film made of an inorganic insulating material or an organic insulating material such as silicon nitride film (SiNx) is formed on the thin film transistor 140, and the contact hole CH exposing the drain electrode 143 is formed in the protective film. The pixel electrode 150 is formed on the upper surface of the pixel electrode 150 to be in contact with the drain electrode 143 through the contact hole CH.

In such a structure, the area of the semiconductor layer 144 overlapping the source electrode 142 and the drain electrode 143 is reduced by an area corresponding to the groove of the gate electrode 141, whereby the gate electrode 141 and the drain electrode ( Compared to the conventional case in which no groove is formed in the region where the 143 overlaps, the parasitic capacitance Cgd may be reduced to reduce the feed through voltage ΔVp.

On the other hand, since the current flowing when the voltage is applied is proportional to the electrode width to the distance between the electrodes, in order to secure a certain amount or more of the current flowing from the source electrode 142 to the drain electrode 143, the electrode width must be maintained to a certain degree, As a result, there is a limit in reducing the parasitic capacitance (Cgd) by reducing the electrode width or overlap area.

Therefore, in order to reduce the parasitic capacitance Cgd while securing a constant current, grooves are formed on the gate electrode 141 in consideration of overlapping portions with the drain electrode 143, but the gate electrode 141 and the drain electrode 143 are formed. By providing an overlay margin between the layers to be formed so that the outer portion of the drain electrode 143 partially overlaps with the gate electrode 141, the channel portion 144_1 is not formed on the semiconductor layer 144, so that the defect It should not happen.

More specifically, the electrode width of the source electrode 142 or the drain electrode 143 is in the range of 2 μm to 10 μm to allow development of the photoresist film when forming the electrode while ensuring a constant current, and the drain electrode 143 is a gate electrode ( The width overlapping the 141 is less than 1/2 of the width of the drain electrode 143 to minimize the parasitic capacitance Cgd.

The width W of the drain electrode 143 is 5 μm, the overlapping length C of the gate electrode 141 and the drain electrode 143 is 15 μm, and the outer side of the drain electrode 143 is the gate electrode 141. In the case where the overlay margin (m) overlapping with each other is 1 μm, the gate electrode 141 and the drain electrode 143 which assume a groove of the gate electrode 141 as a quadrangle and generate a feed through voltage ΔVp Calculating the overlap area causing parasitic capacitor (Cgd) between is as follows.

When there is no groove, the overlap area between the gate electrode 141 and the drain electrode 143 becomes 15 μm × 5 μm (overlap length × electrode width) = 75 μm ² , but the overlap area when the groove is formed (Overlap ) Is 33 μm ² , which is reduced by the area of the groove (14 μm × 3 μm = 42 μm ² ) from 75 μm ² of the overlapping area of the two electrodes 141 and 143 when there is no groove.

In liquid crystal capacitance (Clc), storage capacitance (Cst), and parasitic capacitance (Cgd) (see Equation 1), which affect the feed through voltage (ΔVp), the liquid crystal capacitance (Clc) is a material property, and thus is difficult to change. In addition, when the storage capacitance Cst is increased to reduce the feed through voltage ΔVp, the aperture ratio may be reduced.

However, as shown in FIG. 5, when the overlapping region between the gate electrode 141 and the drain electrode 143 formed toward the pixel region P is reduced to less than half, the parasitic capacitance Cgd is easily reduced to 50% or less. You can.

When the overlap region between the gate electrode 141 and the drain electrode 143 is reduced to 1/2, the change in the parasitic capacitance Cgd and the feed through voltage ΔVp is expressed as follows.

Therefore, since twice the liquid crystal capacitance Clc and twice the storage capacitance Cst can be used, it is very effective in reducing the feed through voltage ΔVp and to reduce the feed through voltage ΔVp. Since the required storage capacitance region Cst can be used as the aperture ratio portion, the aperture ratio can be improved as a result.

As such, by reducing the overlapping area between the drain electrode 143 and the gate electrode 141 by an area corresponding to the groove of the gate electrode 141, the parasitic capacitance Cgd generated in the cumulative area is reduced, and the parasitic capacitance ( The feed-through voltage ΔVp by Cgd) is lowered, and the aperture ratio is secured to realize clear image quality.

FIG. 7 is a waveform diagram of data voltages applied to the pixel electrode of FIG. 4, and illustrates the shape of the data voltage applied to the pixel electrode 150 when the thin film transistor 140 of the present invention is applied to the liquid crystal display. .

According to the present invention, as shown in FIG. 7, the feed through voltage DELTA Vp is reduced, which is advantageous in afterimages, and the common voltage Vcom is easily set, which is effective for improving flicker.

In addition, since it is not necessary to increase the storage capacitance Cst in order to reduce the influence of the feed through voltage ΔVp, the area can be optimized and the regulation rate can be increased.

8 is a flowchart illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

First, in step S100, the gate electrode layer 141 having a concave groove is formed by depositing a gate electrode layer on the transparent insulating substrate 100, and then patterning the gate electrode layer deposited by a photo process using a first mask and an etching process. To form. As shown in FIGS. 5 and 6, the recessed groove 141-1 of the gate electrode 141 cuts the gate line 120 from one side SD of the gate line 120 toward the center CT. It can be represented by the recessed portion (141-1) formed.

Next, in step S110, the gate insulating layer 110 is formed on the entire surface of the transparent insulating substrate 100 including the gate electrode 141. That is, the gate insulating layer 110 is formed on the entire surface of the transparent insulating substrate 100 and covers the gate electrode 141.

Next, in step S120, the ohmic contact layer 145 or 146 of the n + hydrogenated amorphous silicon material in which the semiconductor layer 144 of the undoped amorphous silicon material and the n-type impurities are heavily doped on the gate insulating layer 110 is formed. The semiconductor layer 144 and the ohmic contact layer 145 except for the region corresponding to the gate electrode 141 and the region where the source and drain electrodes 142 and 143 are to be formed using the second mask. 146) is etched and patterned.

Next, in step S130, after depositing the metal layer, the source and drain electrodes 142 and 143 are formed by etching the deposited metal layer using a third mask. In this case, the source electrode 142 is formed in a “U” shape so as to overlap the gate electrode 141 and surround the groove of the gate electrode 141 at regular intervals, that is, the source electrode 142 is “U”. After forming a metal shape and overlapping the gate electrode 141 and depositing a metal layer on the semiconductor layer 144, the metal layer is etched to surround the recess 141-1 at regular intervals, and the drain electrode 143 Is formed in an “I” shape so as to correspond to the groove of the gate electrode 141, and is positioned inside the source electrode 142 so that a part of the outer portion overlaps the gate electrode 141. The drain electrode 143 is formed on the semiconductor layer 144 on the recess 141-1, and includes the recess 141-1 to have an “I” shape overlapping the gate electrode 141.

Next, in step S140, back channel etching (BCE) is performed on the ohmic contacts 145 and 146 in the region corresponding to the gate electrode 141 using the source and drain electrodes 142 and 143 as masks. The channel portion 144_1 of the semiconductor layer 144 is defined by removing a process to expose a portion of the semiconductor layer 144 to complete the ohmic contacts 145 and 146.

Thereafter, an insulating material is coated to form a protective film, and a contact hole CH exposing the drain electrode 143 is formed in the protective film by using a fourth mask. The transparent conductive layer is deposited and the pixel electrode 150 connected to the drain electrode 143 through the contact hole CH is formed using the fifth mask.

The thin film transistor 140 described with reference to FIGS. 4 to 7 has not only a TN structure as shown in FIG. 4 but also a liquid crystal having various structures such as IPS (In-Plane Switching) or S-IPS II (Super In-Plane Switching II) structure. It can be extended to the display device.

In the case of the IPS or S-IPS II structure, since the driving voltage is relatively higher than that of the TN structure, and the feed through voltage ΔVp is also increased, the thin film transistor 140 of the present invention is applied to the parasitic capacitance Cgd. The increase in the feed through voltage DELTA Vp can be suppressed more efficiently.

9 and 10 are modified examples of the array substrate for the liquid crystal display device to which the thin film transistor 140 is applied.

FIG. 9 is a plan view illustrating some pixels of a liquid crystal display according to another exemplary embodiment, and illustrates a pixel area P of an array substrate for a liquid crystal display device applied to an IPS structure.

9, in the array substrate for a liquid crystal display according to another exemplary embodiment, the gate line 121 and the common line 160 are arranged in parallel in the horizontal direction, and the data line 131 in the vertical direction. The gate line 121 and the common line 160 are vertically arranged.

On the pixel region P, the common electrodes 161 branched from the common line 160 and the pixel electrodes 152 branched from the pixel line 151 contacting the thin film transistor 140 through the contact hole CH. These are crossed each other.

FIG. 10 is a plan view illustrating some pixels of a liquid crystal display according to another exemplary embodiment, and illustrates a pixel region P of an array substrate for a liquid crystal display device applied to an S-IPS II structure.

The gate line 122 and the data line 132 are formed to cross each other to define the pixel region P, and the thin film transistor 140 is formed at the intersection of the two lines 122 and 132. The common line 162 includes two horizontal lines arranged in parallel with the gate line 122 and two vertical lines formed in a curved structure to connect the common lines 162 to surround the pixel area P. The pixel electrode 154 and the common electrode 163 are alternately formed on (P) to implement a wide viewing angle.

In more detail, the gate line 122 and the two lines of the common line 162 are parallel to each other, and the curved data line 132 is parallel to the other two lines of the common line 162. In the common line 162, the pixel electrode 154 is branched from the pixel line 153 in which the common electrode 163 is disposed in parallel with the gate line 122.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand.

Therefore, it should be understood that the above-described embodiments are provided so that those skilled in the art can fully understand the scope of the present invention. Therefore, it should be understood that the embodiments are to be considered in all respects as illustrative and not restrictive, The invention is only defined by the scope of the claims.

The thin film transistor for liquid crystal display according to the preferred embodiment of the present invention made as described above is optimized to reduce the overlap area between the gate electrode and the drain electrode, thereby minimizing the parasitic capacitance (Cgd), and thereby the feed through The image quality can be improved by reducing the voltage DELTA Vp and solving flicker or afterimage.

The method of manufacturing a thin film transistor for a liquid crystal display according to a preferred embodiment of the present invention can efficiently manufacture such a thin film transistor.

Claims (8)

A gate electrode formed on the transparent insulating substrate to have a recessed portion formed by cutting the gate line toward a center from one side of the gate line; A gate insulating film formed on an entire surface of the transparent insulating substrate and covering the gate electrode; A semiconductor layer formed on the gate insulating layer and formed of an undoped amorphous silicon material, wherein the region corresponding to the gate electrode forms a channel portion; A “U” shaped source electrode overlapping the gate electrode and formed on the semiconductor layer and surrounding the recess at regular intervals; A “I” shaped drain electrode formed on the semiconductor layer on the recess and overlapping the gate electrode including the recess; And And a resistive contact layer formed at an interface between the source electrode and the drain electrode and the semiconductor layer, the resistive contact layer made of an n + hydrogenated amorphous silicon material doped with a high concentration of n-type impurities. The method of claim 1, The width of the source electrode is a thin film transistor for a liquid crystal display device, characterized in that 2㎛ to 10㎛. The method of claim 1, The width of the drain electrode is a thin film transistor for a liquid crystal display device, characterized in that 2㎛ to 10㎛. The method of claim 1, The width of the drain electrode overlapping the gate electrode is 1/2 or less of the width of the drain electrode. Forming a gate electrode on the transparent insulating substrate so as to have a recessed portion formed by cutting the gate line toward the center from one side of the gate line; Forming a gate insulating film formed on an entire surface of the transparent insulating substrate and covering the gate electrode; After depositing an undoped amorphous silicon layer on top of the gate insulating layer and an n + hydrogenated amorphous silicon layer doped with a high concentration of n-type impurities, the semiconductor layer is etched while leaving a region corresponding to the gate electrode. Forming; After depositing a metal layer on the semiconductor layer while overlapping the gate electrode, the metal layer is formed on the source electrode of the "U" shape surrounding the recess at regular intervals by etching the metal layer, and the semiconductor layer on the recess Forming a drain electrode having an “I” shape overlapping the gate electrode including the recessed portion to face each other; And The n + hydrogenated amorphous silicon layer is etched to expose the semiconductor layer of the partial region corresponding to the gate electrode to define a channel portion, and is formed at an interface between the source electrode and the drain electrode and the semiconductor layer, and a high concentration of n-type impurities is formed. A method of manufacturing a thin film transistor for a liquid crystal display device, the method comprising: forming a resistive contact layer made of an n + hydrogenated amorphous silicon material doped with N 2. The method of claim 5, The width of the source electrode is formed in the range of 2㎛ 10㎛ method for manufacturing a thin film transistor for a liquid crystal display device. The method of claim 5, The width of the drain electrode is formed in the range of 2㎛ 10㎛ method for manufacturing a thin film transistor for a liquid crystal display device. The method of claim 5, The width of the drain electrode overlapping the gate electrode is formed to be 1/2 or less of the width of the drain electrode.

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