KR101193448B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a high aperture liquid crystal display device, the liquid crystal display device according to the present invention, the first substrate and the second substrate; Gate lines and data lines arranged vertically and horizontally on the first substrate to define unit pixels; A semiconductor layer formed on the first substrate; A source electrode and a drain electrode receiving a signal from the data line; A pixel electrode receiving a signal from the source electrode and the drain electrode; A common line transferring a common signal; A first light blocking layer formed along an outer line of the unit pixel and overlapping the pixel electrode with a first width; And a liquid crystal layer formed between the first and second substrates.

Liquid crystal display device, aperture ratio, first light blocking layer

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a perspective view showing a conventional liquid crystal display device.

2A is a plan view of a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 2B is a sectional view taken along line II ′ of FIG. 1A; FIG.

3A to 3D are flowcharts illustrating a manufacturing process of a liquid crystal display device according to an exemplary embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

1, 101: gate line 3, 103: data line

111: common line 111a: first light shielding layer

20, 120: pixel electrode W1: first width

W2: 2nd width

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of maximizing the aperture ratio while forming a set storage capacitance.

The liquid crystal display device is a display device in which data signals according to image information are individually supplied to liquid crystal cells arranged in a matrix form so that a desired image can be displayed by adjusting the light transmittance of the liquid crystal cells.

1 is a perspective view schematically illustrating a conventional liquid crystal display device, wherein a liquid crystal display device generally includes a first substrate 10 that is a thin film transistor array substrate, a second substrate 50 that is a color filter substrate, and the first and second substrates. It consists of the liquid crystal layer 30 formed between (10, 50).

In addition, a plurality of gate lines 1 and data lines 3 intersect the first substrate 10 to define a pixel area, and switching is performed in an area where the gate lines 1 and the data lines 3 intersect. A thin film transistor T, which is an element, is formed to switch each pixel region. The pixel electrode 20 for driving the liquid crystal of the liquid crystal layer 30 is formed in the pixel region.

In addition, color filters 52 such as R (red), G (green), and B (blue) are disposed on the second substrate 50 so as to correspond to each pixel area on the first substrate 10 one-to-one. A black matrix 51 is formed in a checkered pattern to shield a portion where light leakage occurs due to abnormal operation of the liquid crystal in the boundary region between the pixel regions. In addition, a common electrode 53 for driving liquid crystal molecules is formed on the color filters 52 by generating an electric field together with the pixel electrode 20.

By the way, in the conventional liquid crystal display device as described above, the black matrix 51 serves to shield light leakage, but has a problem of encroaching on the aperture ratio of the liquid crystal panel because it is designed with a processing margin.

When forming the black matrix, the reason for the process margin is to prepare for the case where the bonding error between the first substrate 10 and the second substrate 50 occurs.

Thus, for this reason, there is a problem that the opening ratio of the liquid crystal panel is lowered by the process margin.

Accordingly, the present invention has been made in view of the above-described problems, and by forming the first light blocking layer on the boundary region between pixels on the array substrate, that is, the region in which the liquid crystal molecules are abnormally operated by the electric field distortion, the color filter is formed. An object of the present invention is to provide a liquid crystal display device capable of improving the aperture ratio by minimizing the bonding margin with the substrate.

In addition, the present invention extends a common line on an array substrate to form the first light blocking layer, and overlaps a portion of the first light blocking layer and the pixel electrode, thereby providing a new storage capacitance between the first light blocking layer and the pixel electrode. It is another object of the present invention to provide a liquid crystal display device capable of improving the aperture ratio by forming a storage capacitance, thereby reducing the width of the storage capacitor, which is a light blocking region arranged in the pixel, corresponding to the formed storage capacitance.

Other objects and features of the present invention will be described in the following description of the invention and claims.

Therefore, the liquid crystal display device according to the present invention to achieve the above object, the first substrate and the second substrate; Gate lines and data lines arranged vertically and horizontally on the first substrate to define unit pixels; A semiconductor layer formed on the first substrate; A source electrode and a drain electrode receiving a signal from the data line; A pixel electrode receiving a signal from the source electrode and the drain electrode; A common line transferring a common signal; A first light blocking layer formed along an outer line of the unit pixel and overlapping the pixel electrode with a first width; And a liquid crystal layer formed between the first and second substrates.

At this time, the first width is characterized in that it is formed in the range of 0.1 ㎛ ~ 3 ㎛.

The first light blocking layer may be formed by extending a portion of the common line, and a storage capacitance may be generated between the first light blocking layer and the pixel electrode.

In addition, a second light blocking layer may be further formed on the second substrate, and the second light blocking layer may be disposed in a space between the data line and the first light blocking layer and a space between the gate line and the first light blocking layer. It may be formed in a corresponding region.

And, the semiconductor layer is characterized in that the polycrystalline silicon semiconductor layer.

The liquid crystal display device may further include a storage first electrode formed by extending a portion of the semiconductor layer; And a storage second electrode formed as a part of the common line, wherein the drain electrode extends over the storage first electrode and the storage second electrode, and the storage first electrode and the storage second electrode. Together, the storage capacitors can be formed.

The liquid crystal display device may further include at least one gate electrode protruding from the gate line.

Hereinafter, a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2A is a plan view of a liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line II ′ of FIG. 2A.

First, the liquid crystal display device of the present invention includes a first substrate, which is an array substrate, a second substrate, which is a color filter substrate, and a liquid crystal layer between the first and second substrates.

On the transparent first substrate, as shown in the figure, the gate lines 101 and the data lines 103 are vertically and horizontally arranged to define unit pixels. The thin film transistor 109 is formed near the intersection of the gate line 101 and the data line 103. The thin film transistor 109 includes a semiconductor layer 105 formed of polycrystalline silicon, two gate electrodes 101a and 101b formed thereon, and source / drain electrodes 102a and 102b. At this time, the two gate electrodes 101a and 101b constituting the dual gate are formed to protrude from the gate line 101. When the dual gate electrode is used as described above, a leakage current generated when the gate signal is blocked There is an advantage that can be reduced. However, it is also possible to use a single gate electrode.

The source electrode 102a protrudes from the data line 103, is connected to the semiconductor layer 105 through the first contact hole 107a, and one side of the drain electrode 119b is the second contact hole. The signal is connected to the semiconductor layer 105 through 107b, and the other side of the signal is applied to the transparent pixel electrode 120 through the third contact hole 107c. The pixel electrode 320 applied with the signal forms an electric field together with a common electrode (not shown) formed on the second substrate 150 to drive the liquid crystal of the liquid crystal layer (not shown).

A portion of the semiconductor layer 105 extends to constitute the storage first electrode 105 ′. In addition, a storage second electrode 111 ′ formed as a part of the common line 111 is formed on the storage first electrode 105 ′, and a drain electrode is formed on the story second electrode 111 ′. 102b is extended to form a storage capacitor together with the storage first and second electrodes 105 ', 111'.

In the liquid crystal display device configured as described above, when a gate signal is applied to the gate electrodes 101a and 101b, a channel is formed in the semiconductor layer 105 so that the data signal of the source electrode 102a is applied to the semiconductor layer 105. The storage capacitor charges the gate voltage while the gate signal is applied to the gate electrodes 101a and 101b. The storage capacitor transfers data to the pixel electrode 120 when the next gate line 101 is driven. Discharges the charged voltage while the voltage is supplied to prevent voltage variations of the pixel electrode 120. On the other hand, when a gate signal having a low level is applied to the gate electrodes 101a and 101b, the channel formed in the semiconductor layer 105 is cut off and the transmission of the data signal to the drain electrode 102b is stopped.

The common line 111 through which the common signal is transmitted extends along the outer region of the unit pixel to form the first light blocking layer 111a. One side of the first light blocking layer 111a overlaps a corner region of the pixel electrode 120, and the other side thereof is spaced apart from the pixel electrode 120 and the data line 103 and adjacent to the pixel electrode 120. It is formed to correspond to the spaced space of the gate line 101 of the pixel. Therefore, light is prevented from leaking to the outer region of the unit pixel, that is, the region in which the liquid crystal molecules are abnormally operated by the electric field distortion.

Since the first light blocking layer 111a of the present invention is formed on the first substrate 100 which is an array substrate, it is not necessary to consider the bonding margin with the color filter substrate, thereby minimizing the overlap region with the pixel electrode as the light transmitting region. As a result, the opening area can be increased in the unit pixel. In other words, the pixel electrode 120 overlaps the pixel electrode 120 with a narrower width than the conventional black matrix formed on the second substrate, thereby increasing the aperture ratio of the liquid crystal display.

FIG. 2B is a cross-sectional view taken along line II ′ of FIG. 2A, and shows that the aperture ratio of the liquid crystal display is increased due to the first light blocking layer 111a of the present invention.

As shown in the figure, a buffer layer 100a is formed on the bottom of the first substrate 100 of the present invention, and a semiconductor layer (not shown) is formed on the buffer layer 100a. A first insulating film 100b is formed on the semiconductor layer, a gate line 101 transmitting a gate signal of the present invention, and a common line transferring a common signal on the first insulating film 100b. A storage first electrode (not shown) formed as part of the common line and a portion of the common line and a first light blocking layer 111a extending along an outer line of the unit pixel are formed. In addition, a second insulating layer 111b is formed on the first substrate 111 including the first light blocking layer 111a, and a data line 103 is formed thereon. In addition, a third insulating layer 100d is formed on the data line 103, and a pixel electrode 120 is formed on the data line 103.

In addition, a second light blocking layer 151 formed of a black matrix is formed on the second substrate 150 facing the first substrate 100, so that light leakage occurs due to abnormal operation of the liquid crystal. Light is shielded in a region where light is not blocked by the light shielding layer 111a.

Meanwhile, as shown in the drawing, the first light blocking layer 111a and the pixel electrode 120 overlap each other with a first width W1 along an edge of the pixel electrode 120, which is a first substrate. The width considering the patterning error between the wirings formed on the first substrate 100, not the bonding margin of the (100) and the second substrate 150, and formed in a relatively narrow width than the overlap width considering the conventional bonding margin do. That is, in the conventional liquid crystal display device, one side of the black matrix and the pixel electrode are generally overlapped with each other by about 5 μm in width. However, in the present invention, the bonding margin of the two substrates does not need to be considered. The electrode 120 may be formed to overlap in the range of 0.1 μm to 3 μm.

As a result, the second light blocking layer 151 of the present invention corresponds to a space between the data line 103 and the first light blocking layer 111a and a space between the gate line 101 and the first light blocking layer 111a. The width of the second light blocking layer 151 can be reduced by at least the second width W2 to increase the opening area in the unit pixel.

Meanwhile, since the common line 111 is formed to extend in the first light blocking layer 111a of the present invention, a common signal is applied. Therefore, a new storage capacitance is formed in an area where the first light blocking layer 111a and the pixel electrode 120 overlap each other.

Therefore, since the storage capacitance is increased over the entire pixel area, it can be formed by reducing the width of the storage capacitor as the light blocking region. That is, the widths of the storage first electrode 105 'and the storage second electrode 111' constituting the storage capacitor and the drain electrode 102b disposed thereon can be reduced, thereby increasing the aperture ratio. Get As a result, the present invention can maximize the aperture ratio of the liquid crystal display while forming a set storage capacitor.

Hereinafter, the manufacturing method of the liquid crystal display device according to the above embodiment will be described in detail with reference to the accompanying drawings.

3A to 3D illustrate a manufacturing process of a liquid crystal display according to the present invention. First, as shown in FIG. 3A, a transparent first substrate 100 is prepared, and then a semiconductor film (not shown) is disposed thereon. After the formation, the island-type polycrystalline silicon semiconductor layer 105 and the storage first electrode 105 ′ formed of an extension line of the semiconductor layer 105 are formed through a first mask process.

The semiconductor film is deposited on the first substrate 100 by plasma enhanced chemical vapor deposition (PECVD) to a predetermined thickness, and then formed through a dehydrogenation process and a crystallization process. At this time, the dehydrogenation process is carried out by removing hydrogen bound in the amorphous silicon layer in a heating furnace and heating at a temperature of about 400 ℃. That is, in the process of forming the amorphous silicon layer, since the bonds of the molecules are formed to be unstable, the hydrogen ions are bonded to the excess bond groups of the molecules, which act as impurities in the process of crystallizing the amorphous silicon. It may cause damage to the silicon layer during the crystallization process and should be removed in advance.

The crystallization process may be a heating method for heating the amorphous silicon layer in a high temperature furnace and a laser crystallization method for instantaneously heating and crystallizing the amorphous silicon layer using excimer laser energy. Since the laser crystallization method can form a large grain size during the crystallization process, there is an advantage that can significantly improve the electrical mobility than the heating method, it is effective when forming a thin film transistor requiring a high speed operation.

Although not shown, a buffer layer (not shown) such as SiOx or SiNx is formed on the first substrate 100 before the semiconductor layer is formed. In this case, as the temperature increases in the heat treatment process of converting the amorphous silicon into polysilicon, the buffer layer prevents impurities contained in the first substrate 100 from entering and contaminating the semiconductor layer.

Next, as shown in FIG. 3B, a silicon oxide film (SiO 2) or a silicon nitride film (SiNx), which is a gate insulating film, on the entire surface of the first substrate 100 including the semiconductor layer 105 and the storage first electrode 105 ′. A first insulating film (not shown) and a first metal film (not shown) such as a double layer of aluminum (Al), molybdenum (Mo), copper (Cu) or aluminum (Al) and molybdenum (Mo) do. Subsequently, the first metal layer is patterned through a second mask process, so that the gate electrodes separated from the gate line 101 and the gate lines 101, that is, the first and second gate electrodes 101a and 101b, and the common signal are provided. A storage second electrode 111 ′ formed as a part of the common line 111 is formed on the common line 111 to be transferred and the storage first electrode 105 ′. In addition, the first light blocking layer 111a is formed to extend from the common line 111. In this case, the storage first electrode 105 'and the storage second electrode 111' form a storage capacitor with a first insulating film (not shown) interposed therebetween, and the first light blocking layer 111a will be described later. An additional storage capacitance is formed together with the pixel electrode 120 to be formed in the process.

Subsequently, the impurity ions are implanted into the semiconductor layer 105 by applying the first and second gate electrodes 101a and 101b as masks, thereby forming the source region 112a and the drain region 112b in the region into which the impurity ions are implanted. Form each. In this case, the source / drain regions 112a and 112b are formed to improve ohmic contact characteristics with electrodes connected to the regions by metallizing a part of the semiconductor layer formed of polycrystalline silicon. Mainly uses Group III impurity ions (eg, boron (B)). This is because the manufacturing process of the liquid crystal display device using polysilicon as the semiconductor layer is simpler than the N-type thin film transistor, and there is no problem of deterioration of the device. However, when manufacturing an N-type thin film transistor, it can be used by implanting Group 5 impurity ions, such as phosphorus (P).

As described above, when the formation of the source / drain regions 112a and 112b is completed through impurity implantation, a second insulating film (not shown) is deposited on the upper portion thereof, and then patterned by a third mask process. First and second contact holes (not shown) are formed to expose portions of the source region 117a and the drain region 117b.

Next, by applying a second metal film such as molybdenum (Mo), molybdenum alloys (MoTa, MoW) on top of it, and patterning it through a fourth mask process, as shown in Figure 3c, the data line 104, Source / drain electrodes 102a and 102b are formed. In this case, the source electrode 102a is connected to the source region 112a through the first contact hole 107a and the drain electrode 119b is connected to the drain region 412b through the second contact hole 107b. do.

Subsequently, a third insulating film (not shown) is applied by coating an organic film such as benzocyclobutene (BCB) or photoacryl (BCB) on the entire surface of the first substrate 100 including the source electrode 102a and the drain electrode 102b. After forming, as shown in FIG. 3D, a third insulating layer (not shown) is patterned through a fifth mask process to form a third contact hole 107c exposing a part of the drain electrode 102b. Subsequently, transparency such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or TO (tin oxide) is formed on the third insulating layer (not shown) on which the third contact hole 107c is formed. The entire layer (not shown) is coated and the transparent conductive layer is patterned through a sixth mask process to form the pixel electrode 120, which is disposed on the drain electrode through the third contact hole 107c. It is to be electrically connected to the electrode (102b). In this case, the pixel electrode 120 is formed such that a predetermined region overlaps the first light blocking layer 111a.

The embodiments described above are illustrated to illustrate the present invention, and do not limit the scope of the present invention.

Accordingly, the scope of the invention should be determined by the appended claims rather than by the foregoing description.

As described above, the present invention forms a first light blocking layer formed of a common line on the array substrate, thereby minimizing the bonding margin with the color filter substrate, thereby reducing the width of the light blocking region by the conventional black matrix, By reducing the width of the phosphorus storage capacitor, the aperture ratio of the liquid crystal display device can be improved.

Claims (10)

A first substrate and a second substrate; And A liquid crystal layer formed between the first substrate and the second substrate, The first substrate, A semiconductor layer formed on the first substrate and forming a storage first electrode; A gate line and a data line formed on an upper layer of the semiconductor layer and arranged vertically and horizontally on the first substrate to define a unit pixel; A source electrode and a drain electrode connected to the semiconductor layer through a contact hole and receiving a signal from the data line; A common line transferring a common signal and formed on the same layer as the gate line to form a storage second electrode; A pixel electrode receiving a signal from the source electrode and the drain electrode to form an electric field together with the common electrode formed on the second substrate to drive the liquid crystal material of the liquid crystal layer; And The common line extends along the outer line of the unit pixel, and includes a first light blocking layer overlapping the pixel electrode with a first width; The drain electrode extends over the storage first electrode and the storage second electrode to form a storage capacitor together with the storage second electrode.  The liquid crystal display device of claim 1, wherein the first width is in a range of about 0.1 μm to about 3 μm. delete  The liquid crystal display of claim 1, wherein a storage capacitance is generated between the first light blocking layer and the pixel electrode.  The liquid crystal display device of claim 1, wherein a second light blocking layer is further formed on the second substrate.  The liquid crystal display device of claim 5, wherein the second light blocking layer is formed in an area corresponding to a space between the data line and the first light blocking layer and a space between the gate line and the first light blocking layer. The liquid crystal display device of claim 1, wherein the semiconductor layer is a polycrystalline silicon semiconductor layer. delete delete The method of claim 1, And at least one gate electrode protruding from the gate line.

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