KR101177486B1 - Semiconductor device and method for forming the same - Google Patents

Abstract

A method of forming a semiconductor device according to the present invention may include forming a gate electrode embedded in a semiconductor substrate including a cell region including an isolation layer and an active region and a cell edge region including only the isolation layer; Forming a sealing insulating film on the semiconductor substrate; forming a barrier film on the sealing insulating film and on the device isolation layer in the cell edge region; forming a storage electrode contact plug between the semiconductor substrate and the barrier film; And forming a metal contact plug penetrating the barrier layer and the sealing insulating layer in the cell edge region and connected to the gate electrode, wherein the semiconductor substrate and the metal contact are connected when the gate metal and the metal contact plug are connected to each other. This prevents the plug from being connected and improves the characteristics of the semiconductor device. It provides an effect that can be improved.

Description

Semiconductor device and method for forming the same

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device including a metal contact plug and a method for forming the same.

Recently, most electronic appliances have semiconductor devices. The semiconductor device includes electronic elements such as transistors, resistors, and capacitors, which are designed to perform partial functions of the electronic products and then integrated on the semiconductor substrate. For example, electronic products such as a computer or a digital camera include semiconductor devices such as a memory chip for storing information and a processing chip for controlling information, and the memory chip and the processing chip are semiconductors. And the electronic components integrated on a substrate.

On the other hand, semiconductor devices need to be increasingly integrated to meet consumer demands for superior performance and low cost. As the degree of integration of semiconductor devices increases, the number of design rules decreases and the pattern of semiconductor devices becomes finer. As miniaturization and high integration of a semiconductor device progresses, the overall chip area increases in proportion to an increase in memory capacity, but the area of a cell area where a semiconductor device pattern is formed is actually decreasing. Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell region, so that a fine pattern with a reduced critical dimension of the pattern must be formed.

Among the types of semiconductor devices, a DRAM includes a plurality of unit cells including capacitors and transistors. Among them, a capacitor is used for temporarily storing data, and a transistor is used for transferring data between a bit line and a capacitor corresponding to a control signal (word line) by using the property of a semiconductor whose electrical conductivity changes according to an environment. A transistor consists of three regions: a gate, a source, and a drain. A charge is transferred between the source and the drain in accordance with a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region, which uses the nature of the semiconductor.

When a conventional transistor is formed on a semiconductor substrate, a gate is formed on a semiconductor substrate and doping is performed on both sides of the gate to form a source and a drain. In this case, the region between the source and the drain under the gate becomes the channel region of the transistor. A transistor having such a horizontal channel region occupies a semiconductor substrate of a certain area. In the case of a complicated semiconductor memory device, it is difficult to reduce the total area due to a plurality of transistors included in the semiconductor memory device.

By reducing the total area of the semiconductor memory device, the number of semiconductor memory devices that can be produced per wafer can be increased and productivity is improved. Various methods have been proposed to reduce the total area of the semiconductor memory device. In place of a conventional planar gate in which one of them has a horizontal channel region, a recess is formed in the substrate and a gate is formed in the recess, thereby forming a recess in which the channel region is formed along the curved surface of the recess A buried gate is formed by embedding the entire gate in the recess in addition to the recessed gate.

The buried gate is connected to the metal contact plug at the edge of the cell mat. As the metal contact plug and the buried gate are connected, the height of the metal contact plug increases and the depth of the metal contact hole also increases.

FIG. 1B is a plan view of a semiconductor device according to the prior art, and FIG. 1B is a cross-sectional view of a semiconductor device taken along the line AA ′ of FIG. 1.

As shown in FIG. 1B, the semiconductor device according to the related art is perpendicular to the gate electrode 14 and the gate electrode 14 embedded in the semiconductor substrate 10 including the device isolation film 12. The metal contact plug 20 includes a bit line 17 arranged to be connected to the gate electrode 14 provided in the cell edge region. In more detail, it demonstrates with reference to FIG. 1 (ii).

As shown in FIG. 1 (ii), the gate electrode 14 embedded in the bottom of the device isolation film 12 of the semiconductor substrate 10 and the gate electrode 14 are disposed on the gate electrode 14 and embedded in the device isolation film 12. The sealing insulating film 16 and the interlayer insulating film 18 provided on the sealing insulating film 16 are formed. Subsequently, a contact hole is formed by etching the interlayer insulating film 18 and the sealing insulating film 16 so that the gate electrode 14 is exposed, and then a metal contact for supplying power to the gate electrode 14 by embedding a conductive layer in the contact hole. The plug 20 is formed.

However, there is no big problem in the case of precisely connecting the gate electrode 14 like the metal contact plug 20c, but the size is increased as in the metal contact plug 20a or the metal contact plug as in the metal contact plug 20b. In the case of misalignment, if the gate electrode 14 is not connected correctly but is connected to the semiconductor substrate 10, a punch may occur to deteriorate the characteristics of the semiconductor device.

The present invention is to solve the problem that when the gate electrode and the metal contact plug is misaligned or the contact plug increases in size, the gate electrode is not connected to the gate electrode and is connected to the semiconductor substrate to deteriorate the characteristics of the semiconductor device.

A semiconductor device of the present invention includes a gate electrode embedded in a semiconductor substrate including a cell region including an isolation layer and an active region, and a cell edge region including only the isolation layer, and disposed on the gate electrode and in the semiconductor substrate. A buried sealing insulating film, a barrier film provided on the sealing insulating film and an upper portion of the cell isolation region in the cell edge region, a storage electrode contact plug provided between the semiconductor substrate and the barrier film, the barrier film and the sealing And a metal contact plug penetrating the insulating film and connected to the gate electrode.

And a bit line arranged perpendicular to the gate electrode and connected to a central portion of the active region.

The barrier layer extends in a direction parallel to the gate electrode of the cell region and is connected to a line type barrier layer provided on the sealing insulating layer and to one end of the line type barrier layer in the cell edge region. And a pad type barrier film extending in a direction parallel to the bit line and provided on the device isolation film.

The barrier layer and the sealing insulating layer may be formed of a material having the same etching selectivity.

The barrier layer and the sealing insulating layer may have an etching selectivity greater than that of the storage electrode contact plug.

In addition, the stack structure of the metal contact plug, the sealing insulating film and the barrier film may be alternately provided.

A method of forming a semiconductor device according to the present invention may include forming a gate electrode embedded in a semiconductor substrate including a cell region including an isolation layer and an active region and a cell edge region including only the isolation layer; Forming a sealing insulating layer on the upper surface of the semiconductor substrate; forming a barrier layer on the sealing insulating layer and on the device isolation layer in the cell edge region; forming a storage electrode contact plug between the semiconductor substrate and the barrier layer; And forming a metal contact plug penetrating the barrier layer and the sealing insulating layer in the cell edge region and connected to the gate electrode.

The forming of the gate electrode may include forming a trench by etching the device isolation layer and the active region, and forming a gate conductive material on the bottom of the trench.

In the forming of the sealing insulating layer, the trench may be embedded.

And forming a bit line connected to a central portion of the active region after the forming of the sealing insulating layer.

And forming an interlayer insulating film on the semiconductor substrate after the forming of the bit line, and performing a planarization etching process on the interlayer insulating film to expose the bit line.

In the forming of the barrier layer, the barrier layer may be formed to extend in a direction parallel to the gate electrode of the cell region. And a pad type barrier layer formed on the device isolation layer and connected to an end thereof and extending in a direction parallel to the bit line.

The forming of the line type barrier layer may include forming a line type barrier predetermined region by etching the interlayer insulating layer so that the sealing insulating layer of the cell region and the cell edge region is exposed. And forming an insulating film in a predetermined region.

The forming of the pad type barrier layer may include connecting the interlayer insulating layer to one end of the predetermined line type barrier region in the cell edge region and extending in a direction parallel to the bit line and exposing the device isolation layer. Etching to form a pad type barrier predetermined region, and forming an insulating layer on the pad type barrier predetermined region.

The forming of the storage electrode contact plug may include forming a storage electrode contact hole by etching the interlayer insulating layer formed on both sides of the barrier layer, and forming a conductive material in the storage electrode contact hole. It features.

The forming of the metal contact plug may include forming a metal contact hole by etching the line type barrier layer and the sealing insulating layer to expose the gate metal, and filling a conductive layer in the metal contact hole. Characterized in that it comprises a.

The forming of the metal contact hole may include etching the stacked structure of one sealing insulating layer and the line type barrier layer among the stacked structures of the sealing insulating layer and the line type barrier layer that are adjacent to each other. .

The etching of the stacked structure of the line type barrier layer and the sealing insulating layer may be performed using an etching selectivity with the storage electrode contact plug.

The present invention provides an effect of improving the characteristics of the semiconductor device by preventing the problem that the semiconductor substrate and the metal contact plug is connected when the gate metal and the metal contact plug are connected.

FIG. 1B is a plan view showing a semiconductor device according to the prior art, and FIG. 1 (ii) is a cross-sectional view showing a semiconductor device taken along the line A-A 'in FIG.
FIG. 2B is a plan view showing a semiconductor device according to the present invention, and FIG. 2 (ii) is a cross-sectional view showing a semiconductor device taken along the line A-A 'in FIG.
3A to 3H illustrate a method of forming a semiconductor device according to the present invention.
4 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings in accordance with the present invention will be described in detail.

FIG. 2B is a plan view showing a semiconductor device according to the present invention, and FIG. 2 (ii) is a cross-sectional view showing a semiconductor device taken along the line A-A 'of FIG.

As shown in FIG. 2 (i), the semiconductor device according to the present invention includes an active region 104 defined by an isolation layer 102 in a cell region, and includes a cell edge region. The semiconductor substrate 100 including only the isolation layer 102, the barrier layer 130 provided on the isolation layer 102 and the active region 104, and the bit line 120 perpendicular to the barrier layer 130. ) And a storage electrode contact plug 134 filling the barrier layer 130 and the bit line 120. Here, the barrier layer 130 is connected to one end of the line type barrier layer 130a and the line type barrier layer 130a formed extending from the cell region, and is perpendicular to the bit line 120. The pad type barrier film 130b is provided. The line type barrier layer 130a is preferably formed to extend in the cell region and the cell edge region, and the pad type barrier layer 130b is preferably formed in the cell edge region. Do. More specifically, it will be described with reference to Fig. 2 (ii) in Fig. 2 (ii) cut to A-A '.

As shown in FIG. 2 (ii), the gate electrode 106 embedded in the device isolation film 102 in the semiconductor substrate 100 and the gate electrode 106 are provided on the gate electrode 106 and embedded in the device isolation film 102. The sealing insulating film 108, the line type barrier film 130a extending over the sealing insulating film 108, and the line type barrier film 130a are provided on both sides of the device isolation film 102. The storage electrode contact plug 134, the interlayer insulating film 136 provided on the storage electrode contact plug 134, and the line type barrier film 130a, the interlayer insulating film 136, and the line type barrier film 130a. And a metal contact plug 140 passing through the sealing insulating film 108 and connected to the gate electrode 106.

Although the pad type barrier film 130b is not shown in FIG. 2 (ii), the pad type barrier film 130b is connected to one end of the line type barrier film 130a at the cell edge. And extend in a direction parallel to the bit line 120 and provided on the device isolation layer 102.

Here, the barrier layer 130 and the sealing insulating layer 108 preferably include a material having the same etching selectivity. In addition, the metal contact plugs 140 are preferably arranged alternately with the stacked structure of the sealing insulating film 108 and the line type barrier film 130a.

A method of forming a semiconductor device according to the present invention having the above-described configuration is as follows. 3A to 3H illustrate a method of forming a semiconductor device according to the present invention. (A) of FIG. 3A-FIG. 3E here is a top view, (ii) is sectional drawing which cut BB 'of (i). (F) of FIG. 3F shows a top view, (ii) is sectional drawing which cut BB 'of (iii), and (b) is sectional drawing which cut A-A' of the top view (iii). 3G and 3H show a plan view, and (ii) shows a cross-sectional view taken along the line A-A 'of (i).

As shown in FIG. 3A, a semiconductor substrate including an active region 104 defined by an isolation layer 102 in a cell region and an isolation layer 102 in a cell edge ( After forming the trench in 100, the gate conductive material is embedded in the bottom of the trench to form the gate electrode 106. A sealing insulating layer 108 is formed on the gate electrode 106, and a capping insulating layer 110 is formed on the semiconductor substrate 100 including the sealing insulating layer 108. Subsequently, an interlayer insulating layer 112 is formed on the capping insulating layer 110, and a contact hole is formed by etching the interlayer insulating layer 112 and the capping insulating layer 110 so that the center portion of the active region 104 is exposed. The spacer 113 is formed in the groove. The conductive material is formed to fill the contact hole to form the bit line contact plug 114, and then the bit line electrode 116 and the hard mask layer 118 are formed on the bit line contact plug 114 to form the bit line 120. ). The bit line 120 is preferably arranged perpendicular to the gate electrode 106. Subsequently, a spacer 122 is formed on the sidewall of the bit line 120.

As shown in FIG. 3B, after forming the interlayer insulating layer 124 on the interlayer insulating layer 112, the planarization etching process is performed on the interlayer insulating layer 124 to expose the hard mask layer 118. Here, the interlayer insulating film 124 preferably includes an oxide film.

As shown in FIG. 3C, after the photoresist pattern 126 is formed on the interlayer insulating layer 124 and the bit line 120, the sealing insulation layer formed on the gate electrode 106 using the photoresist pattern 126 as an etch mask ( The barrier insulating region 128 is formed by etching the interlayer insulating layer 124 to expose the 108 and the device isolation layer 102. Here, the device isolation layer 102 means the device isolation layer 102 provided at the cell edge region. Therefore, since the barrier predetermined region 128 is formed to expose the upper portion of the sealing insulating layer 108 formed on the gate electrode 106, the barrier predetermined region 128 extends to overlap the gate electrode 106 in the cell region, and the sealing insulating layer 108 is formed. ) And includes a line-type barrier predetermined region 128a for exposing), and is connected to one end of the line-type barrier predetermined region 128a at a cell edge and extends in a direction parallel to the bit line 120. And a pad type barrier predetermined region 128b exposing the device isolation layer 102.

As shown in FIG. 3D, an insulating film is embedded in the barrier predetermined regions 128a and 128b to form the barrier film 130. For convenience, the insulating film embedded in the barrier predetermined region 128a is referred to as a line type barrier film 130a, and the insulating film embedded in the barrier predetermined region 128b is referred to as a pad type barrier film 130b.

The insulating layer 130 may be formed of a material having the same etching selectivity as that of the sealing insulating layer 108, and may preferably include a material having an etching selectivity different from that of the interlayer insulating layer 124. Specifically, the barrier film 130 preferably includes a nitride film.

As shown in FIG. 3E, the interlayer insulating layer 124 is etched to expose both ends of the active region 104 to form the storage electrode contact plug region 132. The storage electrode contact plug region 132 may be formed to expose not only both ends of the active region 104 but also a portion of the device isolation layer 102. In addition, the storage electrode contact plug region 132 is formed in a portion where the interlayer insulating layer 124 is etched in the cell edge region. The interlayer insulating layer 124 may be etched using a different etching selectivity from the barrier layer 130.

As shown in FIG. 3F, a conductive layer is embedded in the storage electrode contact plug region 132 to form the storage electrode contact plug 134. Here, the storage electrode contact plug 134 may be formed at both ends of the active region 104 in the cell region as shown in (ii) of FIG. 3F, and as shown in (i) of FIG. 3F. Likewise, the cell edge may be formed on the device isolation layer 102. In the cell edge region, after forming the storage electrode contact plug 134, the interlayer insulating layer 136 is preferably formed on the storage electrode contact plug 134 and the line type barrier layer 130a. In this case, the storage electrode contact plug 134 may be formed of a material having a smaller etching selectivity than that of the barrier layer 130 and the sealing insulating layer 108.

Since the process after the storage electrode contact plug 134 is formed is centered on the cell edge area, the cross-sectional view of the cell area is omitted and the cross-sectional view taken along the line A-A 'of the cell edge area is omitted. Explain.

As shown in FIG. 3G, the interlayer insulating layer 136, the line type barrier layer 130a, and the sealing insulating layer 108 are etched to expose the gate electrode 106 to form a metal contact hole 138. Here, the metal contact hole 138 is a sealing insulating film 108 and a line type barrier film of one of the stacked structures of the sealing insulating film 108 and the line type barrier film 130a adjacent to each other in Fig. 3G (ii). It is preferable that the laminate structure 130a is formed by etching. The stack structure of the line type barrier layer 130a and the sealing insulating layer 108 may be etched using an etching selectivity with the storage electrode contact plug 134. Since the line type barrier layer 130a and the sealing insulating layer 108 have a larger etching selectivity than the storage electrode contact plug 134, even if the metal contact hole 138 is misaligned or enlarged, the line type barrier layer 130a and Since only the sealing insulating layer 108 is etched, it is possible to prevent the metal contact hole 138 from extending to the semiconductor substrate 100. In addition, since the line-type barrier layer 130a and the sealing insulating layer 108 are materials having the same etching selectivity, they may be easily etched when the gate metal 106 is exposed to be etched, thereby etching the semiconductor substrate 100. Can be prevented.

As shown in FIG. 3H, a metal contact plug 140 is formed by filling a conductive layer in the metal contact hole 138. When the size of the metal contact plug 140 according to the present invention is large, even when misaligned, the metal contact plug 140 is formed to be connected only to the gate electrode 106 without being connected to the semiconductor substrate 100.

As shown in FIG. 4, even though the size of the metal contact hole 138 is greatly increased so that the interlayer insulating film 136 is etched to a large width, the metal contact hole 138 is a line type barrier film 130a and a sealing insulating film ( 108 is formed to be smaller than the width of the metal contact hole formed in the interlayer insulating film 136. Therefore, it is possible to fundamentally prevent the metal contact hole 138 from extending to the semiconductor substrate 100. Similarly, when the metal contact hole 138 is misaligned, the metal contact hole 138 is a line type of a portion overlapping with the gate electrode 106 even if the interlayer insulating film 136 on the upper extension line of the gate electrode 106 is not etched. Since the barrier layer 130a and the sealing insulating layer 108 are formed by etching, it may be prevented from extending to the semiconductor substrate 100. Accordingly, the metal contact plug 140b formed by misaligning the metal contact plug 140a and the metal contact hole 138 when the size of the metal contact hole 138 is greatly increased is the metal contact plug formed according to the present invention. It may be easily connected to the gate electrode 106, such as 140c.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

Claims (18)

A gate electrode embedded in a semiconductor substrate including a cell region including an isolation layer and an active region and a cell edge region including only the isolation layer;
A sealing insulating layer disposed on the gate electrode and buried in the semiconductor substrate;
A barrier layer provided on the sealing insulating layer and on the device isolation layer in the cell edge region;
A storage electrode contact plug provided between the semiconductor substrate and the barrier layer; And
And a metal contact plug penetrating the barrier layer and the sealing insulating layer and connected to the gate electrode. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1,
And a bit line arranged perpendicular to the gate electrode and connected to a central portion of the active region. Claim 3 has been abandoned due to the setting registration fee. The method according to claim 1,
The barrier film is
A line type barrier layer arranged in a direction parallel to the gate electrode of the cell region and disposed above the sealing insulating layer; And
And a pad type barrier layer connected to one end of the line type barrier layer in the cell edge region and extending in a direction parallel to the bit line and disposed on the device isolation layer. Claim 4 has been abandoned due to the setting registration fee. The method according to claim 1,
And the barrier layer and the sealing insulating layer include materials having the same etching selectivity. Claim 5 was abandoned upon payment of a set-up fee. The method according to claim 1,
And the barrier layer and the sealing insulating layer have an etching selectivity greater than that of the storage electrode contact plug. Claim 6 has been abandoned due to the setting registration fee. The method according to claim 1,
And the stack structure of the metal contact plug, the sealing insulating film, and the barrier film are alternately provided. Forming a gate electrode embedded in a semiconductor substrate including a cell region in which an isolation layer and an active region are formed, and a cell edge region in which only the isolation layer is formed;
Forming a sealing insulating film on the gate electrode;
Forming a barrier layer on the sealing insulating layer and on the device isolation layer in the cell edge region;
Forming a storage electrode contact plug between the semiconductor substrate and the barrier layer; And
And forming a metal contact plug penetrating the barrier layer and the sealing insulating layer in the cell edge region and connected to the gate electrode. Claim 8 was abandoned when the registration fee was paid. The method of claim 7,
Forming the gate electrode
Etching the device isolation layer and the active region to form a trench; And
And forming a gate conductive material on the bottom of the trench. Claim 9 has been abandoned due to the setting registration fee. The method according to claim 8,
The forming of the sealing insulating film may include forming the trench to fill the trench. Claim 10 has been abandoned due to the setting registration fee. The method of claim 7,
After forming the sealing insulating film
And forming a bit line connected to the central portion of the active region. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10,
After forming the bit line
Forming an interlayer insulating film on the semiconductor substrate; And
And performing a planarization etch process on the interlayer insulating layer to expose the bit line. Claim 12 is abandoned in setting registration fee. The method of claim 11,
Forming the barrier film
An array extending in a direction parallel to the gate electrode of the cell region, and forming a line-type barrier layer on the sealing insulation layer, connected to one end of the line-type barrier layer in the cell edge region, and parallel to the bit line And forming a pad type barrier film over the device isolation film and extending in one direction. Claim 13 was abandoned upon payment of a registration fee. The method of claim 12,
Forming the line type barrier film
Etching the interlayer insulating layer to expose the sealing insulating layer of the cell region and the cell edge region to form a line type barrier predetermined region; And
And forming an insulating film in the barrier predetermined region of the line type. Claim 14 has been abandoned due to the setting registration fee. The method of claim 12,
Forming the pad type barrier film
Forming a pad type barrier predetermined region by etching the interlayer insulating layer to be connected to one end of the line type barrier predetermined region in the cell edge region and extending in a direction parallel to the bit line and exposing the device isolation layer; ; And
And forming an insulating film on the pad type barrier predetermined region. Claim 15 is abandoned in the setting registration fee payment. The method of claim 12,
Forming the storage electrode contact plug
Etching the interlayer dielectric layers formed on both sides of the barrier layer to form a storage electrode contact hole; And
And forming a conductive material in the storage electrode contact hole. Claim 16 has been abandoned due to the setting registration fee. The method of claim 12,
Forming the metal contact plug
Forming a metal contact hole by etching the line type barrier layer and the sealing insulating layer to expose the gate metal; And
Forming a conductive layer in the metal contact hole. Claim 17 has been abandoned due to the setting registration fee. 18. The method of claim 16,
Forming the metal contact hole
And etching one of a sealing structure of one of the stacked structures of the sealing insulating film and the line-type barrier film and a stacked structure of the line-type barrier film. Claim 18 has been abandoned due to the setting registration fee. 18. The method of claim 17,
And etching the stacked structure of the line type barrier layer and the sealing insulating layer using an etch selectivity with respect to the storage electrode contact plug.

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