KR101157248B1 - Mass production system checking structure of liquid crystal display device - Google Patents

Abstract

The present invention relates to an MPS inspection wiring structure of a liquid crystal display device. The MPS inspection wiring structure of a liquid crystal display device according to the present invention includes a gate wiring and a data wiring composed of a plurality of odd and even wirings formed on a substrate; A unit liquid crystal panel including a thin film transistor formed at a point where a plurality of odd-numbered and even-numbered gate lines and data lines cross each other, and a pixel display part formed in a region where the gate lines and data lines are formed; An odd gate wiring for MPS inspection connected to the odd gate wiring and disposed in the unit liquid crystal panel; An even gate wiring for MPS inspection connected to the even gate wiring and disposed in the unit liquid crystal panel; And a common wiring disposed inside the unit liquid crystal panel.

MPS inspection gate wiring, MPS inspection data wiring, unit liquid crystal panel, common wiring

Description

MPS PRODUCTION CHECKING STRUCTURE OF LIQUID CRYSTAL DISPLAY DEVICE}

1 is a schematic diagram showing a thin film transistor array substrate for explaining the MPS inspection wiring structure according to the prior art.

Figure 2 is a schematic diagram showing an enlarged structure of the MPS inspection wiring per unit panel according to the prior art.

3 is a schematic diagram illustrating an enlarged Vcom line arrangement region of FIG. 2, that is, "A" in the MPS inspection wiring structure per unit panel according to the prior art; FIG.

4 is a plan view illustrating an array substrate on which a plurality of liquid crystal display panels according to the prior art are arranged;

Figure 5 is a schematic diagram showing a thin film transistor array substrate for explaining the MPS wiring structure according to the present invention.

Figure 6 is a schematic diagram showing an enlarged MPS inspection wiring structure per unit panel according to the present invention.

FIG. 7 is a schematic diagram illustrating an enlarged Vcom line arrangement region of FIG. 6, that is, “B” in FIG. 6, in the MPS inspection wiring structure per unit panel according to the present disclosure; FIG.

8 is a plan view schematically illustrating the application of the MPS inspection wiring structure per unit panel to an array substrate on which a plurality of liquid crystal display panels according to the present invention are arranged;

-Explanation of symbols for the main parts of the drawings-

110: array substrate 120: unit liquid crystal panel

125: odd gate pad for MPS inspection 135: odd gate wiring for MPS inspection 140: even gate pad for MPS inspection 145: even gate wiring for MPS inspection 150: common wiring pad

155: Common wiring (Vcom) 160: Odd data pad for MPS inspection 165: Odd data wiring for MPS inspection 170: Even data pad for MPS inspection 175: Even data wiring for MPS inspection W: Width between unit liquid crystal display panel

The present invention relates to a mass production system (MPS) inspection wiring structure of a liquid crystal display device. More particularly, the MPS wiring is disposed inside the liquid crystal display panel instead of the outer portion of the liquid crystal display panel so that there is no problem during the inspection process. An MPS inspection wiring structure of a liquid crystal display device.

In general, a liquid crystal display device is a display device in which data signals are individually supplied to liquid crystal cells arranged in a matrix form, and an image corresponding to the data signal is displayed by adjusting light transmittance of the liquid crystal cells.

The liquid crystal display includes a liquid crystal panel in which liquid crystal cells forming pixel units are arranged in an active form, and a driver integrated circuit (IC) for driving the liquid crystal cells.

Here, the liquid crystal panel is arranged so that the common electrode is formed on one side of each inner side of the upper and lower substrates facing each other, and the pixel electrode is formed on the other side of the liquid crystal panel to face each other, and is injected at intervals between the upper and lower substrates. An electric field is applied to the liquid crystal layer through the common electrode and the pixel electrode. In this case, the pixel electrode is formed for each liquid crystal cell on the lower substrate, and the common electrode is integrally formed on the entire surface of the upper substrate.

In addition, a plurality of data wires for transmitting the data signal supplied from the data driver integrated circuit to the liquid crystal cells and a scan signal supplied from the gate driver integrated circuit are provided on the lower substrate of the liquid crystal panel. A plurality of gate lines are formed in directions perpendicular to each other, and an input pad to which data signals and scan signals supplied from the data driver IC and the gate driver IC are applied to one end of the data lines and the gate lines, respectively. The liquid crystal cells are defined at each intersection of the data lines and the gator lines.

In addition, the gate driver integrated circuit sequentially supplies the investigation signals to the plurality of gate wirings so that the liquid crystal cells arranged in a matrix form are sequentially selected one by one, and the data driver integrated circuits are arranged in the liquid crystal cells of the selected one wiring. From the data signal is supplied.

In each liquid crystal cell, a thin film transistor used as a switching element is formed, and in a liquid crystal cell in which a scan signal is supplied to the gate electrode of the thin film transistor through the gate wiring, a conductive channel is formed between the source and drain electrodes of the thin film transistor. In this case, as the data signal supplied to the source electrode of the thin film transistor through the data wiring is supplied to the pixel electrode via the drain electrode of the thin film transistor, the light transmittance of the corresponding liquid crystal cell is controlled.

As described above, the upper and lower substrates constituting the liquid crystal panel are formed of a plurality of unit panels on a large glass mother substrate, usually formed four or six at the same time and then cut into each unit panel to improve the yield Promote.

In manufacturing a general liquid crystal display panel, when the thin film transistor array is formed on the lower substrate, the thin film transistor array formed on the lower substrate is inspected before bonding to the upper substrate on which the color filter is formed.

In the inspection step of the thin film transistor array, a pattern inspection step, a review step, an MPS inspection step, and a repair step are performed in this order.

First, in the pattern inspection step, the xenon-lamp is irradiated onto the TFT array to distinguish the normal part from the defective part by the difference in brightness of the light reflected by the pixel of the TFT. At this time, the defective part sets the coordinates of the defect and delivers information about the defect coordinate to the next step.

After that, the pattern inspection step moves to a review station, where the type of defect or the degree of the defect is a possibility of repair based on the coordinates of the defect detected by the pattern inspector. The operator judges directly, and transmitted light is installed on the back of the review station to check even defects generated in the TFT array.

Subsequently, as a Mass Production System (MPS) inspection step, a voltage is applied to each panel through an MPS inspector to identify an array that is actually defective when the thin film transistor is driven, thereby checking the electrical failure of the panel.

The MPS inspection wiring structure of the liquid crystal display device according to the related art applied to check the electrical failure of the panel is as follows.

1 is a schematic diagram showing a thin film transistor array substrate for explaining the MPS inspection wiring structure according to the prior art.

Figure 2 is a schematic diagram showing an enlarged structure of the MPS inspection wiring per unit panel according to the prior art.

3 is a schematic diagram illustrating an enlarged Vcom line arrangement region of FIG. 2, that is, "A" in the MPS inspection wiring structure per unit panel according to the related art.

4 is a plan view illustrating an array substrate on which a plurality of liquid crystal display panels according to the prior art are arranged.

1 and 2, in order to proceed with the MPS inspection of the liquid crystal display according to the prior art, four or six unit liquid crystal panels 20 are applied on the glass substrate 10 to be applied according to the model of the liquid crystal panel. Although not shown in the drawings, a plurality of gate wirings (not shown) and data wirings (not shown) are formed in a matrix form in each unit liquid crystal panel 20, and the gate wirings (not shown) Thin film transistors that function as switching elements are formed near the intersections of the data lines (not shown).

Although not shown in the drawings, a gate pad (not shown) is formed at one end of the gate wiring (not shown) to apply a signal to the gate wiring (not shown).

Data pads (not shown) are formed at one end of the data line (not shown), and common electrode pads (not shown) are formed at one end of the common electrode line (not shown). In this case, as shown in FIGS. 2 and 3, the common electrode line (not shown) is disposed at an outer portion of the liquid crystal display 25 defined in the unit liquid crystal panel 20.

Further, for the MPS inspection of the unit liquid crystal panel, each gate pad (not shown) is divided into an odd wiring and an even wiring, and the gate wiring for MPS inspection (hereinafter referred to as GO) 35 connected to the odd wiring is even. MPS inspection gate wiring (hereinafter referred to as GE) 45 for connecting the wirings is provided, and each data pad (not shown) is also divided into odd wiring and even wiring to connect the odd wiring. In the following, DO 65 is provided, and an MPS inspection data wiring 75 (hereinafter referred to as DE) 75 is connected to even-numbered wirings, and a common wiring 55 for MPS inspection is provided on the common electrode pad (not shown). ) Is provided. The MPS inspection gate wirings 35 and 45, the common wiring 55, and the MPS inspection data wirings 65 and 75 are provided in the outer region of the liquid crystal panel 20.

In addition, the MPS inspection gate wiring (hereinafter referred to as GO) 35 to connect the odd wirings and the MPS inspection gate wiring (hereinafter referred to as GE) 45 to connect the even wirings are odd gate pads for the MPS inspection, respectively. An MPS inspection data line connected to the 30 and the even gate pads 40 and connected to the odd line; DO) 65 and the MPS inspection data wiring (hereinafter referred to as DE) 75 connecting even wirings are connected to the odd data pad 60 and the even data pad 70 for MPS inspection, respectively. The common wiring 55 is connected to the common wiring pad 50 for the MPS inspection.

In this way, power is selectively applied to the MPS inspection gate lines GO and GE and the data lines DO and DE to determine whether the gate line and the data line of the thin film transistor array are disconnected or short-circuited.

As described above, according to the MPS inspection wiring structure of the liquid crystal display according to the prior art, if the MPS inspection wiring problem and the resistance of the odd wiring and even wiring are wrong, the electrical signal does not flow the same, and thus the load and the defect in the inspection process As the detection output drops considerably, the defective product is judged to be good.

In addition, the existing MPS inspection wiring design method occupies a large glass area because the MPS inspection wiring is designed in glass (approximately 5%), and the wiring design becomes difficult according to the glass arrangement, and has a complicated shape. Therefore, there is a problem that it is difficult to match the resistance of the even wiring (Even), odd wiring (Odd). In particular, in the case of a small model, the unit liquid crystal panel arrangement in the glass has almost no width (W) between the panel and the panel as shown in FIG. do.

Accordingly, the present invention has been made in order to solve all the problems according to the prior art, and the MPS inspection wiring is arranged inside the unit liquid crystal panel instead of outside the unit liquid crystal panel to perform disconnection and short circuit inspection of the wiring using the MPS inspection wiring. It is an object of the present invention to provide an MPS inspection wiring structure of a liquid crystal display device so that no problem occurs.

The MPS inspection wiring structure of the liquid crystal display according to the present invention for achieving the above object is a gate wiring and data wiring consisting of a plurality of odd and even wiring formed on a substrate, the plurality of odd and even gate wiring and data A unit liquid crystal panel including a thin film transistor formed at a point where wirings cross each other, and a pixel display unit formed in an area formed between the gate line and the data line; An odd gate wiring for MPS inspection connected to the odd gate wiring and disposed in the unit liquid crystal panel; An even gate wiring for MPS inspection connected to the even gate wiring and disposed in the unit liquid crystal panel; And a common wiring disposed inside the unit liquid crystal panel.

Hereinafter, the MPS inspection wiring structure of the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a schematic diagram illustrating a thin film transistor array substrate for explaining the MPS inspection wiring structure according to the present invention.

6 is an enlarged schematic view of an MPS inspection wiring structure per unit panel according to the present invention.

7 is a schematic diagram illustrating an enlarged Vcom line arrangement region of FIG. 6, that is, "B" of FIG. 6 in the MPS inspection wiring structure per unit panel according to the present invention.

8 is a plan view schematically illustrating the application of the MPS inspection wiring structure per unit panel to an array substrate on which a plurality of liquid crystal display panels according to the present invention are arranged.

5 and 6, in the MPS inspection of the liquid crystal display according to the present invention, four or six thin film transistor arrays are formed on a glass substrate 110 to be applied according to a model of a unit liquid crystal panel. The liquid crystal panel 120 is formed, and each of the unit liquid crystal panels 120 includes a plurality of gate wirings (not shown) and data wirings (not shown) in a matrix form, although not shown in the drawing. A thin film transistor (not shown) that functions as a switching element is formed near the intersection of the wiring (not shown) and the data wiring (not shown).

Although not shown in the drawing, a gate pad (not shown) is formed at one end of the gate wiring (not shown) to apply a signal to the gate wiring (not shown), and the data wiring (not shown). A data pad (not shown) is formed at one end of the common electrode, and a common electrode pad (not shown) is formed at one end of the common electrode (not shown). In this case, as shown in FIGS. 5 and 6, the common electrode (not shown) is disposed at an outer portion of the liquid crystal display 125 defined in the unit liquid crystal panel 120.

In addition, for the MPS inspection of the unit liquid crystal panel 120, each gate pad (not shown) is divided into an odd wiring and an even wiring to connect to an odd wiring MPS inspection gate wiring (hereinafter referred to as GO) 135 ) MPS inspection gate wiring (hereinafter referred to as GE) 145 that is connected to each other and even wiring is provided, and each data pad (not shown) is divided into odd wiring and even wiring to connect odd wiring. Less than data wiring; DO) 165 and an MPS inspection data wiring (hereinafter referred to as DE) 175 for connecting even-numbered wirings are provided, and a common wiring 155 for MPS inspection is provided on the common electrode pad (not shown). It is prepared. In this case, the common wiring 155 is formed to have a smaller width than the conventional case, so that the odd and even gate wirings 135 and 145 for the MPS inspection to be described later are disposed in the remaining region.

Here, the MPS inspection gate wirings 135 and 145 are provided in the unit liquid crystal panel 120. In particular, the MPS inspection gate wirings 135 and 145 are disposed at an outer portion of the liquid crystal display 125 inside the unit liquid crystal panel 120. In particular, as shown in FIG. 7, the MPS inspection gate wirings 135 and 145 are spaced apart from the common wiring 155 by a predetermined distance, and they are electrically insulated from each other.

In addition, the MPS inspection gate wiring (hereinafter referred to as GO) 135 connected to the odd wirings and the MPS inspection gate wiring (hereinafter referred to as GE) 145 connected to the even wirings are each odd gate pads for the MPS inspection. Connected to the 130 and the even gate pads 140, and less than or equal to the MPS inspection data wiring line connecting the odd wiring lines; DO) 165 and MPS inspection data wiring (hereinafter referred to as DE) 175 connecting even wirings are connected to odd data pads 160 and even data pads 170 for MPS inspection, respectively. The common wiring 155 is connected to the common wiring pad 150 for the MPS inspection. In this case, the odd and even gate pads 130 and 140, the common wiring pad 150, and the odd data pads 160 and 170 are formed on the lower substrate 110.

In this way, the MPS inspection gate wirings 135 and 145 and the data wirings 165.

By selectively applying power to 175, it is determined whether the gate wiring and the data wiring are disconnected or short-circuited in the thin film transistor array.

The thin film transistor may include a gate electrode drawn from the gate wiring (not shown), a source electrode drawn from the data wiring (not shown), an active layer, and a drain electrode, and the drain electrode may be a gate wiring (not shown). And a pixel electrode formed in a region enclosed by the C) and data lines (not shown).

As described above, the MPS inspection wirings (GO, GE, DO, DE) are formed separately to inspect the defects such as disconnection and short circuits of the wirings formed on the lower substrate on which the thin film transistor array is formed. When complete, it will be cut and removed.

Meanwhile, the MPS inspection gate lines GO and GE and the MPS inspection data lines DO and DE cross each other with a gate insulating film (not shown) and an active layer (not shown) formed on the entire lower substrate. The gate wirings GO and GE for the MPS inspection are formed in a process of forming a gate wiring (not shown) and a gate electrode (not shown), and include chromium (Cr), molybdenum (Mo), tantalum (Ta), or antimony ( Sb) and the like, the MPS inspection data wiring (DO, DE) is formed in the data wiring and data electrode forming process is made of a metal such as chromium (Cr) or molybdenum (Mo).

In addition, conventionally, only the common wiring (Vcom) was formed in the area between the pixel display portion defined inside the unit display panel and the edge portion of the unit display panel. In the present invention, odd and even gate wiring for MPS inspection is used for gate wiring inspection. Is disposed in the area between the pixel display portion defined inside the unit display panel and the edge portion of the unit display panel together with the common wiring. In particular, the width of the common wiring Vcom in the area between the pixel display portion and the edge portion of the unit display panel defined in the existing unit display panel has a sufficient resistance to drive the panel so that the width of the common wiring Vcom is approximately 1. Reduce to / 2 and fill the remaining space with odd and even gate wiring for MPS inspection.

In addition, the MPS inspection gate wiring is arranged in the area remaining between the pixel display portion defined inside the unit display panel and the edge portion of the unit display panel, so that the resistances of the two wirings can be set equally.

As described above, according to the MPS inspection wiring structure of the liquid crystal display device according to the present invention, the MPS inspection wiring is arranged inside the panel instead of the conventional method which has been designed outside the unit liquid crystal panel. By eliminating the problem, the detection power of MPS inspection and design can be improved. In particular, as shown in FIG. 8, even in the case of a small 14.0 inch model, even though there is little width W between the unit panels, the MPS inspection wiring is arranged inside the panel, so that the MPS inspection can be effectively performed. .

Therefore, it is possible to design the MPS when there is a lack of space due to the panel arrangement in the glass, and accordingly, the resistance design can be easily improved, thereby finally improving the detection power for the defect.

On the other hand, while described above with reference to a preferred embodiment of the present invention, those skilled in the art various modifications of the present invention without departing from the spirit and scope of the invention described in the claims below And can be changed.

Claims (9)

Gate wiring and data wiring formed of a plurality of odd and even wirings formed on a substrate, a thin film transistor formed at a point where the plurality of odd and even gate wirings and data wirings cross each other, and the gate wiring and data wiring A unit liquid crystal panel including a pixel display unit formed in the region formed therein; An odd gate wiring for MPS inspection connected to the odd gate wiring and disposed in the unit liquid crystal panel; An even gate wiring for MPS inspection connected to the even gate wiring and disposed in the unit liquid crystal panel; And And a common wiring disposed inside the unit liquid crystal panel. And the odd and even gate wirings for the MPS inspection and the common wiring are arranged at an outer portion of the pixel display unit provided in the unit liquid crystal panel. delete The MPS inspection wiring structure of the liquid crystal display device according to claim 1, wherein the odd and even gate wirings for the MPS inspection are disposed between a pixel display area provided inside the unit liquid crystal display panel and an edge portion of the unit liquid crystal display panel. . The MPS inspection wiring structure of claim 1, wherein the odd and even gate wirings for the MPS inspection are spaced apart from the common wiring. The MPS inspection wiring structure of a liquid crystal display device according to claim 1, wherein the odd and even gate wirings for the MPS inspection are electrically insulated from the common wiring. The unit liquid crystal display of claim 1, wherein the odd data wirings are connected to each other, and the odd data wirings for MPS inspection and the even data wirings are arranged on an outer portion of the pixel display unit provided inside the unit liquid crystal panel. MPS inspection wiring structure of the liquid crystal display device further comprises an even data wiring for MPS inspection disposed in the outer portion of the pixel display portion provided in the. delete The MPS inspection gate wiring for connecting the odd-numbered wirings and the MPS inspection gate wiring for even-numbered wirings are connected to the odd gate pads and the even gate pads for the MPS inspection, respectively, and the common wiring is connected to the MPS inspection. MPS inspection wiring structure of the liquid crystal display device, characterized in that connected to the common wiring pad. The liquid crystal display of claim 6, wherein the MPS inspection data wirings connecting the odd lines and the MPS inspection data wirings connecting the even lines are connected to the odd data pads and the even data pads, respectively. MPS inspection wiring structure of the device.

Images