KR101152819B1 - Method of manufacturing semiconductor device - Google Patents

Abstract

The present invention discloses a method of manufacturing a semiconductor device capable of forming fine contact holes in a narrowed active region according to a high integration trend. The disclosed method comprises the steps of providing a semiconductor substrate having a gate and a source / drain region; Forming a first interlayer insulating film on the semiconductor substrate; Forming a first buffer bit line covering a portion of the upper portion of the source region and a second buffer bit line covering a portion of the upper portion of the gate and the drain region adjacent thereto on the first interlayer insulating layer; Forming a second interlayer insulating film on the first interlayer insulating film including buffer bit lines; Etching the first and second interlayer dielectric layers to form a first contact hole exposing side surfaces and a source region of the first buffer bit line and a second contact hole exposing side surfaces and a drain region of the second buffer bit line; And a first metal wire contacting the side surface and the source region of the first buffer bit line through the first contact hole on the second interlayer insulating layer, and the side surface and the drain region of the second buffer bit line through the second contact hole. Forming a second metal wiring to be; characterized in that it comprises a.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view of a semiconductor device according to the prior art.

2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

3 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23: gate 24a: source region

24b: drain region 25: first interlayer insulating film

26a: first buffer bit line 26b: second buffer bit line

27: second interlayer insulating film 28a: first contact hole

28b: second contact hole 29a: first metal wiring

29b: second metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of forming fine contact holes for metal wiring in an active region narrowed according to a high integration trend.

As is well known, a bit line is formed to connect a gate and a source / drain region of a MOS transistor, and a metal wiring contact hole connected to the bit line is connected to an upper portion of the bit line to connect different transistors. Form in.

Hereinafter, a method of manufacturing a conventional semiconductor device will be described with reference to FIG. 1.

First, an isolation layer 12 defining an active region is formed on the semiconductor substrate 11, and gates 13 and source / drain regions 14a and 14b are formed on the active region. Subsequently, after depositing the first interlayer insulating film 15 on the substrate product including the gate 13, the first bit line exposing the source region 14a by etching the first interlayer insulating film 15 ( A second bit line 16b exposing 16a and the drain region 14b is formed, and a third bit line 16c in contact with the gate 13 is formed. Here, the second bit line 16b and the third bit line 16c are formed to be connected to each other on the first interlayer insulating film 15.

Next, after forming the second interlayer insulating layer 17 to cover the bit lines 16a, 16b, and 16c, the second interlayer insulating layer 17 is etched to contact the upper portion of the first bit line 16a. A second contact hole 18b is formed in contact with an upper portion of the third bit line 16c connected to the first contact hole 18a and the second bit line 16b. Subsequently, the contact holes 18a and 18b are filled to form metal wirings 19a and 19b including metal plugs.

However, as the semiconductor technology advances, the demand for miniaturization of the pattern and high precision of the pattern dimension is increasing, and as a result, the area of the active region in which the contact hole for metal wiring is to be formed is reduced.

Therefore, as a new exposure technique and an etching technique for forming a fine metallization contact hole formed in the narrowed active region are required, a huge investment of cost and time is required.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming fine contact holes for metal wiring in an active region narrowed according to a high integration trend.

A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate having a gate and a source / drain region; Forming a first interlayer insulating film on the semiconductor substrate; Forming a first buffer bit line covering a portion of the upper portion of the source region and a second buffer bit line covering a portion of the upper portion of the gate and the drain region adjacent thereto on the first interlayer insulating layer; Forming a second interlayer insulating film on the first interlayer insulating film including buffer bit lines; Etching the first and second interlayer dielectric layers to form a first contact hole exposing side surfaces and a source region of the first buffer bit line and a second contact hole exposing side surfaces and a drain region of the second buffer bit line; And a first metal wire contacting the side surface and the source region of the first buffer bit line through the first contact hole on the second interlayer insulating layer, and the side surface and the drain region of the second buffer bit line through the second contact hole. And forming a second metal wire to be contacted.

Here, the first buffer bit line and the second buffer bit line are formed of tungsten.

The second buffer bit line functions as a buffer when forming the second contact hole and as an input terminal of the gate.

The first buffer bit line and the second buffer bit line respectively reduce the size of the first contact hole contacting the source region and the size of the second contact hole contacting the drain region.

The first contact hole and the second contact hole are formed to be narrower from the top to the bottom.

In addition, in order to achieve the above object, the present invention provides a semiconductor substrate comprising a gate and a source / drain region; Forming a first interlayer insulating film on the semiconductor substrate; Forming a first buffer bit line covering a portion of the upper portion of the source region and a second buffer bit line covering a portion of the upper portion of the drain region on the first interlayer insulating layer, and forming a third buffer bit line in contact with the gate; Forming a second interlayer insulating film on the first interlayer insulating film including buffer bit lines; Etching the first and second interlayer dielectric layers to expose the first and second contact holes exposing the side and source regions of the first buffer bit line and the second and third contact holes exposing the side and drain regions of the second buffer bit line. Forming a third contact hole exposing the line; And a first metal wire contacting the side surface and the source region of the first buffer bit line through the first contact hole on the second interlayer insulating layer, and the side surface and the drain region of the second buffer bit line through the second contact hole. And forming a third metal wire contacted with the third buffer bit line through the second metal wire and the third contact hole.

Here, the first buffer bit line, the second buffer bit line, and the third buffer bit line are formed of tungsten.

The first buffer bit line and the second buffer bit line respectively reduce the size of the first contact hole contacting the source region and the size of the second contact hole contacting the drain region.

The first contact hole and the second contact hole are formed to be narrower from the top to the bottom.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described. Instead of forming a bit line to connect a gate and a source / drain region of a MOS transistor, the present invention forms a buffer bit line and uses a metal line connected to the buffer bit line. The contact holes are formed to be connected to the source / drain regions of the semiconductor substrate.

In addition, according to the present invention, the contact hole for metal wiring is formed to be narrower from the top to the bottom, thereby forming a fine contact hole in the active region narrowed according to the trend of high integration.

In detail, Figure 2 is a cross-sectional view for each process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, as follows.

Referring to FIG. 2, an isolation layer 22 defining an active region is formed on a semiconductor substrate 21, a gate 23 is formed on the active region, and a source is formed at both sides of the gate 23. / Drain regions 24a and 24b are formed. Subsequently, a first interlayer dielectric layer 25 is deposited on the substrate 21 including the gate 23, and then a part of the upper portion of the source region 24a is covered on the first interlayer dielectric layer 25. A second buffer bit line 26b covering the first buffer bit line 26a and the gate 23 and a part of the upper portion of the drain region 24b adjacent thereto is formed.

Here, the first buffer bit line 26a and the second buffer bit line 26b are formed of tungsten, and the first buffer bit line 26a is formed when a contact hole is formed on the source region 24a that is subsequently formed. Since it functions as a buffer, it is formed in a predetermined area of the contact hole on the source region 24a, and the second buffer bit line 26b functions as a buffer when forming a contact hole on a subsequent drain region 24b. 23 is formed by etching, and then extended in the direction of the drain region 24b.

Accordingly, the first and second buffer bit lines 26a and 26b serve as buffers for the metal wiring contact holes to be formed in the future, and also serve as signal transmission and input terminals of the gate 23. It is not necessary to form the bit line on the).

Next, after depositing a second interlayer insulating film 27 on the resultant formed first and second buffer bit lines (26a, 26b), the first and second interlayer insulating films (25, 27) are etched The first contact hole 28a exposing the side surface and the source region 24a of the first buffer bit line 26a is formed, and the side surface and drain region 24b of the second buffer bit line 26b are exposed. The second contact hole 28b is formed.

In this case, the contact holes 28a and 28b are formed to expose side surfaces of the first and second buffer bit lines 26a and 26b, thereby overlapping the ends of the first and second buffer bit lines 26a and 26b. Overlapping and contacting the buffer bit lines (26a, 26b) in the side, and is formed so that the width becomes narrower from the top to the bottom. Here, the first buffer bit line 26a and the second buffer bit line 26b are respectively the size of the first contact hole 28a contacting the source region 24a and the second contacting the drain region 24b. It serves to reduce the size of the contact hole (28b).

Accordingly, although the size of the upper portion of the contact holes 28a and 28b is the same as the conventional size, the size of the lower portion connected to the source / drain regions 24a and 24b decreases so that the fine contact hole 28a, 28b) is possible.

Subsequently, the first metal wiring 29a and the first metal contacting the side surface of the first buffer bit line 26a and the source region 24a on the second interlayer insulating layer 27 through the first contact hole 28a. A second metal wiring 29b is formed to contact the side of the second buffer bit line 26b and the drain region 24b through the second contact hole 28b.

Subsequently, although not shown, a dielectric film and a conductive film for a capacitor upper electrode are sequentially deposited, and then patterned to form a capacitor, and then a subsequent known process is performed to complete the semiconductor device.

In the present invention, each contact hole directly contacting the buffer bit lines without forming a bit line on the active area is formed directly on the active area, and the contact holes are formed to be narrower from the top to the bottom. As a result, minute contact holes can be formed on the active region.

Meanwhile, in the above-described embodiment of the present invention, the buffer bit line on the gate is formed to extend to the drain region, thereby forming two buffer bit lines including the buffer bit line on the source region. Fine contact holes may also be formed by separating the buffer bit lines on the source and drain regions and forming three buffer bit lines, respectively.

In detail, Figure 3 is a cross-sectional view for each process for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 3, an isolation layer 32 defining an active region is formed on a semiconductor substrate 31, a gate 33 is formed on the active region, and a source is formed at both sides of the gate 33. / Drain regions 34a and 34b are formed. Subsequently, after depositing the first interlayer dielectric layer 35 on the substrate 31 including the gate 33, a portion covering the upper portion of the source region 34a on the first interlayer dielectric layer 35 is formed. A third buffer bit line 36b covering a portion of the first buffer bit line 36a and an upper portion of the drain region 34b, and an upper portion of the gate 33 is etched to contact the gate 33 Buffer bit line 36c is formed.

Here, the first buffer bit line 36a, the second buffer bit line 36b, and the third buffer bit line 36c are formed of tungsten, and the first buffer bit line 36a is subsequently processed. Since a buffer function is formed when the contact hole is formed on the source region 34a, the buffer layer is formed in a predetermined contact hole region on the source region 34a, and the second buffer bit line 36b is formed on the drain region 34b which is subsequently formed. Since a buffer function is formed in forming the contact hole, the contact hole is formed in a predetermined region of the contact hole on the drain region 34b.

Accordingly, the first and second buffer bit lines 36a and 36b function as buffers for the contact holes for metal wirings to be formed in the future, and also serve as a signal transfer function and an input terminal of the gate 33. It is not necessary to form the bit line on the).

Next, after depositing the second interlayer insulating film 37 on the resultant formed first, second and third buffer bit line (36a, 36b, 36c), the first, second interlayer insulating film (35, 37 is etched to expose the first contact hole 38a and the second buffer bitline 36b and the side and drain regions 34b that expose the side and source regions 34a of the first buffer bit line 36a. The third contact hole 38c exposing the second contact hole 38b and the third buffer bit line 36c is formed.

In this case, the first and second contact holes 38a and 38b are formed to expose side surfaces of the first and second buffer bit lines 36a and 36b so that the first and second buffer bit lines 36a and 36b are exposed. Overlap is formed at the end of the in contact with the buffer bit lines (36a, 36b) in the side, and is formed so that the width becomes narrower from the top to the bottom. In addition, the third contact hole 38c is formed to contact the third buffer bit line 36c which is in contact with the gate 33.

Here, the first buffer bit line 36a and the second buffer bit line 36b are respectively the size of the first contact hole 38a in contact with the source region 34a and the second contact with the drain region 34b. It serves to reduce the size of the contact hole 38b.

Accordingly, the size of the upper portions of the first and second contact holes 38a and 38b is the same as that of the conventional size, but the size of the lower portion connected to the source / drain regions 34a and 34b is reduced to reduce the size of the active region. It is possible to implement the fine contact holes 38a and 38b.

Subsequently, the first metal wiring 39a and the first metal contacting the side surface of the first buffer bit line 36a and the source region 34a are formed on the second interlayer insulating layer 37 through the first contact hole 38a. The third buffer bit line (the third metal wiring 39b and the third contact hole 38c contacted with the side and drain regions 34b of the second buffer bit line 36b through the second contact hole 38b). A third metal wiring 39c in contact with 36c is formed.

Subsequently, although not shown, a dielectric film and a conductive film for a capacitor upper electrode are sequentially deposited, and then patterned to form a capacitor, and then a subsequent known process is performed to complete the semiconductor device.

Here, the present invention forms three buffer bit lines by separately forming the buffer bit lines on the gate and the source / drain regions, and contacts each contacting the buffer bit lines without forming the bit lines on the active region. By forming the holes directly on the active region, fine contact holes can be formed on the active region.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention forms a buffer pattern instead of forming a bit line to connect a gate and a source / drain region when fabricating a semiconductor device, and forms a contact hole for a metal wiring connected to the buffer pattern in a source / It is formed to be connected to the drain region and the metal contact hole is formed to be narrower from the top to the bottom to form a fine contact hole in the narrowed active region according to the high integration trend without new equipment and technology.

Claims (9)

Providing a semiconductor substrate having a gate and a source / drain region; Forming a first interlayer insulating film on the semiconductor substrate; Forming a first buffer bit line covering a portion of an upper portion of a source region and a second buffer bit line covering a portion of an upper portion of an upper portion of a gate and an adjacent drain region on the first interlayer insulating layer; Forming a second interlayer insulating film on the first interlayer insulating film including the buffer bit lines; Etching the first and second interlayer insulating layers to form a first contact hole exposing side surfaces and a source region of a first buffer bit line and a second contact hole exposing side surfaces and a drain region of a second buffer bit line; ; And A first metal wiring contacting the side surface and the source region of the first buffer bit line through the first contact hole on the second interlayer insulating layer, and the side surface and the drain region of the second buffer bit line through the second contact hole. Forming a second metal wiring; Method of manufacturing a semiconductor device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And the first buffer bit line and the second buffer bit line are formed of tungsten. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, And the second buffer bit line functions as an input terminal of a gate. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The first buffer bit line and the second buffer bit line respectively function as signal transmission, and the first buffer bit line functions to reduce the size of the first contact hole contacting the source region, and the second buffer bit line. Is a function of reducing the size of the second contact hole in contact with the drain region. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein The first contact hole and the second contact hole is a manufacturing method of a semiconductor device, characterized in that the width is narrowed from the top to the bottom. Providing a semiconductor substrate having a gate and a source / drain region; Forming a first interlayer insulating film on the semiconductor substrate; Forming a first buffer bit line covering a portion of the upper portion of the source region and a second buffer bit line covering a portion of the upper portion of the drain region on the first interlayer insulating layer, and forming a third buffer bit line in contact with the gate; ; Forming a second interlayer insulating film on the first interlayer insulating film including the buffer bit lines; Etching the first and second interlayer insulating layers to expose the first and second contact holes exposing side surfaces and source regions of the first buffer bit line and the second and second contact holes exposing side surfaces and drain regions of the second buffer bit line. Forming a third contact hole exposing the bit line; And A first metal wiring contacting the side surface and the source region of the first buffer bit line through the first contact hole on the second interlayer insulating layer, and the side surface and the drain region of the second buffer bit line through the second contact hole. Forming a third metal wire to contact the third buffer bit line through the second metal wire and the third contact hole; Method of manufacturing a semiconductor device comprising a. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, And the first buffer bit line, the second buffer bit line, and the third buffer bit line are formed of tungsten. Claim 8 was abandoned when the registration fee was paid. The method of claim 6, The first buffer bit line and the second buffer bit line respectively function as signal transmission, and the first buffer bit line functions to reduce the size of the first contact hole contacting the source region, and the second buffer bit line. Is a function of reducing the size of the second contact hole in contact with the drain region. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8,

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